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PATCH: Fix popcnt for SSE4.2/ABM


I am checking in this patch to fix popcnt for SSE4.2/ABM.


H.J.
---
gas/testsuite/

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-5.d: New file.
	* gas/i386/arch-5.s: Likewise.
	* gas/i386/arch-6.d: Likewise.
	* gas/i386/arch-6.s: Likewise.
	* gas/i386/arch-7.d: Likewise.
	* gas/i386/arch-7.s: Likewise.
	* gas/i386/arch-8.d: Likewise.
	* gas/i386/arch-8.s: Likewise.

	* gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.

opcodes/

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

--- binutils/gas/testsuite/gas/i386/arch-5.d.popcnt	2008-01-02 19:40:48.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-5.d	2008-01-02 21:14:43.000000000 -0800
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 arch 5
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+#pass
--- binutils/gas/testsuite/gas/i386/arch-5.s.popcnt	2008-01-02 19:40:51.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-5.s	2008-01-02 21:11:45.000000000 -0800
@@ -0,0 +1,5 @@
+# Test .arch .sse4.2
+.arch generic32
+.arch .sse4.2
+popcnt	%ecx,%ebx
+crc32	%ecx,%ebx
--- binutils/gas/testsuite/gas/i386/arch-6.d.popcnt	2008-01-02 19:40:57.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-6.d	2008-01-02 21:15:02.000000000 -0800
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 arch 6
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+#pass
--- binutils/gas/testsuite/gas/i386/arch-6.s.popcnt	2008-01-02 19:40:54.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-6.s	2008-01-02 19:50:16.000000000 -0800
@@ -0,0 +1,5 @@
+# Test .arch .sse4
+.arch generic32
+.arch .sse4
+popcnt	%ecx,%ebx
+crc32	%ecx,%ebx
--- binutils/gas/testsuite/gas/i386/arch-7.d.popcnt	2008-01-02 21:09:48.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-7.d	2008-01-02 21:15:22.000000000 -0800
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 arch 7
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
+#pass
--- binutils/gas/testsuite/gas/i386/arch-7.s.popcnt	2008-01-02 21:09:39.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-7.s	2008-01-02 19:50:37.000000000 -0800
@@ -0,0 +1,5 @@
+# Test .arch .abm
+.arch generic32
+.arch .abm
+popcnt	%ecx,%ebx
+lzcnt	%ecx,%ebx
--- binutils/gas/testsuite/gas/i386/arch-8.d.popcnt	2008-01-02 21:09:45.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-8.d	2008-01-02 21:15:46.000000000 -0800
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: i386 arch 8
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[a-f0-9]+:	0f 7a 12 ca          	frczss %xmm2,%xmm1
+#pass
--- binutils/gas/testsuite/gas/i386/arch-8.s.popcnt	2008-01-02 21:09:42.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/arch-8.s	2008-01-02 19:52:03.000000000 -0800
@@ -0,0 +1,5 @@
+# Test .arch .sse5
+.arch generic32
+.arch .sse5
+popcnt	%ecx,%ebx
+frczss	%xmm2, %xmm1
--- binutils/gas/testsuite/gas/i386/i386.exp.popcnt	2007-12-28 08:04:51.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/i386.exp	2008-01-02 19:49:40.000000000 -0800
@@ -102,6 +102,10 @@ if [expr ([istarget "i*86-*-*"] ||  [ist
     run_dump_test "arch-2"
     run_dump_test "arch-3"
     run_dump_test "arch-4"
+    run_dump_test "arch-5"
+    run_dump_test "arch-6"
+    run_dump_test "arch-7"
+    run_dump_test "arch-8"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
--- binutils/opcodes/i386-gen.c.popcnt	2008-01-02 19:29:11.000000000 -0800
+++ binutils/opcodes/i386-gen.c	2008-01-02 21:13:36.000000000 -0800
@@ -81,7 +81,7 @@ static initializer cpu_flag_init [] =
   { "CPU_K8_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
   { "CPU_AMDFAM10_FLAGS",
-    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
+    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE4_2_Or_ABM|CpuLM" },
   { "CPU_MMX_FLAGS",
     "CpuMMX" },
   { "CPU_SSE_FLAGS",
@@ -95,7 +95,7 @@ static initializer cpu_flag_init [] =
   { "CPU_SSE4_1_FLAGS",
     "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_1_Or_5" },
   { "CPU_SSE4_2_FLAGS",
-    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5" },
+    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM" },
   { "CPU_3DNOW_FLAGS",
     "CpuMMX|Cpu3dnow" },
   { "CPU_3DNOWA_FLAGS",
@@ -107,9 +107,9 @@ static initializer cpu_flag_init [] =
   { "CPU_SSE4A_FLAGS",
     "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
   { "CPU_ABM_FLAGS",
-    "CpuABM" },
+    "CpuABM|CpuSSE4_2_Or_ABM" },
   { "CPU_SSE5_FLAGS",
-    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5"},
+    "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM"},
 };
 
 static initializer operand_type_init [] =
@@ -235,6 +235,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuSSE4a),
   BITFIELD (CpuSSE5),
   BITFIELD (CpuSSE4_1_Or_5),
+  BITFIELD (CpuSSE4_2_Or_ABM),
   BITFIELD (Cpu3dnow),
   BITFIELD (Cpu3dnowA),
   BITFIELD (CpuPadLock),
--- binutils/opcodes/i386-opc.h.popcnt	2008-01-02 19:29:11.000000000 -0800
+++ binutils/opcodes/i386-opc.h	2008-01-02 19:42:45.000000000 -0800
@@ -84,8 +84,10 @@
 #define CpuSSE5		(CpuSSE4_2 + 1)
 /* SSE4.1 or SSE5 support required */
 #define CpuSSE4_1_Or_5	(CpuSSE5 + 1)
+/* SSE4.2 or ABM support required */
+#define CpuSSE4_2_Or_ABM (CpuSSE4_1_Or_5 + 1)
 /* 64bit support available, used by -march= in assembler.  */
-#define CpuLM		(CpuSSE4_1_Or_5 + 1)
+#define CpuLM		(CpuSSE4_2_Or_ABM + 1)
 /* 64bit support required  */
 #define Cpu64		(CpuLM + 1)
 /* Not supported in the 64bit mode  */
@@ -135,6 +137,7 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_2:1;
       unsigned int cpusse5:1;
       unsigned int cpusse4_1_or_5:1;
+      unsigned int cpusse4_2_or_abm:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
--- binutils/opcodes/i386-opc.tbl.popcnt	2008-01-02 19:29:11.000000000 -0800
+++ binutils/opcodes/i386-opc.tbl	2008-01-02 19:45:14.000000000 -0800
@@ -1459,7 +1459,7 @@ insertq, 2, 0xf20f79, None, 2, CpuSSE4a,
 insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }
 
 // ABM instructions
-popcnt, 2, 0xf30fb8, None, 2, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+popcnt, 2, 0xf30fb8, None, 2, CpuSSE4_2_Or_ABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 lzcnt, 2, 0xf30fbd, None, 2, CpuABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 
 // SSE5 instructions


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