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Common SSE4.1/SSE5 insns broken
- From: Jakub Jelinek <jakub at redhat dot com>
- To: "H.J. Lu" <hjl at lucon dot org>
- Cc: binutils at sources dot redhat dot com
- Date: Fri, 28 Dec 2007 10:10:34 +0100
- Subject: Common SSE4.1/SSE5 insns broken
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
Hi!
Doesn't CpuSSE4_1|CpuSSE5 mean it requires SSE4.1 AND SSE5 rather than
SSE4.1 OR SSE5?
ptest, 2, 0x660f3817, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
Say e.g.:
.arch generic64
.arch .sse5
ptest %xmm1,%xmm0
frczss %xmm2, %xmm1
fails to assemble with
Warning: `ptest' is not supported on `generic64.sse5'
Error: suffix or operands invalid for `ptest'
and likewise for .arch .sse4.1. Works if both .sse5 and .sse4.1
are present. Do we need yet another bit for the common
SSE4.1 / SSE5 instructions, which .sse4.1, .sse5 would
both set (and be set in unknown too)?
Jakub