This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
PATCH: Turn SYSV386_COMPAT into run-time options
- From: "H.J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Fri, 21 Dec 2007 15:08:59 -0800
- Subject: PATCH: Turn SYSV386_COMPAT into run-time options
This patch turns SYSV386_COMPAT it into run-time options for x86
disassembler. I will post a similar patch for assembler later.
H.J.
---
binutils/doc/
2007-12-21 H.J. Lu <hongjiu.lu@intel.com>
* doc/binutils.texi: Document the new intel-compatible and
intel-compatible options for i386 disassembler.
gas/testsuite/
2007-12-21 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/compat.d: New file.
* gas/i386/compat.s: Likewise.
* gas/i386/i386.exp: Run compat.
opcodes/
2007-12-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (intel_compatible): New.
(print_i386_disassembler_options): Display att-compatible and
intel-compatible options.
(print_insn): Handle att-compatible and intel-compatible.
(float_reg): Replace SYSV386_COMPAT with "!M" and "M".
(putop): Handle "!M" and "M".
--- binutils/binutils/doc/binutils.texi.compat 2007-11-07 15:37:22.000000000 -0800
+++ binutils/binutils/doc/binutils.texi 2007-12-21 14:45:28.000000000 -0800
@@ -1801,7 +1801,11 @@ switch, but allow finer grained control.
following may be specified as a comma separated string.
@option{x86-64}, @option{i386} and @option{i8086} select disassembly for
the given architecture. @option{intel} and @option{att} select between
-intel syntax mode and AT&T syntax mode. @option{addr64}, @option{addr32},
+intel syntax mode and AT&T syntax mode.
+@option{intel-compatible} and @option{att-compatible} select between
+intel mnemonic mode and AT&T mnemonic mode. @option{intel-compatible}
+implies @option{intel} and @option{att-compatible} implies @option{att}.
+@option{addr64}, @option{addr32},
@option{addr16}, @option{data32} and @option{data16} specify the default
address size and operand size. These four options will be overridden if
@option{x86-64}, @option{i386} or @option{i8086} appear later in the
--- binutils/gas/testsuite/gas/i386/compat.d.compat 2007-12-21 14:23:52.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/compat.d 2007-12-21 14:56:01.000000000 -0800
@@ -0,0 +1,25 @@
+#objdump: -d -Matt-compatible
+#name: i386 float sysv compatible
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ ]*[a-f0-9]+: dc e3 fsub %st,%st\(3\)
+[ ]*[a-f0-9]+: de e1 fsubp %st,%st\(1\)
+[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
+[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc eb fsubr %st,%st\(3\)
+[ ]*[a-f0-9]+: de e9 fsubrp %st,%st\(1\)
+[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
+[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc f3 fdiv %st,%st\(3\)
+[ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
+[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
+[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
+[ ]*[a-f0-9]+: dc fb fdivr %st,%st\(3\)
+[ ]*[a-f0-9]+: de f9 fdivrp %st,%st\(1\)
+[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
+[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
+#pass
--- binutils/gas/testsuite/gas/i386/compat.s.compat 2007-12-21 14:23:54.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/compat.s 2007-12-21 14:28:26.000000000 -0800
@@ -0,0 +1,18 @@
+# Check SYSV compatible instructions.
+ .text
+ fsub %st,%st(3)
+ fsubp
+ fsubp %st(3)
+ fsubp %st,%st(3)
+ fsubr %st,%st(3)
+ fsubrp
+ fsubrp %st(3)
+ fsubrp %st,%st(3)
+ fdiv %st,%st(3)
+ fdivp
+ fdivp %st(3)
+ fdivp %st,%st(3)
+ fdivr %st,%st(3)
+ fdivrp
+ fdivrp %st(3)
+ fdivrp %st,%st(3)
--- binutils/gas/testsuite/gas/i386/i386.exp.compat 2007-11-01 09:27:21.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/i386.exp 2007-12-21 14:24:29.000000000 -0800
@@ -96,6 +96,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "reg"
run_dump_test "reg-intel"
run_dump_test "i386"
+ run_dump_test "compat"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
--- binutils/opcodes/i386-dis.c.compat 2007-11-01 09:27:21.000000000 -0700
+++ binutils/opcodes/i386-dis.c 2007-12-21 14:59:21.000000000 -0800
@@ -730,6 +730,7 @@ struct dis386 {
'J' => print 'l'
'K' => print 'd' or 'q' if rex prefix is present.
'L' => print 'l' if suffix_always is true
+ 'M' => print 'r' if intel_compatible is false.
'N' => print 'n' if instruction has no wait "prefix"
'O' => print 'd' or 'o' (or 'q' in Intel mode)
'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
@@ -746,6 +747,7 @@ struct dis386 {
'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
suffix_always is true.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
+ '!' => change condition from true to false or from false to true.
Many of the above letters print nothing in Intel mode. See "putop"
for the details.
@@ -5058,6 +5060,7 @@ static bfd_vma start_pc;
*/
static char intel_syntax;
+static char intel_compatible = !SYSV386_COMPAT;
static char open_char;
static char close_char;
static char separator_char;
@@ -5102,6 +5105,10 @@ with the -M switch (multiple options sho
fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
+ fprintf (stream, _(" att-compatible\n"
+ " Display instruction in AT&T mnemonic\n"));
+ fprintf (stream, _(" intel-compatible\n"
+ " Display instruction in Intel mnemonic\n"));
fprintf (stream, _(" addr64 Assume 64bit address size\n"));
fprintf (stream, _(" addr32 Assume 32bit address size\n"));
fprintf (stream, _(" addr16 Assume 16bit address size\n"));
@@ -5245,10 +5252,14 @@ print_insn (bfd_vma pc, disassemble_info
else if (CONST_STRNEQ (p, "intel"))
{
intel_syntax = 1;
+ if (CONST_STRNEQ (p + 5, "-compatible"))
+ intel_compatible = 0;
}
else if (CONST_STRNEQ (p, "att"))
{
intel_syntax = 0;
+ if (CONST_STRNEQ (p + 5, "-compatible"))
+ intel_compatible = 1;
}
else if (CONST_STRNEQ (p, "addr"))
{
@@ -5790,17 +5801,10 @@ static const struct dis386 float_reg[][8
{ "fmul", { STi, ST } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
-#if SYSV386_COMPAT
- { "fsub", { STi, ST } },
- { "fsubr", { STi, ST } },
- { "fdiv", { STi, ST } },
- { "fdivr", { STi, ST } },
-#else
- { "fsubr", { STi, ST } },
- { "fsub", { STi, ST } },
- { "fdivr", { STi, ST } },
- { "fdiv", { STi, ST } },
-#endif
+ { "fsub!M", { STi, ST } },
+ { "fsubM", { STi, ST } },
+ { "fdiv!M", { STi, ST } },
+ { "fdivM", { STi, ST } },
},
/* dd */
{
@@ -5819,17 +5823,10 @@ static const struct dis386 float_reg[][8
{ "fmulp", { STi, ST } },
{ "(bad)", { XX } },
{ FGRPde_3 },
-#if SYSV386_COMPAT
- { "fsubp", { STi, ST } },
- { "fsubrp", { STi, ST } },
- { "fdivp", { STi, ST } },
- { "fdivrp", { STi, ST } },
-#else
- { "fsubrp", { STi, ST } },
- { "fsubp", { STi, ST } },
- { "fdivrp", { STi, ST } },
- { "fdivp", { STi, ST } },
-#endif
+ { "fsub!Mp", { STi, ST } },
+ { "fsubMp", { STi, ST } },
+ { "fdiv!Mp", { STi, ST } },
+ { "fdivMp", { STi, ST } },
},
/* df */
{
@@ -5967,6 +5964,7 @@ putop (const char *template, int sizefla
{
const char *p;
int alt = 0;
+ int cond = 1;
for (p = template; *p; p++)
{
@@ -5975,6 +5973,9 @@ putop (const char *template, int sizefla
default:
*obufp++ = *p;
break;
+ case '!':
+ cond = 0;
+ break;
case '{':
alt = 0;
if (intel_syntax)
@@ -6114,6 +6115,10 @@ putop (const char *template, int sizefla
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'l';
break;
+ case 'M':
+ if (intel_compatible != cond)
+ *obufp++ = 'r';
+ break;
case 'N':
if ((prefixes & PREFIX_FWAIT) == 0)
*obufp++ = 'n';