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PATCH: Upated x86 assembler
- From: "H.J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Thu, 1 Nov 2007 09:23:21 -0700
- Subject: PATCH: Upated x86 assembler
I am checking in this patch to use i386_opcode_modifier for suffix
checking.
H.J.
----
gas/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Check addrprefixop0 to
see if the address size override prefix changes the size of the
first operand.
(check_byte_reg): Don't warn if byteokintel is set.
(check_long_reg): Set i.suffix to QWORD_MNEM_SUFFIX if toqword
is set.
(check_qword_reg): Set i.suffix to LONG_MNEM_SUFFIX if todword
is set.
gas/testsuite/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.d: New.
* gas/i386/i386.s: Likewise.
* gas/i386/i386.exp: Run i386.
* gas/i386/x86_64.s: Add tests for movsx, movsbl, movsbq,
movsbw, movswl, movswq, movzx, movzb, movzbl, movzbq,
movzbw, movzwl and movzwq.
* gas/i386/x86_64.d: Updated.
opcodes/
2007-11-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword,
ToQword and AddrPrefixOp0.
* i386-opc.h (ByteOkIntel): New.
(ToDword): Likewise.
(ToQword): Likewise.
(AddrPrefixOp0): Likewise.
(IsPrefix): Updated.
(i386_opcode_modifier): Add byteokintel, todword, toqword
and addrprefixop0.
* i386-opc.tbl (cvtss2si): Add ToQword.
(cvttss2si): Likewise.
(cvtsd2si): Add ToDword.
(cvttsd2si): Likewise.
(monitor): Add AddrPrefixOp0.
(invlpga): Likewise.
(vmload): Likewise.
(vmrun): Likewise.
(vmsave): Likewise.
(pextrb): Add ByteOkIntel.
(pinsrb): Likewise.
* i386-tbl.h: Regenerated.
--- binutils/gas/config/tc-i386.c.suffix 2007-10-30 11:48:39.000000000 -0700
+++ binutils/gas/config/tc-i386.c 2007-11-01 08:56:01.000000000 -0700
@@ -3492,17 +3492,10 @@ process_suffix (void)
/* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway. */
- if (i.tm.base_opcode == 0x0f01
- && (i.tm.extension_opcode == 0xc8
- || i.tm.extension_opcode == 0xd8
- || i.tm.extension_opcode == 0xda
- || i.tm.extension_opcode == 0xdb
- || i.tm.extension_opcode == 0xdf))
- {
- /* monitor in SSE3 is a very special case. The default size
- of AX is the size of mode. The address size override
- prefix will change the size of AX. It is also true for
- invlpga, vmload, vmrun and vmsave in SVME. */
+ if (i.tm.opcode_modifier.addrprefixop0)
+ {
+ /* The address size override prefix changes the size of the
+ first operand. */
if ((flag_code == CODE_32BIT
&& i.op->regs[0].reg_type.bitfield.reg16)
|| (flag_code != CODE_32BIT
@@ -3569,16 +3562,8 @@ check_byte_reg (void)
if (i.types[op].bitfield.reg8)
continue;
- /* movzx, movsx, pextrb and pinsrb should not generate this
- warning. */
- if (intel_syntax
- && (i.tm.base_opcode == 0xfb7
- || i.tm.base_opcode == 0xfb6
- || i.tm.base_opcode == 0x63
- || i.tm.base_opcode == 0xfbe
- || i.tm.base_opcode == 0xfbf
- || i.tm.base_opcode == 0x660f3a14
- || i.tm.base_opcode == 0x660f3a20))
+ /* Don't generate this warning if not needed. */
+ if (intel_syntax && i.tm.opcode_modifier.byteokintel)
continue;
/* crc32 doesn't generate this warning. */
@@ -3690,12 +3675,10 @@ check_long_reg (void)
|| i.tm.operand_types[op].bitfield.acc))
{
if (intel_syntax
- && (i.tm.base_opcode == 0xf30f2d
- || i.tm.base_opcode == 0xf30f2c)
+ && i.tm.opcode_modifier.toqword
&& !i.types[0].bitfield.regxmm)
{
- /* cvtss2si/cvttss2si convert DWORD memory to Reg64. We
- want REX byte. */
+ /* Convert to QWORD. We want REX byte. */
i.suffix = QWORD_MNEM_SUFFIX;
}
else
@@ -3738,12 +3721,10 @@ check_qword_reg (void)
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
if (intel_syntax
- && (i.tm.base_opcode == 0xf20f2d
- || i.tm.base_opcode == 0xf20f2c)
+ && i.tm.opcode_modifier.todword
&& !i.types[0].bitfield.regxmm)
{
- /* cvtsd2si/cvttsd2si convert QWORD memory to Reg32. We
- don't want REX byte. */
+ /* Convert to DWORD. We don't want REX byte. */
i.suffix = LONG_MNEM_SUFFIX;
}
else
--- binutils/gas/testsuite/gas/i386/i386.d.suffix 2007-11-01 08:56:01.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/i386.d 2007-11-01 08:56:01.000000000 -0700
@@ -0,0 +1,27 @@
+#as: -J
+#objdump: -dw
+#name: i386
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.*>:
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
+[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
--- binutils/gas/testsuite/gas/i386/i386.exp.suffix 2007-10-10 08:49:17.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/i386.exp 2007-11-01 08:56:02.000000000 -0700
@@ -95,6 +95,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "mem-intel"
run_dump_test "reg"
run_dump_test "reg-intel"
+ run_dump_test "i386"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
--- binutils/gas/testsuite/gas/i386/i386.s.suffix 2007-11-01 08:56:02.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/i386.s 2007-11-01 08:56:02.000000000 -0700
@@ -0,0 +1,26 @@
+# i386 instructions
+ .text
+
+ movsx (%eax), %edx
+ movsx (%eax), %dx
+ movsbl (%eax), %edx
+ movsbw (%eax), %dx
+ movsbl (%eax), %edx
+ movswl (%eax), %edx
+
+ movzx (%eax), %edx
+ movzx (%eax), %dx
+ movzb (%eax), %edx
+ movzb (%eax), %dx
+ movzbl (%eax), %edx
+ movzbw (%eax), %dx
+ movzwl (%eax), %edx
+
+ .intel_syntax noprefix
+ movsx edx,BYTE PTR [eax]
+ movsx dx,BYTE PTR [eax]
+ movsx edx,WORD PTR [eax]
+
+ movzx edx,BYTE PTR [eax]
+ movzx dx,BYTE PTR [eax]
+ movzx edx,WORD PTR [eax]
--- binutils/gas/testsuite/gas/i386/x86_64.d.suffix 2007-04-26 21:22:14.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/x86_64.d 2007-11-01 08:56:02.000000000 -0700
@@ -1,161 +1,191 @@
#as: -J
#objdump: -dw
-#name: i386 x86_64
+#name: x86_64
#stderr: x86_64.e
.*: +file format .*
Disassembly of section .text:
0+ <.*>:
-[ ]+0: 01 ca[ ]+add[ ]+%ecx,%edx
-[ ]+2: 44 01 ca[ ]+add[ ]+%r9d,%edx
-[ ]+5: 41 01 ca[ ]+add[ ]+%ecx,%r10d
-[ ]+8: 48 01 ca[ ]+add[ ]+%rcx,%rdx
-[ ]+b: 4d 01 ca[ ]+add[ ]+%r9,%r10
-[ ]+e: 41 01 c0[ ]+add[ ]+%eax,%r8d
-[ ]+11: 66 41 01 c0[ ]+add[ ]+%ax,%r8w
-[ ]+15: 49 01 c0[ ]+add[ ]+%rax,%r8
-[ ]+18: 05 11 22 33 44[ ]+add[ ]+\$0x44332211,%eax
-[ ]+1d: 48 05 11 22 33 f4[ ]+add[ ]+\$0xf+4332211,%rax
-[ ]+23: 66 05 33 44[ ]+add[ ]+\$0x4433,%ax
-[ ]+27: 48 05 11 22 33 44[ ]+add[ ]+\$0x44332211,%rax
-[ ]+2d: 00 ca[ ]+add[ ]+%cl,%dl
-[ ]+2f: 00 f7[ ]+add[ ]+%dh,%bh
-[ ]+31: 40 00 f7[ ]+add[ ]+%sil,%dil
-[ ]+34: 41 00 f7[ ]+add[ ]+%sil,%r15b
-[ ]+37: 44 00 f7[ ]+add[ ]+%r14b,%dil
-[ ]+3a: 45 00 f7[ ]+add[ ]+%r14b,%r15b
-[ ]+3d: 50[ ]+push[ ]+%rax
-[ ]+3e: 41 50[ ]+push[ ]+%r8
-[ ]+40: 41 59[ ]+pop[ ]+%r9
-[ ]+42: 04 11[ ]+add[ ]+\$0x11,%al
-[ ]+44: 80 c4 11[ ]+add[ ]+\$0x11,%ah
-[ ]+47: 40 80 c4 11[ ]+add[ ]+\$0x11,%spl
-[ ]+4b: 41 80 c0 11[ ]+add[ ]+\$0x11,%r8b
-[ ]+4f: 41 80 c4 11[ ]+add[ ]+\$0x11,%r12b
-[ ]+53: 0f 20 c0[ ]+mov[ ]+%cr0,%rax
-[ ]+56: 41 0f 20 c0[ ]+mov[ ]+%cr0,%r8
-[ ]+5a: 44 0f 20 c0[ ]+mov[ ]+%cr8,%rax
-[ ]+5e: 44 0f 22 c0[ ]+mov[ ]+%rax,%cr8
-[ ]+62: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
-[ ]+65: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
-[ ]+68: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
-[ ]+6b: b0 11[ ]+mov[ ]+\$0x11,%al
-[ ]+6d: b4 11[ ]+mov[ ]+\$0x11,%ah
-[ ]+6f: 40 b4 11[ ]+mov[ ]+\$0x11,%spl
-[ ]+72: 41 b4 11[ ]+mov[ ]+\$0x11,%r12b
-[ ]+75: b8 44 33 22 11[ ]+mov[ ]+\$0x11223344,%eax
-[ ]+7a: 41 b8 44 33 22 11[ ]+mov[ ]+\$0x11223344,%r8d
-[ ]+80: 48 b8 88 77 66 55 44 33 22 11 mov[ ]+\$0x1122334455667788,%rax
-[ ]+8a: 49 b8 88 77 66 55 44 33 22 11 mov[ ]+\$0x1122334455667788,%r8
-[ ]+94: 03 00[ ]+add[ ]+\(%rax\),%eax
-[ ]+96: 41 03 00[ ]+add[ ]+\(%r8\),%eax
-[ ]+99: 45 03 00[ ]+add[ ]+\(%r8\),%r8d
-[ ]+9c: 49 03 00[ ]+add[ ]+\(%r8\),%rax
-[ ]+9f: 03 05 22 22 22 22[ ]+add[ ]+0x22222222\(%rip\),%eax.*
-[ ]+a5: 03 45 00[ ]+add[ ]+0x0\(%rbp\),%eax
-[ ]+a8: 03 04 25 22 22 22 22 add[ ]+0x22222222,%eax
-[ ]+af: 41 03 45 00[ ]+add[ ]+0x0\(%r13\),%eax
-[ ]+b3: 03 04 80[ ]+add[ ]+\(%rax,%rax,4\),%eax
-[ ]+b6: 41 03 04 80[ ]+add[ ]+\(%r8,%rax,4\),%eax
-[ ]+ba: 45 03 04 80[ ]+add[ ]+\(%r8,%rax,4\),%r8d
-[ ]+be: 43 03 04 80[ ]+add[ ]+\(%r8,%r8,4\),%eax
-[ ]+c2: 46 01 04 81[ ]+add[ ]+%r8d,\(%rcx,%r8,4\)
-[ ]+c6: 03 14 c0[ ]+add[ ]+\(%rax,%rax,8\),%edx
-[ ]+c9: 03 14 c8[ ]+add[ ]+\(%rax,%rcx,8\),%edx
-[ ]+cc: 03 14 d0[ ]+add[ ]+\(%rax,%rdx,8\),%edx
-[ ]+cf: 03 14 d8[ ]+add[ ]+\(%rax,%rbx,8\),%edx
-[ ]+d2: 03 10[ ]+add[ ]+\(%rax\),%edx
-[ ]+d4: 03 14 e8[ ]+add[ ]+\(%rax,%rbp,8\),%edx
-[ ]+d7: 03 14 f0[ ]+add[ ]+\(%rax,%rsi,8\),%edx
-[ ]+da: 03 14 f8[ ]+add[ ]+\(%rax,%rdi,8\),%edx
-[ ]+dd: 42 03 14 c0[ ]+add[ ]+\(%rax,%r8,8\),%edx
-[ ]+e1: 42 03 14 c8[ ]+add[ ]+\(%rax,%r9,8\),%edx
-[ ]+e5: 42 03 14 d0[ ]+add[ ]+\(%rax,%r10,8\),%edx
-[ ]+e9: 42 03 14 d8[ ]+add[ ]+\(%rax,%r11,8\),%edx
-[ ]+ed: 42 03 14 e0[ ]+add[ ]+\(%rax,%r12,8\),%edx
-[ ]+f1: 42 03 14 e8[ ]+add[ ]+\(%rax,%r13,8\),%edx
-[ ]+f5: 42 03 14 f0[ ]+add[ ]+\(%rax,%r14,8\),%edx
-[ ]+f9: 42 03 14 f8[ ]+add[ ]+\(%rax,%r15,8\),%edx
-[ ]+fd: 83 c1 11[ ]+add[ ]+\$0x11,%ecx
- 100: 83 00 11[ ]+addl[ ]+\$0x11,\(%rax\)
- 103: 48 83 00 11[ ]+addq[ ]+\$0x11,\(%rax\)
- 107: 41 83 00 11[ ]+addl[ ]+\$0x11,\(%r8\)
- 10b: 83 04 81 11[ ]+addl[ ]+\$0x11,\(%rcx,%rax,4\)
- 10f: 41 83 04 81 11[ ]+addl[ ]+\$0x11,\(%r9,%rax,4\)
- 114: 42 83 04 81 11[ ]+addl[ ]+\$0x11,\(%rcx,%r8,4\)
- 119: 83 05 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rip\).*
- 120: 48 83 05 22 22 22 22 33 addq[ ]+\$0x33,0x22222222\(%rip\).*
- 128: 81 05 22 22 22 22 33 33 33 33 addl[ ]+\$0x33333333,0x22222222\(%rip\).*
- 132: 48 81 05 22 22 22 22 33 33 33 33 addq[ ]+\$0x33333333,0x22222222\(%rip\).*
- 13d: 83 04 c5 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(,%rax,8\)
- 145: 83 80 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rax\)
- 14c: 83 80 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rax\)
- 153: 41 83 04 e8 33[ ]+addl[ ]+\$0x33,\(%r8,%rbp,8\)
- 158: 83 04 25 22 22 22 22 33 addl[ ]+\$0x33,0x22222222
- 160: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al
- 169: a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%eax
- 172: a2 11 22 33 44 55 66 77 88 mov[ ]+%al,0x8877665544332211
- 17b: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211
- 184: 48 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%rax
- 18e: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211
- 198: 48 99[ ]+cqto[ ]+
- 19a: 48 98[ ]+cltq[ ]+
- 19c: 48 63 c0[ ]+movslq %eax,%rax
- 19f: 48 0f bf c0[ ]+movswq %ax,%rax
- 1a3: 48 0f be c0[ ]+movsbq %al,%rax
+[ ]*[a-f0-9]+: 01 ca add %ecx,%edx
+[ ]*[a-f0-9]+: 44 01 ca add %r9d,%edx
+[ ]*[a-f0-9]+: 41 01 ca add %ecx,%r10d
+[ ]*[a-f0-9]+: 48 01 ca add %rcx,%rdx
+[ ]*[a-f0-9]+: 4d 01 ca add %r9,%r10
+[ ]*[a-f0-9]+: 41 01 c0 add %eax,%r8d
+[ ]*[a-f0-9]+: 66 41 01 c0 add %ax,%r8w
+[ ]*[a-f0-9]+: 49 01 c0 add %rax,%r8
+[ ]*[a-f0-9]+: 05 11 22 33 44 add \$0x44332211,%eax
+[ ]*[a-f0-9]+: 48 05 11 22 33 f4 add \$0xfffffffff4332211,%rax
+[ ]*[a-f0-9]+: 66 05 33 44 add \$0x4433,%ax
+[ ]*[a-f0-9]+: 48 05 11 22 33 44 add \$0x44332211,%rax
+[ ]*[a-f0-9]+: 00 ca add %cl,%dl
+[ ]*[a-f0-9]+: 00 f7 add %dh,%bh
+[ ]*[a-f0-9]+: 40 00 f7 add %sil,%dil
+[ ]*[a-f0-9]+: 41 00 f7 add %sil,%r15b
+[ ]*[a-f0-9]+: 44 00 f7 add %r14b,%dil
+[ ]*[a-f0-9]+: 45 00 f7 add %r14b,%r15b
+[ ]*[a-f0-9]+: 50 push %rax
+[ ]*[a-f0-9]+: 41 50 push %r8
+[ ]*[a-f0-9]+: 41 59 pop %r9
+[ ]*[a-f0-9]+: 04 11 add \$0x11,%al
+[ ]*[a-f0-9]+: 80 c4 11 add \$0x11,%ah
+[ ]*[a-f0-9]+: 40 80 c4 11 add \$0x11,%spl
+[ ]*[a-f0-9]+: 41 80 c0 11 add \$0x11,%r8b
+[ ]*[a-f0-9]+: 41 80 c4 11 add \$0x11,%r12b
+[ ]*[a-f0-9]+: 0f 20 c0 mov %cr0,%rax
+[ ]*[a-f0-9]+: 41 0f 20 c0 mov %cr0,%r8
+[ ]*[a-f0-9]+: 44 0f 20 c0 mov %cr8,%rax
+[ ]*[a-f0-9]+: 44 0f 22 c0 mov %rax,%cr8
+[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ ]*[a-f0-9]+: 66 f3 a5 rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ ]*[a-f0-9]+: b0 11 mov \$0x11,%al
+[ ]*[a-f0-9]+: b4 11 mov \$0x11,%ah
+[ ]*[a-f0-9]+: 40 b4 11 mov \$0x11,%spl
+[ ]*[a-f0-9]+: 41 b4 11 mov \$0x11,%r12b
+[ ]*[a-f0-9]+: b8 44 33 22 11 mov \$0x11223344,%eax
+[ ]*[a-f0-9]+: 41 b8 44 33 22 11 mov \$0x11223344,%r8d
+[ ]*[a-f0-9]+: 48 b8 88 77 66 55 44 33 22 11 mov \$0x1122334455667788,%rax
+[ ]*[a-f0-9]+: 49 b8 88 77 66 55 44 33 22 11 mov \$0x1122334455667788,%r8
+[ ]*[a-f0-9]+: 03 00 add \(%rax\),%eax
+[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
+[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
+[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
+[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
+[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
+[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
+[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
+[ ]*[a-f0-9]+: 03 04 80 add \(%rax,%rax,4\),%eax
+[ ]*[a-f0-9]+: 41 03 04 80 add \(%r8,%rax,4\),%eax
+[ ]*[a-f0-9]+: 45 03 04 80 add \(%r8,%rax,4\),%r8d
+[ ]*[a-f0-9]+: 43 03 04 80 add \(%r8,%r8,4\),%eax
+[ ]*[a-f0-9]+: 46 01 04 81 add %r8d,\(%rcx,%r8,4\)
+[ ]*[a-f0-9]+: 03 14 c0 add \(%rax,%rax,8\),%edx
+[ ]*[a-f0-9]+: 03 14 c8 add \(%rax,%rcx,8\),%edx
+[ ]*[a-f0-9]+: 03 14 d0 add \(%rax,%rdx,8\),%edx
+[ ]*[a-f0-9]+: 03 14 d8 add \(%rax,%rbx,8\),%edx
+[ ]*[a-f0-9]+: 03 10 add \(%rax\),%edx
+[ ]*[a-f0-9]+: 03 14 e8 add \(%rax,%rbp,8\),%edx
+[ ]*[a-f0-9]+: 03 14 f0 add \(%rax,%rsi,8\),%edx
+[ ]*[a-f0-9]+: 03 14 f8 add \(%rax,%rdi,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 c0 add \(%rax,%r8,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 c8 add \(%rax,%r9,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 d0 add \(%rax,%r10,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 d8 add \(%rax,%r11,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 e0 add \(%rax,%r12,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 e8 add \(%rax,%r13,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 f0 add \(%rax,%r14,8\),%edx
+[ ]*[a-f0-9]+: 42 03 14 f8 add \(%rax,%r15,8\),%edx
+[ ]*[a-f0-9]+: 83 c1 11 add \$0x11,%ecx
+[ ]*[a-f0-9]+: 83 00 11 addl \$0x11,\(%rax\)
+[ ]*[a-f0-9]+: 48 83 00 11 addq \$0x11,\(%rax\)
+[ ]*[a-f0-9]+: 41 83 00 11 addl \$0x11,\(%r8\)
+[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
+[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
+[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
+[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
+[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
+[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
+[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
+[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
+[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
+[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
+[ ]*[a-f0-9]+: 41 83 04 e8 33 addl \$0x33,\(%r8,%rbp,8\)
+[ ]*[a-f0-9]+: 83 04 25 22 22 22 22 33 addl \$0x33,0x22222222
+[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
+[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
+[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
+[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
+[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
+[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
+[ ]*[a-f0-9]+: 48 99 cqto
+[ ]*[a-f0-9]+: 48 98 cltq
+[ ]*[a-f0-9]+: 48 63 c0 movslq %eax,%rax
+[ ]*[a-f0-9]+: 48 0f bf c0 movswq %ax,%rax
+[ ]*[a-f0-9]+: 48 0f be c0 movsbq %al,%rax
0+1a7 <bar>:
- 1a7: b0 00[ ]+mov[ ]+\$0x0,%al
- 1a9: 66 b8 00 00[ ]+mov[ ]+\$0x0,%ax
- 1ad: b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
- 1b2: 48 c7 c0 00 00 00 00 mov[ ]+\$0x0,%rax
- 1b9: a1 00 00 00 00 00 00 00 00 mov[ ]+0x0,%eax
- 1c2: 8b 04 25 00 00 00 00 mov[ ]+0x0,%eax
- 1c9: 8b 80 00 00 00 00[ ]+mov[ ]+0x0\(%rax\),%eax
- 1cf: 8b 05 00 00 00 00[ ]+mov[ ]+0x0\(%rip\),%eax.*
- 1d5: b0 00[ ]+mov[ ]+\$0x0,%al
- 1d7: 66 b8 00 00[ ]+mov[ ]+\$0x0,%ax
- 1db: b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
- 1e0: 48 c7 c0 00 00 00 00 mov[ ]+\$0x0,%rax
- 1e7: a1 00 00 00 00 00 00 00 00 mov[ ]+0x0,%eax
- 1f0: 8b 04 25 00 00 00 00 mov[ ]+0x0,%eax
- 1f7: 8b 80 00 00 00 00[ ]+mov[ ]+0x0\(%rax\),%eax
- 1fd: 8b 05 00 00 00 00[ ]+mov[ ]+0x0\(%rip\),%eax.*
+[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
+[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
+[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
+[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
+[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 mov 0x0,%eax
+[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
+[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
+[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
+[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
+[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
+[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
+[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 mov 0x0,%eax
+[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
+[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
0+203 <foo>:
- 203: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al
- 20c: 66 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%ax
- 216: a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%eax
- 21f: 48 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%rax
- 229: a2 11 22 33 44 55 66 77 88 mov[ ]+%al,0x8877665544332211
- 232: 66 a3 11 22 33 44 55 66 77 88 mov[ ]+%ax,0x8877665544332211
- 23c: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211
- 245: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211
- 24f: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al
- 258: 66 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%ax
- 262: a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%eax
- 26b: 48 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%rax
- 275: a2 11 22 33 44 55 66 77 88 mov[ ]+%al,0x8877665544332211
- 27e: 66 a3 11 22 33 44 55 66 77 88 mov[ ]+%ax,0x8877665544332211
- 288: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211
- 291: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211
- 29b: 8a 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%al
- 2a2: 66 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%ax
- 2aa: 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%eax
- 2b1: 48 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%rax
- 2b9: 88 04 25 11 22 33 ff mov[ ]+%al,0xffffffffff332211
- 2c0: 66 89 04 25 11 22 33 ff mov[ ]+%ax,0xffffffffff332211
- 2c8: 89 04 25 11 22 33 ff mov[ ]+%eax,0xffffffffff332211
- 2cf: 48 89 04 25 11 22 33 ff mov[ ]+%rax,0xffffffffff332211
- 2d7: 8a 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%al
- 2de: 66 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%ax
- 2e6: 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%eax
- 2ed: 48 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%rax
- 2f5: 88 04 25 11 22 33 ff mov[ ]+%al,0xffffffffff332211
- 2fc: 66 89 04 25 11 22 33 ff mov[ ]+%ax,0xffffffffff332211
- 304: 89 04 25 11 22 33 ff mov[ ]+%eax,0xffffffffff332211
- 30b: 48 89 04 25 11 22 33 ff mov[ ]+%rax,0xffffffffff332211
- 313: 48 0f c7 08[ ]+cmpxchg16b \(%rax\)
- 317: 48 0f c7 08[ ]+cmpxchg16b \(%rax\)
+[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
+[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%ax
+[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
+[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
+[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
+[ ]*[a-f0-9]+: 66 a3 11 22 33 44 55 66 77 88 mov %ax,0x8877665544332211
+[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
+[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
+[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
+[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%ax
+[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
+[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
+[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
+[ ]*[a-f0-9]+: 66 a3 11 22 33 44 55 66 77 88 mov %ax,0x8877665544332211
+[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
+[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
+[ ]*[a-f0-9]+: 8a 04 25 11 22 33 ff mov 0xffffffffff332211,%al
+[ ]*[a-f0-9]+: 66 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%ax
+[ ]*[a-f0-9]+: 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%eax
+[ ]*[a-f0-9]+: 48 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%rax
+[ ]*[a-f0-9]+: 88 04 25 11 22 33 ff mov %al,0xffffffffff332211
+[ ]*[a-f0-9]+: 66 89 04 25 11 22 33 ff mov %ax,0xffffffffff332211
+[ ]*[a-f0-9]+: 89 04 25 11 22 33 ff mov %eax,0xffffffffff332211
+[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
+[ ]*[a-f0-9]+: 8a 04 25 11 22 33 ff mov 0xffffffffff332211,%al
+[ ]*[a-f0-9]+: 66 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%ax
+[ ]*[a-f0-9]+: 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%eax
+[ ]*[a-f0-9]+: 48 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%rax
+[ ]*[a-f0-9]+: 88 04 25 11 22 33 ff mov %al,0xffffffffff332211
+[ ]*[a-f0-9]+: 66 89 04 25 11 22 33 ff mov %ax,0xffffffffff332211
+[ ]*[a-f0-9]+: 89 04 25 11 22 33 ff mov %eax,0xffffffffff332211
+[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
+[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
+[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
+[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
+[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
+[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
+ ...
#pass
--- binutils/gas/testsuite/gas/i386/x86_64.s.suffix 2006-12-15 05:22:44.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86_64.s 2007-11-01 08:56:02.000000000 -0700
@@ -193,5 +193,40 @@ cmpxchg16b (%rax)
.intel_syntax noprefix
cmpxchg16b oword ptr [rax]
+.att_syntax
+ movsx (%rax), %edx
+ movsx (%rax), %rdx
+ movsx (%rax), %dx
+ movsbl (%rax), %edx
+ movsbq (%rax), %rdx
+ movsbw (%rax), %dx
+ movswl (%rax), %edx
+ movswq (%rax), %rdx
+
+ movzx (%rax), %edx
+ movzx (%rax), %rdx
+ movzx (%rax), %dx
+ movzb (%rax), %edx
+ movzb (%rax), %rdx
+ movzb (%rax), %dx
+ movzbl (%rax), %edx
+ movzbq (%rax), %rdx
+ movzbw (%rax), %dx
+ movzwl (%rax), %edx
+ movzwq (%rax), %rdx
+
+ .intel_syntax noprefix
+ movsx edx,BYTE PTR [rax]
+ movsx rdx,BYTE PTR [rax]
+ movsx dx,BYTE PTR [rax]
+ movsx edx,WORD PTR [rax]
+ movsx rdx,WORD PTR [rax]
+
+ movzx edx,BYTE PTR [rax]
+ movzx rdx,BYTE PTR [rax]
+ movzx dx,BYTE PTR [rax]
+ movzx edx,WORD PTR [rax]
+ movzx rdx,WORD PTR [rax]
+
# Get a good alignment.
.p2align 4,0
--- binutils/opcodes/i386-gen.c.suffix 2007-10-12 14:40:38.000000000 -0700
+++ binutils/opcodes/i386-gen.c 2007-11-01 08:56:02.000000000 -0700
@@ -277,6 +277,10 @@ static bitfield opcode_modifiers[] =
BITFIELD (IsString),
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
+ BITFIELD (ByteOkIntel),
+ BITFIELD (ToDword),
+ BITFIELD (ToQword),
+ BITFIELD (AddrPrefixOp0),
BITFIELD (IsPrefix),
BITFIELD (ImmExt),
BITFIELD (NoRex64),
--- binutils/opcodes/i386-opc.h.suffix 2007-10-12 14:40:38.000000000 -0700
+++ binutils/opcodes/i386-opc.h 2007-11-01 08:56:02.000000000 -0700
@@ -197,8 +197,16 @@ typedef union i386_cpu_flags
#define RegKludge (IsString + 1)
/* The first operand must be xmm0 */
#define FirstXmm0 (RegKludge + 1)
+/* BYTE is OK in Intel syntax. */
+#define ByteOkIntel (FirstXmm0 + 1)
+/* Convert to DWORD */
+#define ToDword (ByteOkIntel + 1)
+/* Convert to QWORD */
+#define ToQword (ToDword + 1)
+/* Address prefix changes operand 0 */
+#define AddrPrefixOp0 (ToQword + 1)
/* opcode is a prefix */
-#define IsPrefix (FirstXmm0 + 1)
+#define IsPrefix (AddrPrefixOp0 + 1)
/* instruction has extension in 8 bit imm */
#define ImmExt (IsPrefix + 1)
/* instruction don't need Rex64 prefix. */
@@ -243,6 +251,10 @@ typedef struct i386_opcode_modifier
unsigned int isstring:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
+ unsigned int byteokintel:1;
+ unsigned int todword:1;
+ unsigned int toqword:1;
+ unsigned int addrprefixop0:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;
--- binutils/opcodes/i386-opc.tbl.suffix 2007-10-12 14:40:38.000000000 -0700
+++ binutils/opcodes/i386-opc.tbl 2007-11-01 09:04:48.000000000 -0700
@@ -1103,9 +1103,9 @@ comiss, 2, 0xf2f, None, 2, CpuSSE, Modrm
cvtpi2ps, 2, 0xf2a, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM }
cvtps2pi, 2, 0xf2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX }
cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
+cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf|ToQword, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX }
-cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
+cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf|ToQword, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
divps, 2, 0xf5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
divss, 2, 0xf30f5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
ldmxcsr, 1, 0xfae, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
@@ -1250,11 +1250,11 @@ cvtpd2pi, 2, 0x660f2d, None, 2, CpuSSE2,
cvtpd2ps, 2, 0x660f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cvtps2pd, 2, 0xf5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cvtps2dq, 2, 0x660f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-cvtsd2si, 2, 0xf20f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
+cvtsd2si, 2, 0xf20f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf|ToDword, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
cvtsd2ss, 2, 0xf20f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cvtss2sd, 2, 0xf30f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cvttpd2pi, 2, 0x660f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX }
-cvttsd2si, 2, 0xf20f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
+cvttsd2si, 2, 0xf20f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf|ToDword, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 }
cvttpd2dq, 2, 0x660fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM }
@@ -1293,9 +1293,9 @@ monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_
// address size override prefix can be used to overrride the AX size in
// all modes.
// Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted.
-monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 }
+monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 }
// Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted.
-monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 }
+monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 }
movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
movshdup, 2, 0xf30f16, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
@@ -1380,11 +1380,11 @@ pblendvb, 3, 0x660f3810, None, 3, CpuSSE
pblendvb, 2, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ByteOkIntel, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
pextrd, 3, 0x660f3a16, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
+pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ByteOkIntel, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
pinsrd, 3, 0x660f3a22, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
pinsrq, 3, 0x660f3a22, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
pmaxsb, 2, 0x660f383c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
@@ -1469,21 +1469,21 @@ rdtscp, 0, 0xf01, 0xf9, 2, CpuSledgehamm
clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
invlpga, 0, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
// FIXME: Need to ensure only "invlpga %[re]ax,%ecx" is accepted.
-invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg32 }
+invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg32 }
skinit, 0, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
// FIXME: Need to ensure only "skinit %eax" is accepted.
skinit, 1, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32 }
stgi, 0, 0xf01, 0xdc, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
vmload, 0, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
// FIXME: Need to ensure only "vmload %[re]ax" is accepted.
-vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
+vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
vmmcall, 0, 0xf01, 0xd9, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
vmrun, 0, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
// FIXME: Need to ensure only "vmrun %[re]ax" is accepted.
-vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
+vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
vmsave, 0, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
// FIXME: Need to ensure only "vmsave %[re]ax" is accepted.
-vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
+vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
// SSE4a instructions