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Re: [PATCH] Add x86 SSE5 instructions to the GNU binary utilities
- From: "H.J. Lu" <hjl at lucon dot org>
- To: "rajagopal, dwarak" <dwarak dot rajagopal at amd dot com>
- Cc: binutils at sourceware dot org, "Meissner, Michael" <michael dot meissner at amd dot com>, "Harle, Christophe" <christophe dot harle at amd dot com>
- Date: Thu, 13 Sep 2007 13:42:45 -0700
- Subject: Re: [PATCH] Add x86 SSE5 instructions to the GNU binary utilities
- References: <20070831175452.GA17876@mmeissner-gold.amd.com> <9E1304B144EBEB4C97F4162BFAC478863D2AED@SAUSEXMB2.amd.com> <20070913203821.GA2831@lucon.org>
On Thu, Sep 13, 2007 at 01:38:21PM -0700, H.J. Lu wrote:
> On Thu, Sep 13, 2007 at 03:08:54PM -0500, rajagopal, dwarak wrote:
> > The enclosed patch adds support for the SSE5 instructions to the
> > assembler and disassembler.
> >
> > I have made changes to the original patch so that it uses bitfields (the
> > new infrastructure changes which H.J had checked in last week) for
> > cpu_flag, opcode_modifier and operand_types for the new instructions.
> >
>
> Did SSE5 reuse the same opcode for move test registers? If not,
> please don't remove OPC_EXT_45. You can use
>
> {
> /* OPC_EXT_45 */
> { THREE_BYTE_SSE5_0F7A }
> { "movL", { Td, Rd } },
> }
>
BTW, please put the patch inline and don't include the generated
files. It is easier to review.
Thanks.
H.J.