disassembly options

[Robin Getz <rgetz at blackfin dot uclinux dot org>]

Today in objdump, MIPS supports a -M reg-names=ARCH option, where the 
disassembler will print CPU-specific register names as appropriate for the 
selected CPU or architecture.

I was wondering if it made sense to extend this so it not only named core 
registers, but memory mapped registers as well...

For example, in Blackfin when we want to access a memory mapped register, we 
load the address into a pointer register, and do a read or write. Today the 
Disassembler puts out something like:

    20e4:       4a e1 c0 ff     P2.H = 0xffc0   /* 0xffc01f24 */;
    20e8:       0a e1 00 00     P2.L = 0x0      /* 0xffc00000 */;
    20ec:       10 95           R0 = W[P2] (Z);

Since we don't have 32-bit atomic loads, we need to load up each 16-bit half 
into a register, and then dereference it.

It would be nice to have something that automatically told me that the MMR at 
0xffc00000 == "PLL_CTL", (the name actually means something - and is 
referenced in the standard processor documentation), and get something that 
looks like:

    20e4:       4a e1 c0 ff     P2.H = 0xffc0   /* 0xffc01f24 */;
    20e8:       0a e1 00 00     P2.L = 0x0      /* 0xffc00000 */;
    20ec:       10 95           R0 = W[P2] (Z)  /* PLL_CTL */;

Thoughts? I thought if this was a nice thing for all SoC devices (ARM, MIPS, 
Blackfin, AVR32, FRV, SH, PPC, etc), I would try to do things in as generic 
way as possible. If everyone thinks this is stupid, then I will continue to 
look things up by hand...

-Robin