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Fix bitrot in the ARM VxWorks port

From: Richard Sandiford <richard at codesourcery dot com>
To: binutils at sourceware dot org
Date: Thu, 10 May 2007 18:01:24 +0100
Subject: Fix bitrot in the ARM VxWorks port
This patch fixes some bitrot in the arm-wrs-vxworks port.  There were
three problems:

  - When the PLT code was changed to differentiate between insns
    and data, the non-shared VxWorks "for (...)" loop wasn't updated.
    (The shared one was, and works fine.)

  - When support for MOVW and MOVT relocs were added, the needs_plt
    check was changed from an inclusive check to an exclusive check.
    R_ARM_ABS12 was missing from this exclusive check.

  - The testsuite was out of date.  Specifically:

    - It still used stmdb and ldmia instead of push and pop.

    - It still expected data to be disassembled as instructions
      rather than .words.  (The new output is _much_ nicer. ;))

    - Addresses in <...> related to in-text data were rendered
      differently.  The tests don't really care about the symbolic
      form of such addresses, so I've replaced them with "<.*>".

Tested on arm-wrs-vxworks, where we now get clean linker test results.
Committed as obvious.

Richard


bfd/
	* elf32-arm.c (elf32_arm_check_relocs): Don't create PLT entries
	for R_ARM_ABS12 relocs.
	(elf32_arm_finish_dynamic_symbol): Fix the loop that creates
	non-shared VxWorks PLT entries.

ld/testsuite/
	* ld-arm/vxworks1-lib.dd: Expect "push" instead of stmdb and
	"pop" instead of ldmia.  Don't require specific symbolic addresses
	for in-text addresses.  Expect data to be rendered as .words rather
	than disassembled.
	* ld-arm/vxworks1.dd: Likewise.

Index: bfd/elf32-arm.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-arm.c,v
retrieving revision 1.113
diff -u -p -r1.113 elf32-arm.c
--- bfd/elf32-arm.c	9 May 2007 13:02:10 -0000	1.113
+++ bfd/elf32-arm.c	10 May 2007 16:54:12 -0000
@@ -8062,7 +8062,8 @@ elf32_arm_check_relocs (bfd *abfd, struc
 		if (r_type != R_ARM_ABS32
                     && r_type != R_ARM_REL32
                     && r_type != R_ARM_ABS32_NOI
-                    && r_type != R_ARM_REL32_NOI)
+                    && r_type != R_ARM_REL32_NOI
+                    && r_type != R_ARM_ABS12)
 		  h->needs_plt = 1;
 
 		/* If we create a PLT entry, this relocation will reference
@@ -9248,7 +9249,7 @@ elf32_arm_finish_dynamic_symbol (bfd * o
 	      unsigned int i;
 	      bfd_vma val;
 
-	      for (i = 0; i != htab->plt_entry_size / 4; i++)
+	      for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
 		{
 		  val = elf32_arm_vxworks_exec_plt_entry[i];
 		  if (i == 2)
Index: ld/testsuite/ld-arm/vxworks1-lib.dd
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-arm/vxworks1-lib.dd,v
retrieving revision 1.1
diff -u -p -r1.1 vxworks1-lib.dd
--- ld/testsuite/ld-arm/vxworks1-lib.dd	7 Mar 2006 08:39:21 -0000	1.1
+++ ld/testsuite/ld-arm/vxworks1-lib.dd	10 May 2007 16:54:12 -0000
@@ -4,35 +4,35 @@
 Disassembly of section \.plt:
 
 00080800 <_PROCEDURE_LINKAGE_TABLE_>:
-   80800:	e59fc000 	ldr	ip, \[pc, #0\]	; 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>
+   80800:	e59fc000 	ldr	ip, \[pc, #0\]	; 80808 <.*>
    80804:	e79cf009 	ldr	pc, \[ip, r9\]
-   80808:	0000000c 	andeq	r0, r0, ip
-   8080c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>
+   80808:	0000000c 	.word	0x0000000c
+   8080c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80814 <.*>
    80810:	e599f008 	ldr	pc, \[r9, #8\]
-   80814:	00000000 	andeq	r0, r0, r0
-   80818:	e59fc000 	ldr	ip, \[pc, #0\]	; 80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
+   80814:	00000000 	.word	0x00000000
+   80818:	e59fc000 	ldr	ip, \[pc, #0\]	; 80820 <.*>
    8081c:	e79cf009 	ldr	pc, \[ip, r9\]
-   80820:	00000010 	andeq	r0, r0, r0, lsl r0
-   80824:	e59fc000 	ldr	ip, \[pc, #0\]	; 8082c <_PROCEDURE_LINKAGE_TABLE_\+0x2c>
+   80820:	00000010 	.word	0x00000010
+   80824:	e59fc000 	ldr	ip, \[pc, #0\]	; 8082c <.*>
    80828:	e599f008 	ldr	pc, \[r9, #8\]
-   8082c:	0000000c 	andeq	r0, r0, ip
+   8082c:	0000000c 	.word	0x0000000c
 Disassembly of section \.text:
 
 00080c00 <foo>:
-   80c00:	e92dc200 	stmdb	sp!, {r9, lr, pc}
-   80c04:	e59f9024 	ldr	r9, \[pc, #36\]	; 80c30 <\.text\+0x30>
+   80c00:	e92dc200 	push	{r9, lr, pc}
+   80c04:	e59f9024 	ldr	r9, \[pc, #36\]	; 80c30 <.*>
    80c08:	e5999000 	ldr	r9, \[r9\]
    80c0c:	e5999000 	ldr	r9, \[r9\]
-   80c10:	e59f001c 	ldr	r0, \[pc, #28\]	; 80c34 <\.text\+0x34>
+   80c10:	e59f001c 	ldr	r0, \[pc, #28\]	; 80c34 <.*>
    80c14:	e7991000 	ldr	r1, \[r9, r0\]
    80c18:	e2811001 	add	r1, r1, #1	; 0x1
    80c1c:	e7891000 	str	r1, \[r9, r0\]
    80c20:	eb000004 	bl	80c38 <slocal>
-   80c24:	ebfffefb 	bl	80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18>
-   80c28:	ebfffef4 	bl	80800 <_PROCEDURE_LINKAGE_TABLE_>
-   80c2c:	e8bd8200 	ldmia	sp!, {r9, pc}
-   80c30:	00000000 	andeq	r0, r0, r0
-   80c34:	00000014 	andeq	r0, r0, r4, lsl r0
+   80c24:	ebfffefb 	bl	80818 <.*>
+   80c28:	ebfffef4 	bl	80800 <.*>
+   80c2c:	e8bd8200 	pop	{r9, pc}
+   80c30:	00000000 	.word	0x00000000
+   80c34:	00000014 	.word	0x00000014
 
 00080c38 <slocal>:
    80c38:	e1a0f00e 	mov	pc, lr
Index: ld/testsuite/ld-arm/vxworks1.dd
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-arm/vxworks1.dd,v
retrieving revision 1.1
diff -u -p -r1.1 vxworks1.dd
--- ld/testsuite/ld-arm/vxworks1.dd	7 Mar 2006 08:39:21 -0000	1.1
+++ ld/testsuite/ld-arm/vxworks1.dd	10 May 2007 16:54:12 -0000
@@ -5,32 +5,32 @@ Disassembly of section \.plt:
 
 00080800 <_PROCEDURE_LINKAGE_TABLE_>:
    80800:	e52dc008 	str	ip, \[sp, #-8\]!
-   80804:	e59fc000 	ldr	ip, \[pc, #0\]	; 8080c <_PROCEDURE_LINKAGE_TABLE_\+0xc>
+   80804:	e59fc000 	ldr	ip, \[pc, #0\]	; 8080c <.*>
    80808:	e59cf008 	ldr	pc, \[ip, #8\]
-   8080c:	00081400 	andeq	r1, r8, r0, lsl #8
+   8080c:	00081400 	.word	0x00081400
 			8080c: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_
-   80810:	e59fc000 	ldr	ip, \[pc, #0\]	; 80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18>
+   80810:	e59fc000 	ldr	ip, \[pc, #0\]	; 80818 <.*>
    80814:	e59cf000 	ldr	pc, \[ip\]
-   80818:	0008140c 	andeq	r1, r8, ip, lsl #8
+   80818:	0008140c 	.word	0x0008140c
 			80818: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_\+0xc
-   8081c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80824 <_PROCEDURE_LINKAGE_TABLE_\+0x24>
-   80820:	eafffff6 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
-   80824:	00000000 	andeq	r0, r0, r0
-   80828:	e59fc000 	ldr	ip, \[pc, #0\]	; 80830 <_PROCEDURE_LINKAGE_TABLE_\+0x30>
+   8081c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80824 <.*>
+   80820:	eafffff6 	b	80800 <.*>
+   80824:	00000000 	.word	0x00000000
+   80828:	e59fc000 	ldr	ip, \[pc, #0\]	; 80830 <.*>
    8082c:	e59cf000 	ldr	pc, \[ip\]
-   80830:	00081410 	andeq	r1, r8, r0, lsl r4
+   80830:	00081410 	.word	0x00081410
 			80830: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_\+0x10
-   80834:	e59fc000 	ldr	ip, \[pc, #0\]	; 8083c <_PROCEDURE_LINKAGE_TABLE_\+0x3c>
-   80838:	eafffff0 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
-   8083c:	0000000c 	andeq	r0, r0, ip
+   80834:	e59fc000 	ldr	ip, \[pc, #0\]	; 8083c <.*>
+   80838:	eafffff0 	b	80800 <.*>
+   8083c:	0000000c 	.word	0x0000000c
 Disassembly of section \.text:
 
 00080c00 <_start>:
-   80c00:	ebffff08 	bl	80428 <_PROCEDURE_LINKAGE_TABLE_-0x3d8>
+   80c00:	ebffff08 	bl	80428 <.*>
 			80c00: R_ARM_PC24	\.plt\+0x20
    80c04:	eb000000 	bl	80c14 <sexternal\+0x8>
 			80c04: R_ARM_PC24	sexternal\+0xfffffff8
-   80c08:	eaffff00 	b	80408 <_PROCEDURE_LINKAGE_TABLE_-0x3f8>
+   80c08:	eaffff00 	b	80408 <.*>
 			80c08: R_ARM_PC24	\.plt\+0x8
 
 00080c0c <sexternal>:
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