diff -ruN --exclude '*#*' --exclude CVS gcc-3.3.3/gcc/config/mips/mips.c gcc-3.3.3_lexra/gcc/config/mips/mips.c --- gcc-3.3.3/gcc/config/mips/mips.c 2003-06-27 19:44:23.000000000 +0800 +++ gcc-3.3.3_lexra/gcc/config/mips/mips.c 2005-06-09 13:54:24.000000000 +0800 @@ -1819,6 +1819,7 @@ register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX; register int num_nops; +#ifdef NO_LEXRA if (type == DELAY_LOAD || type == DELAY_FCMP) num_nops = 1; @@ -1827,6 +1828,14 @@ else num_nops = 0; +#else /* NO_LEXRA */ + if (type == DELAY_FCMP) + num_nops = 1; + + else + num_nops = 0; +#endif /* NO_LEXRA */ + /* Make sure that we don't put nop's after labels. */ next_insn = NEXT_INSN (cur_insn); @@ -4056,11 +4065,14 @@ bytes -= 8; use_lwl_lwr = 1; } - else if (bytes >= 4 && align >= 4) { load_store[num].load = "lw\t%0,%1"; +#ifdef NO_LEXRA // (jackson) load_store[num].load_nop = "lw\t%0,%1%#"; +#else + load_store[num].load_nop = "lw\t%0,%1"; +#endif /* NO_LEXRA */ load_store[num].store = "sw\t%0,%1"; load_store[num].last_store = "sw\t%0,%1"; load_store[num].final = 0; @@ -4068,7 +4080,7 @@ offset += 4; bytes -= 4; } - +#if 0 // LEXRA else if (bytes >= 4 && ! TARGET_SR71K && ! TARGET_MIPS16) @@ -4095,11 +4107,15 @@ bytes -= 4; use_lwl_lwr = 1; } - +#endif // LEXRA else if (bytes >= 2 && align >= 2) { load_store[num].load = "lh\t%0,%1"; +#ifdef NO_LEXRA // (jackson) load_store[num].load_nop = "lh\t%0,%1%#"; +#else + load_store[num].load_nop = "lh\t%0,%1"; +#endif /* NO_LEXRA */ load_store[num].store = "sh\t%0,%1"; load_store[num].last_store = "sh\t%0,%1"; load_store[num].final = 0; @@ -4110,7 +4126,11 @@ else { load_store[num].load = "lb\t%0,%1"; +#ifdef NO_LEXRA // (jackson) load_store[num].load_nop = "lb\t%0,%1%#"; +#else + load_store[num].load_nop = "lb\t%0,%1"; +#endif /* NO_LEXRA */ load_store[num].store = "sb\t%0,%1"; load_store[num].last_store = "sb\t%0,%1"; load_store[num].final = 0; diff -ruN --exclude '*#*' --exclude CVS gcc-3.3.3/gcc/config/mips/mips.md gcc-3.3.3_lexra/gcc/config/mips/mips.md --- gcc-3.3.3/gcc/config/mips/mips.md 2003-06-27 19:44:22.000000000 +0800 +++ gcc-3.3.3_lexra/gcc/config/mips/mips.md 2005-06-09 10:34:45.000000000 +0800 @@ -131,14 +131,25 @@ ;; Does the instruction have a mandatory delay slot? ;; The 3900, is (mostly) mips1, but does not have a mandatory load delay ;; slot. +;;(define_attr "dslot" "no,yes" +;; (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") +;; (and (eq_attr "type" "load") +;; (and (eq (symbol_ref "mips_isa") (const_int 1)) +;; (and (eq (symbol_ref "mips16") (const_int 0)) +;; (eq_attr "cpu" "!r3900"))))) +;; (const_string "yes") +;; (const_string "no"))) + +;; LEXRA remove delay slot (jackson) (define_attr "dslot" "no,yes" (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") - (and (eq_attr "type" "load") - (and (eq (symbol_ref "mips_isa") (const_int 1)) - (and (eq (symbol_ref "mips16") (const_int 0)) - (eq_attr "cpu" "!r3900"))))) - (const_string "yes") - (const_string "no"))) + (and (eq_attr "type" "load") + (and (eq (symbol_ref "mips_isa") (const_int 1)) + (and (eq (symbol_ref "mips16") (const_int 0)) + (eq_attr "cpu" "!r3900,!r3000"))))) + (const_string "yes") + (const_string "no"))) + ;; Can the instruction be put into a delay slot? (define_attr "can_delay" "no,yes" @@ -4888,7 +4899,8 @@ if (operands[0] == NULL_RTX) FAIL; } - emit_insn (gen_movsi_ulw (operands[0], operands[1])); + /* emit_insn (gen_movsi_ulw (operands[0], operands[1])); */ /* LEXRA */ + FAIL; /* LEXRA */ } DONE; }") @@ -4937,7 +4949,8 @@ if (operands[0] == NULL_RTX) FAIL; } - emit_insn (gen_movsi_ulw (operands[0], operands[1])); + /* emit_insn (gen_movsi_ulw (operands[0], operands[1])); */ + FAIL; /* LEXRA */ } DONE; }") @@ -4986,69 +4999,70 @@ if (operands[3] == NULL_RTX) FAIL; } - emit_insn (gen_movsi_usw (operands[0], operands[3])); + /* emit_insn (gen_movsi_usw (operands[0], operands[3])); */ /* LEXRA */ + FAIL; /* LEXRA */ } DONE; }") ;; unaligned word moves generated by the bit field patterns -(define_insn "movsi_ulw" - [(set (match_operand:SI 0 "register_operand" "=&d,&d") - (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] - UNSPEC_ULW))] - "!TARGET_MIPS16" - "* -{ - rtx offset = const0_rtx; - rtx addr = XEXP (operands[1], 0); - rtx mem_addr = eliminate_constant_term (addr, &offset); - const char *ret; - - if (TARGET_STATS) - mips_count_memory_refs (operands[1], 2); - - /* The stack/frame pointers are always aligned, so we can convert - to the faster lw if we are referencing an aligned stack location. */ - - if ((INTVAL (offset) & 3) == 0 - && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) - ret = \"lw\\t%0,%1\"; - else - ret = \"ulw\\t%0,%1\"; - - return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn); -}" - [(set_attr "type" "load,load") - (set_attr "mode" "SI") - (set_attr "length" "8,16")]) - -(define_insn "movsi_usw" - [(set (match_operand:BLK 0 "memory_operand" "=R,o") - (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] - UNSPEC_USW))] - "!TARGET_MIPS16" - "* -{ - rtx offset = const0_rtx; - rtx addr = XEXP (operands[0], 0); - rtx mem_addr = eliminate_constant_term (addr, &offset); - - if (TARGET_STATS) - mips_count_memory_refs (operands[0], 2); - - /* The stack/frame pointers are always aligned, so we can convert - to the faster sw if we are referencing an aligned stack location. */ - - if ((INTVAL (offset) & 3) == 0 - && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) - return \"sw\\t%z1,%0\"; - - return \"usw\\t%z1,%0\"; -}" - [(set_attr "type" "store") - (set_attr "mode" "SI") - (set_attr "length" "8,16")]) +;;(define_insn "movsi_ulw" +;; [(set (match_operand:SI 0 "register_operand" "=&d,&d") +;; (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] +;; UNSPEC_ULW))] +;; "!TARGET_MIPS16" +;; "* +;;{ +;; rtx offset = const0_rtx; +;; rtx addr = XEXP (operands[1], 0); +;; rtx mem_addr = eliminate_constant_term (addr, &offset); +;; const char *ret; +;; +;; if (TARGET_STATS) +;; mips_count_memory_refs (operands[1], 2); +;; +;; /* The stack/frame pointers are always aligned, so we can convert +;; to the faster lw if we are referencing an aligned stack location. */ +;; +;; if ((INTVAL (offset) & 3) == 0 +;; && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) +;; ret = \"lw\\t%0,%1\"; +;; else +;; ret = \"ulw\\t%0,%1\"; +;; +;; return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn); +;;}" +;; [(set_attr "type" "load,load") +;; (set_attr "mode" "SI") +;; (set_attr "length" "8,16")]) + +;;(define_insn "movsi_usw" +;; [(set (match_operand:BLK 0 "memory_operand" "=R,o") +;; (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] +;; UNSPEC_USW))] +;; "!TARGET_MIPS16" +;; "* +;;{ +;; rtx offset = const0_rtx; +;; rtx addr = XEXP (operands[0], 0); +;; rtx mem_addr = eliminate_constant_term (addr, &offset); +;; +;; if (TARGET_STATS) +;; mips_count_memory_refs (operands[0], 2); +;; +;; /* The stack/frame pointers are always aligned, so we can convert +;; to the faster sw if we are referencing an aligned stack location. */ +;; +;; if ((INTVAL (offset) & 3) == 0 +;; && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) +;; return \"sw\\t%z1,%0\"; +;; +;; return \"usw\\t%z1,%0\"; +;;}" +;; [(set_attr "type" "store") +;; (set_attr "mode" "SI") +;; (set_attr "length" "8,16")]) ;; Bit field extract patterns which use ldl/ldr.