[PATCH, ARM] Add documentation for gas .dn/.qn directives

[Julian Brown <julian at codesourcery dot com>]

Hi,

This patch adds missing documentation for the ARM Neon .dn and .qn 
directives. These are similar to .req, but allow vector types to be 
specified.

OK?

Cheers,

Julian

ChangeLog

    gas/
    * doc/c-arm.texi: Add documentation for .dn/.qn directives.

Index: gas/doc/c-arm.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-arm.texi,v
retrieving revision 1.44
diff -c -p -r1.44 c-arm.texi
*** gas/doc/c-arm.texi	13 Dec 2006 16:06:39 -0000	1.44
--- gas/doc/c-arm.texi	2 Mar 2007 15:44:33 -0000
*************** example:
*** 391,397 ****
  @cindex @code{unreq} directive, ARM
  @item .unreq @var{alias-name}
  This undefines a register alias which was previously defined using the
! @code{req} directive.  For example:
  
  @smallexample
          foo .req r0
--- 391,397 ----
  @cindex @code{unreq} directive, ARM
  @item .unreq @var{alias-name}
  This undefines a register alias which was previously defined using the
! @code{req}, @code{dn} or @code{qn} directives.  For example:
  
  @smallexample
          foo .req r0
*************** An error occurs if the name is undefined
*** 402,407 ****
--- 402,437 ----
  be used to delete builtin in register name aliases (eg 'r0').  This
  should only be done if it is really necessary.
  
+ @cindex @code{dn} and @code{qn} directives, ARM
+ @item @var{name} .dn @var{register name} [@var{.type}] [@var{[index]}]
+ @item @var{name} .qn @var{register name} [@var{.type}] [@var{[index]}]
+ 
+ The @code{dn} and @code{qn} directives are used to create typed
+ and/or indexed register aliases for use in Advanced SIMD Extension
+ (Neon) instructions.  The former should be used to create aliases
+ of double-precision registers, and the latter to create aliases of
+ quad-precision registers.
+ 
+ If these directives are used to create typed aliases, those aliases can
+ be used in Neon instructions instead of writing types after the mnemonic
+ or after each operand.  For example:
+ 
+ @smallexample
+         x .dn d2.f32
+         y .dn d3.f32
+         z .dn d4.f32[1]
+         vmul x,y,z
+ @end smallexample
+ 
+ This is equivalent to writing the following:
+ 
+ @smallexample
+         vmul.f32 d2,d3,d4[1]
+ @end smallexample
+ 
+ Aliases created using @code{dn} or @code{qn} can be destroyed using
+ @code{unreq}.
+ 
  @cindex @code{code} directive, ARM
  @item .code @code{[16|32]}
  This directive selects the instruction set being generated. The value 16