This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[patch] Arm sub(3) disassemble
- From: Paul Brook <paul at codesourcery dot com>
- To: binutils at sources dot redhat dot com
- Date: Sun, 28 Aug 2005 00:48:35 +0100
- Subject: [patch] Arm sub(3) disassemble
The attached patch fixes an inconsistency in the arm disassembler. The
three-register 16-but thumb sub instruction sets the condition codes, but was
being disassembled as "sub". Patch changed this to "subs" and adjusts fixed
expected testcase output accordingly.
Tested with cross to arm-none-eabi.
Ok?
Paul
2005-08-28 Paul Brook <paul@codesourcery.com>
opcodes/
* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
gas/testsuite/
* gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
* gas/arm/thumb32.d: Ditto.
Index: gas/testsuite/gas/arm/thumb.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb.d,v
retrieving revision 1.6
diff -u -p -r1.6 thumb.d
--- gas/testsuite/gas/arm/thumb.d 4 Jul 2005 14:55:52 -0000 1.6
+++ gas/testsuite/gas/arm/thumb.d 27 Aug 2005 23:37:09 -0000
@@ -17,8 +17,8 @@ Disassembly of section \.text:
0+00e <[^>]+> 1008 asrs r0, r1, #32
0+010 <[^>]+> 18d1 adds r1, r2, r3
0+012 <[^>]+> 1ca2 adds r2, r4, #2
-0+014 <[^>]+> 1beb sub r3, r5, r7
-0+016 <[^>]+> 1fe2 sub r2, r4, #7
+0+014 <[^>]+> 1beb subs r3, r5, r7
+0+016 <[^>]+> 1fe2 subs r2, r4, #7
0+018 <[^>]+> 24ff movs r4, #255
0+01a <[^>]+> 2bfa cmp r3, #250
0+01c <[^>]+> 367b adds r6, #123
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.10
diff -u -p -r1.10 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d 5 Aug 2005 12:26:30 -0000 1.10
+++ gas/testsuite/gas/arm/thumb32.d 27 Aug 2005 23:37:46 -0000
@@ -95,10 +95,10 @@ Disassembly of section .text:
0+13e <[^>]+> f1b0 0005 subs\.w r0, r0, #5 ; 0x5
0+142 <[^>]+> f1b0 0081 subs\.w r0, r0, #129 ; 0x81
0+146 <[^>]+> f1b0 0508 subs\.w r5, r0, #8 ; 0x8
-0+14a <[^>]+> 1a00 sub r0, r0, r0
-0+14c <[^>]+> 1a05 sub r5, r0, r0
-0+14e <[^>]+> 1a28 sub r0, r5, r0
-0+150 <[^>]+> 1b40 sub r0, r0, r5
+0+14a <[^>]+> 1a00 subs r0, r0, r0
+0+14c <[^>]+> 1a05 subs r5, r0, r0
+0+14e <[^>]+> 1a28 subs r0, r5, r0
+0+150 <[^>]+> 1b40 subs r0, r0, r5
0+152 <[^>]+> f5a0 7d82 sub\.w sp, r0, #260 ; 0x104
0+156 <[^>]+> f5ad 7d82 sub\.w sp, sp, #260 ; 0x104
0+15a <[^>]+> ebb8 0800 subs\.w r8, r8, r0
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.52
diff -u -p -r1.52 arm-dis.c
--- opcodes/arm-dis.c 29 Jul 2005 17:39:39 -0000 1.52
+++ opcodes/arm-dis.c 27 Aug 2005 23:33:43 -0000
@@ -724,9 +724,9 @@ static const struct opcode16 thumb_opcod
{ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
/* format 2 */
{ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
- {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
+ {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
{ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
- {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
+ {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
/* format 8 */
{ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
{ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},