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Thumb32 assembler (52/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 02:59:37 -0700
- Subject: Thumb32 assembler (52/69)
Tidying. Mostly the result of running M-x tabify over the entire
file, but there's also one functional change: optional operand parse
codes are no longer pinned to start at 0x80. This makes the object
code for parse_operands significantly smaller (mainly because there's
no longer a huge gap in the middle of its case table).
zw
* config/tc-arm.c: Canonicalize whitespace throughout.
Remove unnecessary parentheses and/or left shifts by 0 throughout.
(enum vfp_dp_reg_pos, expression_or_fail): Delete.
(OP_I7b): Do not set a value.
(OP_FIRST_OPTIONAL): New constant.
(parse_operands): An operand code is optional if it is
greater than or equal to OP_FIRST_OPTIONAL.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 54)
+++ gas/config/tc-arm.c (revision 55)
@@ -17,7 +17,7 @@
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
@@ -26,7 +26,7 @@
02111-1307, USA. */
#include <string.h>
-#define NO_RELOC 0
+#define NO_RELOC 0
#include "as.h"
#include "safe-ctype.h"
@@ -56,31 +56,31 @@
static struct
{
- symbolS * proc_start;
- symbolS * table_entry;
- symbolS * personality_routine;
- int personality_index;
+ symbolS * proc_start;
+ symbolS * table_entry;
+ symbolS * personality_routine;
+ int personality_index;
/* The segment containing the function. */
- segT saved_seg;
- subsegT saved_subseg;
+ segT saved_seg;
+ subsegT saved_subseg;
/* Opcodes generated from this function. */
unsigned char * opcodes;
- int opcode_count;
- int opcode_alloc;
+ int opcode_count;
+ int opcode_alloc;
/* The number of bytes pushed to the stack. */
- offsetT frame_size;
+ offsetT frame_size;
/* We don't add stack adjustment opcodes immediately so that we can merge
multiple adjustments. We can also omit the final adjustment
when using a frame pointer. */
- offsetT pending_offset;
+ offsetT pending_offset;
/* These two fields are set by both unwind_movsp and unwind_setfp. They
- hold the reg+offset to use when restoring sp from a frame pointer. */
- offsetT fp_offset;
- int fp_reg;
+ hold the reg+offset to use when restoring sp from a frame pointer. */
+ offsetT fp_offset;
+ int fp_reg;
/* Nonzero if an unwind_setfp directive has been seen. */
- unsigned fp_used:1;
+ unsigned fp_used:1;
/* Nonzero if the last opcode restores sp from fp_reg. */
- unsigned sp_restored:1;
+ unsigned sp_restored:1;
} unwind;
#endif /* OBJ_ELF */
@@ -92,7 +92,7 @@
ARM_FLOAT_ABI_SOFT
};
-/* Types of processor to assemble for. */
+/* Types of processor to assemble for. */
#define ARM_1 ARM_ARCH_V1
#define ARM_2 ARM_ARCH_V2
#define ARM_3 ARM_ARCH_V2S
@@ -102,16 +102,16 @@
#define ARM_8 ARM_ARCH_V4
#define ARM_9 ARM_ARCH_V4T
#define ARM_STRONG ARM_ARCH_V4
-#define ARM_CPU_MASK 0x0000000f /* XXX? */
+#define ARM_CPU_MASK 0x0000000f /* XXX? */
#ifndef CPU_DEFAULT
#if defined __XSCALE__
#define CPU_DEFAULT (ARM_ARCH_XSCALE)
#else
#if defined __thumb__
-#define CPU_DEFAULT (ARM_ARCH_V5T)
+#define CPU_DEFAULT (ARM_ARCH_V5T)
#else
-#define CPU_DEFAULT ARM_ANY
+#define CPU_DEFAULT ARM_ANY
#endif
#endif
#endif
@@ -134,16 +134,16 @@
# endif
#endif /* ifndef FPU_DEFAULT */
-#define streq(a, b) (strcmp (a, b) == 0)
+#define streq(a, b) (strcmp (a, b) == 0)
static unsigned long cpu_variant;
/* Flags stored in private area of BFD structure. */
-static int uses_apcs_26 = FALSE;
-static int atpcs = FALSE;
+static int uses_apcs_26 = FALSE;
+static int atpcs = FALSE;
static int support_interwork = FALSE;
static int uses_apcs_float = FALSE;
-static int pic_code = FALSE;
+static int pic_code = FALSE;
/* Variables that we set while parsing command-line options. Once all
options have been read we re-process these values to set the real
@@ -166,7 +166,7 @@
#endif
#ifdef OBJ_ELF
-/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
symbolS * GOT_symbol;
#endif
@@ -181,29 +181,29 @@
struct arm_it
{
- const char * error;
+ const char * error;
unsigned long instruction;
- int size;
+ int size;
struct
{
bfd_reloc_code_real_type type;
- expressionS exp;
- int pc_rel;
+ expressionS exp;
+ int pc_rel;
} reloc;
struct
{
unsigned reg;
unsigned imm;
- unsigned present : 1; /* operand present */
+ unsigned present : 1; /* operand present */
unsigned isreg : 1; /* operand was a register */
- unsigned immisreg : 1; /* .imm field is a second register */
- unsigned hasreloc : 1; /* operand has relocation suffix */
- unsigned writeback : 1; /* operand has trailing ! */
- unsigned preind : 1; /* preindexed address */
- unsigned postind : 1; /* postindexed address */
- unsigned negative : 1; /* index register was negated */
- unsigned shifted : 1; /* shift applied to operation */
+ unsigned immisreg : 1; /* .imm field is a second register */
+ unsigned hasreloc : 1; /* operand has relocation suffix */
+ unsigned writeback : 1; /* operand has trailing ! */
+ unsigned preind : 1; /* preindexed address */
+ unsigned postind : 1; /* postindexed address */
+ unsigned negative : 1; /* index register was negated */
+ unsigned shifted : 1; /* shift applied to operation */
unsigned shift_kind : 3; /* shift operation (enum shift_kind) */
} operands[6];
};
@@ -217,7 +217,7 @@
"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
};
-/* Number of littlenums required to hold an extended precision number. */
+/* Number of littlenums required to hold an extended precision number. */
#define MAX_LITTLENUMS 6
LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
@@ -230,17 +230,17 @@
#define SUFF_E 3
#define SUFF_P 4
-#define CP_T_X 0x00008000
-#define CP_T_Y 0x00400000
+#define CP_T_X 0x00008000
+#define CP_T_Y 0x00400000
-#define CONDS_BIT 0x00100000
-#define LOAD_BIT 0x00100000
+#define CONDS_BIT 0x00100000
+#define LOAD_BIT 0x00100000
#define DOUBLE_LOAD_FLAG 0x00000001
struct asm_cond
{
- const char * template;
+ const char * template;
unsigned long value;
};
@@ -257,10 +257,10 @@
#define SPSR_BIT (1 << 22)
/* The individual PSR flag bits. */
-#define PSR_c (1 << 16)
-#define PSR_x (1 << 17)
-#define PSR_s (1 << 18)
-#define PSR_f (1 << 19)
+#define PSR_c (1 << 16)
+#define PSR_x (1 << 17)
+#define PSR_s (1 << 18)
+#define PSR_f (1 << 19)
struct reloc_entry
{
@@ -268,15 +268,6 @@
bfd_reloc_code_real_type reloc;
};
-/* These values are the bit offsets of the register fields, allowing these
- to be used directly in encoding operations. */
-enum vfp_dp_reg_pos
-{
- VFP_REG_Dd = 12,
- VFP_REG_Dn = 16,
- VFP_REG_Dm = 0
-};
-
enum vfp_sp_reg_pos
{
VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
@@ -288,7 +279,7 @@
};
/* ARM register categories. This includes coprocessor numbers and various
- architecture extensions' registers. */
+ architecture extensions' registers. */
enum arm_reg_type
{
REG_TYPE_RN,
@@ -319,7 +310,7 @@
unsigned char builtin;
};
-/* Diagnostics used when we don't get a register of the expected type. */
+/* Diagnostics used when we don't get a register of the expected type. */
const char *const reg_expected_msgs[] =
{
N_("ARM register expected"),
@@ -342,18 +333,18 @@
};
/* Some well known registers that we refer to directly elsewhere. */
-#define REG_SP 13
-#define REG_LR 14
+#define REG_SP 13
+#define REG_LR 14
#define REG_PC 15
/* ARM instructions take 4bytes in the object file, Thumb instructions
take 2: */
-#define INSN_SIZE 4
+#define INSN_SIZE 4
struct asm_opcode
{
/* Basic string to match. */
- const char * template;
+ const char *template;
/* Basic instruction code. */
unsigned long value;
@@ -361,7 +352,7 @@
/* Which architecture variant provides this instruction. */
unsigned long variant;
- /* Parameters to instruction. */
+ /* Parameters to instruction. */
unsigned char operands[8];
/* Function to call to encode instruction. */
@@ -371,7 +362,7 @@
/* Defines for various bits that we will want to toggle. */
#define INST_IMMEDIATE 0x02000000
#define OFFSET_REG 0x02000000
-#define HWOFFSET_IMM 0x00400000
+#define HWOFFSET_IMM 0x00400000
#define SHIFT_BY_REG 0x00000010
#define PRE_INDEX 0x01000000
#define INDEX_UP 0x00800000
@@ -422,7 +413,7 @@
#define T_OPCODE_ASR_R 0x4100
#define T_OPCODE_LSL_R 0x4080
-#define T_OPCODE_LSR_R 0x40c0
+#define T_OPCODE_LSR_R 0x40c0
#define T_OPCODE_ASR_I 0x1000
#define T_OPCODE_LSL_I 0x0000
#define T_OPCODE_LSR_I 0x0800
@@ -459,9 +450,9 @@
#define THUMB_PP_PC_LR 0x0100
#define THUMB_LOAD_BIT 0x0800
-#define BAD_ARGS _("bad arguments to instruction")
-#define BAD_PC _("r15 not allowed here")
-#define BAD_COND _("instruction is not conditional")
+#define BAD_ARGS _("bad arguments to instruction")
+#define BAD_PC _("r15 not allowed here")
+#define BAD_COND _("instruction is not conditional")
#define BAD_OVERLAP _("registers may not be the same")
#define BAD_HIREG _("lo register required")
@@ -480,7 +471,7 @@
may differ from:
...
label:
- <insn>
+ <insn>
*/
symbolS * last_label_seen;
@@ -492,12 +483,12 @@
#define MAX_LITERAL_POOL_SIZE 1024
typedef struct literal_pool
{
- expressionS literals [MAX_LITERAL_POOL_SIZE];
- unsigned int next_free_entry;
- unsigned int id;
- symbolS * symbol;
- segT section;
- subsegT sub_section;
+ expressionS literals [MAX_LITERAL_POOL_SIZE];
+ unsigned int next_free_entry;
+ unsigned int id;
+ symbolS * symbol;
+ segT section;
+ subsegT sub_section;
struct literal_pool * next;
} literal_pool;
@@ -505,15 +496,15 @@
literal_pool * list_of_pools = NULL;
-/* Pure syntax. */
+/* Pure syntax. */
/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful. */
+ pre-processor is disabled, these aren't very useful. */
const char comment_chars[] = "@";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
- .line and .file directives will appear in the pre-processed output. */
+ .line and .file directives will appear in the pre-processed output. */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
@@ -523,12 +514,12 @@
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant
- from exp in floating point numbers. */
+ from exp in floating point numbers. */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant. */
/* As in 0f12.456 */
-/* or 0d1.2345e12 */
+/* or 0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
@@ -553,7 +544,7 @@
}
#define skip_past_comma(str) skip_past_char (str, ',')
-/* Arithmetic expressions (possibly involving symbols). */
+/* Arithmetic expressions (possibly involving symbols). */
/* Return TRUE if anything in the expression is a bignum. */
@@ -575,7 +566,7 @@
static int in_my_get_expression = 0;
-/* Third argument to my_get_expression. */
+/* Third argument to my_get_expression. */
#define GE_NO_PREFIX 0
#define GE_IMM_PREFIX 1
#define GE_OPT_PREFIX 2
@@ -584,7 +575,7 @@
my_get_expression (expressionS * ep, char ** str, int prefix_mode)
{
char * save_in;
- segT seg;
+ segT seg;
switch (prefix_mode)
{
@@ -637,7 +628,7 @@
#endif
/* Get rid of any bignums now, so that we don't generate an error for which
- we can't establish a line number later on. Big numbers are never valid
+ we can't establish a line number later on. Big numbers are never valid
in instructions, which is where this routine is always called. */
if (ep->X_op == O_big
|| (ep->X_add_symbol
@@ -656,19 +647,13 @@
return 0;
}
-#define expression_or_fail(exp, str, pmode) \
-do { \
- if (my_get_expression (exp, str, pmode)) \
- return; \
- } while (0)
-
/* Turn a string in input_line_pointer into a floating point constant
of type TYPE, and store the appropriate bytes in *LITP. The number
of LITTLENUMS emitted is stored in *SIZEP. An error message is
returned, or NULL on OK.
Note that fp constants aren't represent in the normal way on the ARM.
- In big endian mode, things are as expected. However, in little endian
+ In big endian mode, things are as expected. However, in little endian
mode fp constants are big-endian word-wise, and little-endian byte-wise
within the words. For example, (double) 1.1 in big endian mode is
the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
@@ -757,10 +742,10 @@
fpa_immediate (char ** str)
{
LITTLENUM_TYPE words[MAX_LITTLENUMS];
- char * save_in;
- expressionS exp;
- int i;
- int j;
+ char * save_in;
+ expressionS exp;
+ int i;
+ int j;
/* First try and match exact strings, this is to guarantee
that some formats will work even for cross assembly. */
@@ -770,7 +755,7 @@
if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
{
char *start = *str;
-
+
*str += strlen (fp_const[i]);
if (is_end_of_line[(unsigned char) **str])
return i + 8;
@@ -814,7 +799,7 @@
&& exp.X_add_number < 0)
{
/* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
- Ditto for 15. */
+ Ditto for 15. */
if (gen_to_words (words, 5, (long) 15) == 0)
{
for (i = 0; i < NUM_FLOAT_VALS; i++)
@@ -928,7 +913,7 @@
/* Generic register parser. CCP points to what should be the
beginning of a register name. If it is indeed a valid register
name, advance CCP over it and return the reg_entry structure;
- otherwise return NULL. Does not issue diagnostics. */
+ otherwise return NULL. Does not issue diagnostics. */
static struct reg_entry *
arm_reg_parse_multi (char **ccp)
@@ -1035,8 +1020,8 @@
reg_list (char ** strp)
{
char * str = * strp;
- long range = 0;
- int another_range;
+ long range = 0;
+ int another_range;
/* We come back here if we get ranges concatenated by '+' or '|'. */
do
@@ -1157,7 +1142,7 @@
/* Parse a VFP register list. If the string is invalid return FAIL.
Otherwise return the number of registers, and set PBASE to the first
- register. Double precision registers are matched if DP is nonzero. */
+ register. Double precision registers are matched if DP is nonzero. */
static int
vfp_parse_reg_list (char **str, int *pbase, int dp)
@@ -1279,7 +1264,7 @@
struct asm_shift_name
{
- const char *name;
+ const char *name;
enum shift_kind kind;
};
@@ -1287,10 +1272,10 @@
enum parse_shift_mode
{
NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
- SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
- SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
- SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
- SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
+ SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
+ SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
+ SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
+ SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
};
/* Parse a <shift> specifier on an ARM data processing instruction.
@@ -1362,10 +1347,10 @@
default: abort ();
}
-
+
if (shift != SHIFT_RRX)
{
- /* Whitespace can appear here if the next thing is a bare digit. */
+ /* Whitespace can appear here if the next thing is a bare digit. */
skip_whitespace (p);
if (mode == NO_SHIFT_RESTRICT
@@ -1384,7 +1369,7 @@
}
/* Encode a <shift> in an ARM-format instruction. The immediate,
- if any, is handled by md_apply_fix3. */
+ if any, is handled by md_apply_fix3. */
static void
encode_shift_arm (int i)
{
@@ -1475,7 +1460,7 @@
{
if (inst.operands[i].isreg)
{
- inst.instruction |= inst.operands[i].reg << 0;
+ inst.instruction |= inst.operands[i].reg;
encode_shift_arm (i);
}
else
@@ -1486,7 +1471,7 @@
either nothing, or a word in parentheses. Note that if !OBJ_ELF,
arm_reloc_hsh contains no entries, so this function can only
succeed if there is no () after the word. Returns -1 on error,
- BFD_RELOC_UNUSED if there wasn't any suffix. */
+ BFD_RELOC_UNUSED if there wasn't any suffix. */
static int
parse_reloc (char **str)
{
@@ -1517,9 +1502,9 @@
Preindexed addressing (.preind=1):
[Rn, #offset] .reg=Rn .reloc.exp=offset
- [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
+ [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
[Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
- .shift_kind=shift .reloc.exp=shift_imm
+ .shift_kind=shift .reloc.exp=shift_imm
These three may have a trailing ! which causes .writeback to be set also.
@@ -1528,7 +1513,7 @@
[Rn], #offset .reg=Rn .reloc.exp=offset
[Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
[Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
- .shift_kind=shift .reloc.exp=shift_imm
+ .shift_kind=shift .reloc.exp=shift_imm
Unindexed addressing (.preind=0, .postind=0):
@@ -1749,7 +1734,7 @@
{
assert (inst.operands[i].isreg);
inst.instruction |= inst.operands[i].reg << 16;
-
+
if (inst.operands[i].preind)
{
if (is_t)
@@ -1760,7 +1745,7 @@
inst.instruction |= PRE_INDEX;
if (inst.operands[i].writeback)
inst.instruction |= WRITE_BACK;
-
+
}
else if (inst.operands[i].postind)
{
@@ -1773,7 +1758,7 @@
inst.error = _("instruction does not accept unindexed addressing");
return;
}
-
+
if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
&& (((inst.instruction & 0x000f0000) >> 16)
== ((inst.instruction & 0x0000f000) >> 12)))
@@ -1783,7 +1768,7 @@
}
/* inst.operands[i] was set up by parse_address. Encode it into an
- ARM-format mode 2 load or store instruction. If is_t is true,
+ ARM-format mode 2 load or store instruction. If is_t is true,
reject forms that cannot be used with a T instruction (i.e. not
post-indexed). */
static void
@@ -1794,7 +1779,7 @@
if (inst.operands[i].immisreg)
{
inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
- inst.instruction |= inst.operands[i].imm << 0;
+ inst.instruction |= inst.operands[i].imm;
if (!inst.operands[i].negative)
inst.instruction |= INDEX_UP;
if (inst.operands[i].shifted)
@@ -1818,7 +1803,7 @@
}
/* inst.operands[i] was set up by parse_address. Encode it into an
- ARM-format mode 3 load or store instruction. Reject forms that
+ ARM-format mode 3 load or store instruction. Reject forms that
cannot be used with such instructions. If is_t is true, reject
forms that cannot be used with a T instruction (i.e. not
post-indexed). */
@@ -1830,12 +1815,12 @@
inst.error = _("instruction does not accept scaled register index");
return;
}
-
+
encode_addr_mode_common_arm (i, is_t);
if (inst.operands[i].immisreg)
{
- inst.instruction |= inst.operands[i].imm << 0;
+ inst.instruction |= inst.operands[i].imm;
if (!inst.operands[i].negative)
inst.instruction |= INDEX_UP;
}
@@ -1864,7 +1849,7 @@
assert (!(inst.operands[i].preind && inst.operands[i].postind));
if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
- {
+ {
assert (!inst.operands[i].writeback);
if (!unind_ok)
{
@@ -1904,7 +1889,7 @@
}
/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
- value suitable for splatting into the AIF field of the instruction. */
+ value suitable for splatting into the AIF field of the instruction. */
static int
parse_cps_flags (char **str)
@@ -2016,7 +2001,7 @@
as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
/* Only warn about a redefinition if it's not defined as the
- same register. */
+ same register. */
else if (new->number != number || new->type != type)
as_warn (_("ignoring redefinition of register alias '%s'"), str);
@@ -2035,9 +2020,9 @@
abort ();
}
-/* Look for the .req directive. This is of the form:
+/* Look for the .req directive. This is of the form:
- new_register_name .req existing_register_name
+ new_register_name .req existing_register_name
If we find one, or if it looks sufficiently like one that we want to
handle any error here, return non-zero. Otherwise return zero. */
@@ -2112,7 +2097,7 @@
by .req. For example:
my_alias .req r11
- .unreq my_alias */
+ .unreq my_alias */
static void
s_unreq (int a ATTRIBUTE_UNUSED)
@@ -2137,7 +2122,7 @@
struct reg_entry *reg = hash_find (arm_reg_hsh, name);
if (!reg)
- as_bad (_("unknown register alias '%s'"), name);
+ as_bad (_("unknown register alias '%s'"), name);
else if (reg->builtin)
as_warn (_("ignoring attempt to undefine built-in register '%s'"),
name);
@@ -2165,7 +2150,7 @@
Thumb code, and data. There are inline transitions between code
and data at literal pool boundaries. There can also be inline
transitions between ARM code and Thumb code, for example in
- ARM-Thumb inter-working veneers. Linkers, machine-level
+ ARM-Thumb inter-working veneers. Linkers, machine-level
debuggers, profiling tools, and disassembly tools need to map
images accurately. For example, setting an ARM breakpoint on a
Thumb location, or in a literal pool, can crash the program
@@ -2186,13 +2171,13 @@
4.4.7.1 Mapping symbols
$a Labels the first byte of a sequence of ARM instructions.
- Its type is STT_FUNC.
+ Its type is STT_FUNC.
$d Labels the first byte of a sequence of data items.
- Its type is STT_OBJECT.
+ Its type is STT_OBJECT.
$t Labels the first byte of a sequence of Thumb instructions.
- Its type is STT_FUNC.
+ Its type is STT_FUNC.
This list of mapping symbols may be extended in the future.
@@ -2304,7 +2289,7 @@
const char * name = S_GET_NAME (symbolP);
symbolS * new_target;
- /* This definition must agree with the one in gcc/config/arm/thumb.c. */
+ /* This definition must agree with the one in gcc/config/arm/thumb.c. */
#define STUB_NAME ".real_start_of"
if (name == NULL)
@@ -2312,7 +2297,7 @@
/* Names that start with '.' are local labels, not function entry points.
The compiler may generate BL instructions to these labels because it
- needs to perform a branch to a far away location. */
+ needs to perform a branch to a far away location. */
if (name[0] == '.')
return symbolP;
@@ -2345,7 +2330,7 @@
thumb_mode = 1;
/* No need to force the alignment, since we will have been
- coming from ARM mode, which is word-aligned. */
+ coming from ARM mode, which is word-aligned. */
record_alignment (now_seg, 1);
}
mapping_state (MAP_THUMB);
@@ -2411,7 +2396,7 @@
the target processor does not support thumb instructions.
This is used by gcc/config/arm/lib1funcs.asm for example
to compile interworking support functions even if the
- target processor should not support interworking. */
+ target processor should not support interworking. */
if (! thumb_mode)
{
thumb_mode = 2;
@@ -2429,7 +2414,7 @@
opcode_select (16);
/* The following label is the name/address of the start of a Thumb function.
- We need to know this for the interworking support. */
+ We need to know this for the interworking support. */
label_is_thumb_function_name = TRUE;
demand_empty_rest_of_line ();
@@ -2445,15 +2430,15 @@
We cannot just call that code as we need to get at the symbol that
is created. */
char * name;
- char delim;
+ char delim;
char * end_name;
symbolS * symbolP;
/* Especial apologies for the random logic:
This just grew, and could be parsed much more simply!
Dean - in haste. */
- name = input_line_pointer;
- delim = get_symbol_end ();
+ name = input_line_pointer;
+ delim = get_symbol_end ();
end_name = input_line_pointer;
*end_name = delim;
@@ -2481,7 +2466,7 @@
#ifndef NO_LISTING
/* When doing symbol listings, play games with dummy fragments living
outside the normal fragment chain to record the file and line info
- for this symbol. */
+ for this symbol. */
if (listing & LISTING_SYMBOLS)
{
extern struct list_info_struct * listing_tail;
@@ -2516,7 +2501,7 @@
demand_empty_rest_of_line ();
- /* XXX Now we come to the Thumb specific bit of code. */
+ /* XXX Now we come to the Thumb specific bit of code. */
THUMB_SET_FUNC (symbolP, 1);
ARM_SET_THUMB (symbolP, 1);
@@ -2527,7 +2512,7 @@
/* Directives: sectioning and alignment. */
-/* Same as s_align_ptwo but align 0 => align 2. */
+/* Same as s_align_ptwo but align 0 => align 2. */
static void
s_align (int unused ATTRIBUTE_UNUSED)
@@ -2568,7 +2553,7 @@
s_bss (int ignore ATTRIBUTE_UNUSED)
{
/* We don't support putting frags in the BSS segment, we fake it by
- marking in_bss, then looking at s_skip for clues. */
+ marking in_bss, then looking at s_skip for clues. */
subseg_set (bss_section, 0);
demand_empty_rest_of_line ();
mapping_state (MAP_DATA);
@@ -2620,10 +2605,10 @@
return NULL;
pool->next_free_entry = 0;
- pool->section = now_seg;
- pool->sub_section = now_subseg;
- pool->next = list_of_pools;
- pool->symbol = NULL;
+ pool->section = now_seg;
+ pool->sub_section = now_subseg;
+ pool->next = list_of_pools;
+ pool->symbol = NULL;
/* Add it to the list. */
list_of_pools = pool;
@@ -2664,17 +2649,17 @@
break;
if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
- && (inst.reloc.exp.X_op == O_symbol)
- && (pool->literals[entry].X_add_number
+ && (inst.reloc.exp.X_op == O_symbol)
+ && (pool->literals[entry].X_add_number
== inst.reloc.exp.X_add_number)
- && (pool->literals[entry].X_add_symbol
+ && (pool->literals[entry].X_add_symbol
== inst.reloc.exp.X_add_symbol)
- && (pool->literals[entry].X_op_symbol
+ && (pool->literals[entry].X_op_symbol
== inst.reloc.exp.X_op_symbol))
- break;
+ break;
}
- /* Do we need to create a new entry? */
+ /* Do we need to create a new entry? */
if (entry == pool->next_free_entry)
{
if (entry >= MAX_LITERAL_POOL_SIZE)
@@ -2687,7 +2672,7 @@
pool->next_free_entry += 1;
}
- inst.reloc.exp.X_op = O_symbol;
+ inst.reloc.exp.X_op = O_symbol;
inst.reloc.exp.X_add_number = ((int) entry) * 4;
inst.reloc.exp.X_add_symbol = pool->symbol;
@@ -2701,7 +2686,7 @@
load and return 0. If this is not a valid thing to do in the
current context, set inst.error and return 1.
- inst.operands[i] describes the destination register. */
+ inst.operands[i] describes the destination register. */
static int
move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
@@ -2723,7 +2708,7 @@
if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
{
/* This can be done with a mov instruction. */
- inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
+ inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
inst.instruction |= inst.reloc.exp.X_add_number;
return 1;
}
@@ -2774,10 +2759,10 @@
static void
symbol_locate (symbolS * symbolP,
- const char * name, /* It is copied, the caller can modify. */
- segT segment, /* Segment identifier (SEG_<something>). */
- valueT valu, /* Symbol value. */
- fragS * frag) /* Associated fragment. */
+ const char * name, /* It is copied, the caller can modify. */
+ segT segment, /* Segment identifier (SEG_<something>). */
+ valueT valu, /* Symbol value. */
+ fragS * frag) /* Associated fragment. */
{
unsigned int name_length;
char * preserved_copy_of_name;
@@ -2996,7 +2981,7 @@
/* Mark the start of the function. */
unwind.proc_start = expr_build_dot ();
- /* Reset the rest of the unwind info. */
+ /* Reset the rest of the unwind info. */
unwind.opcode_count = 0;
unwind.table_entry = NULL;
unwind.personality_routine = NULL;
@@ -3039,7 +3024,7 @@
else
val = 0;
- /* Add index table entry. This is two words. */
+ /* Add index table entry. This is two words. */
start_unwind_section (unwind.saved_seg, 1);
frag_align (2, 0, 0);
record_alignment (now_seg, 2);
@@ -3055,7 +3040,7 @@
/* Inline exception table entry. */
md_number_to_chars (ptr + 4, val, 4);
else
- /* Self relative offset of the table entry. */
+ /* Self relative offset of the table entry. */
fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
BFD_RELOC_ARM_PREL31);
@@ -3077,7 +3062,7 @@
}
-/* Parse a personalityindex directive. */
+/* Parse a personalityindex directive. */
static void
s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
@@ -3157,7 +3142,7 @@
registers starting with r4, plus maybe r14. */
for (n = 0; n < 8; n++)
{
- /* Break at the first non-saved register. */
+ /* Break at the first non-saved register. */
if ((range & (1 << (n + 4))) == 0)
break;
}
@@ -3172,21 +3157,21 @@
{
/* Use the short form. */
if (range & 0x4000)
- op = 0xa8; /* Pop r14. */
+ op = 0xa8; /* Pop r14. */
else
op = 0xa0; /* Do not pop r14. */
op |= (n - 1);
add_unwind_opcode (op, 1);
}
- /* Pop r0-r3. */
+ /* Pop r0-r3. */
if (range & 0xf)
{
op = 0xb100 | (range & 0xf);
add_unwind_opcode (op, 2);
}
- /* Record the number of bytes pushed. */
+ /* Record the number of bytes pushed. */
for (n = 0; n < 16; n++)
{
if (range & (1 << n))
@@ -3333,7 +3318,7 @@
demand_empty_rest_of_line ();
/* Generate any deferred opcodes becuuse we're going to be looking at
- the list. */
+ the list. */
flush_pending_unwind ();
for (i = 0; i < 16; i++)
@@ -3342,9 +3327,9 @@
unwind.frame_size += 8;
}
- /* Attempt to combine with a previous opcode. We do this because gcc
+ /* Attempt to combine with a previous opcode. We do this because gcc
likes to output separate unwind directives for a single block of
- registers. */
+ registers. */
if (unwind.opcode_count > 0)
{
i = unwind.opcodes[unwind.opcode_count - 1];
@@ -3389,7 +3374,7 @@
|| !(mask & (1 << reg)))
{
/* We found an unsaved reg. Generate opcodes to save the
- preceeding block. */
+ preceeding block. */
if (reg != hi_reg)
{
if (reg == 9)
@@ -3400,7 +3385,7 @@
}
else
{
- /* Long form. */
+ /* Long form. */
op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
add_unwind_opcode (op, 2);
}
@@ -3466,7 +3451,7 @@
demand_empty_rest_of_line ();
/* Generate any deferred opcodes becuuse we're going to be looking at
- the list. */
+ the list. */
flush_pending_unwind ();
for (reg = 0; reg < 16; reg++)
@@ -3521,8 +3506,8 @@
s_arm_unwind_save_fpa (reg->number);
return;
- case REG_TYPE_RN: s_arm_unwind_save_core (); return;
- case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
+ case REG_TYPE_RN: s_arm_unwind_save_core (); return;
+ case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
@@ -3563,7 +3548,7 @@
op = 0x90 | reg;
add_unwind_opcode (op, 1);
- /* Record the information for later. */
+ /* Record the information for later. */
unwind.fp_reg = reg;
unwind.fp_offset = unwind.frame_size;
unwind.sp_restored = 1;
@@ -3615,7 +3600,7 @@
return;
}
- /* Optional constant. */
+ /* Optional constant. */
if (skip_past_comma (&input_line_pointer) != FAIL)
{
if (immediate_for_directive (&offset) == FAIL)
@@ -3633,7 +3618,7 @@
return;
}
- /* Don't generate any opcodes, just record the information for later. */
+ /* Don't generate any opcodes, just record the information for later. */
unwind.fp_reg = fp_reg;
unwind.fp_used = 1;
if (sp_reg == 13)
@@ -3648,7 +3633,7 @@
s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
{
expressionS exp;
- /* This is an arbitary limit. */
+ /* This is an arbitary limit. */
unsigned char op[16];
int count;
@@ -3671,7 +3656,7 @@
count = 0;
- /* Parse the opcode. */
+ /* Parse the opcode. */
for (;;)
{
if (count >= 16)
@@ -3710,24 +3695,24 @@
const pseudo_typeS md_pseudo_table[] =
{
- /* Never called because '.req' does not start a line. */
- { "req", s_req, 0 },
- { "unreq", s_unreq, 0 },
- { "bss", s_bss, 0 },
- { "align", s_align, 0 },
- { "arm", s_arm, 0 },
- { "thumb", s_thumb, 0 },
- { "code", s_code, 0 },
+ /* Never called because '.req' does not start a line. */
+ { "req", s_req, 0 },
+ { "unreq", s_unreq, 0 },
+ { "bss", s_bss, 0 },
+ { "align", s_align, 0 },
+ { "arm", s_arm, 0 },
+ { "thumb", s_thumb, 0 },
+ { "code", s_code, 0 },
{ "force_thumb", s_force_thumb, 0 },
{ "thumb_func", s_thumb_func, 0 },
- { "thumb_set", s_thumb_set, 0 },
- { "even", s_even, 0 },
- { "ltorg", s_ltorg, 0 },
- { "pool", s_ltorg, 0 },
+ { "thumb_set", s_thumb_set, 0 },
+ { "even", s_even, 0 },
+ { "ltorg", s_ltorg, 0 },
+ { "pool", s_ltorg, 0 },
#ifdef OBJ_ELF
- { "word", s_arm_elf_cons, 4 },
- { "long", s_arm_elf_cons, 4 },
- { "rel31", s_arm_rel31, 0 },
+ { "word", s_arm_elf_cons, 4 },
+ { "long", s_arm_elf_cons, 4 },
+ { "rel31", s_arm_rel31, 0 },
{ "fnstart", s_arm_unwind_fnstart, 0 },
{ "fnend", s_arm_unwind_fnend, 0 },
{ "cantunwind", s_arm_unwind_cantunwind, 0 },
@@ -3740,97 +3725,99 @@
{ "setfp", s_arm_unwind_setfp, 0 },
{ "unwind_raw", s_arm_unwind_raw, 0 },
#else
- { "word", cons, 4},
+ { "word", cons, 4},
#endif
- { "extend", float_cons, 'x' },
- { "ldouble", float_cons, 'x' },
- { "packed", float_cons, 'p' },
+ { "extend", float_cons, 'x' },
+ { "ldouble", float_cons, 'x' },
+ { "packed", float_cons, 'p' },
{ 0, 0, 0 }
};
/* Matcher codes for operand_parse. */
enum operand_parse_code
{
- OP_stop, /* end of line */
+ OP_stop, /* end of line */
- OP_RR, /* ARM register */
- OP_RRnpc, /* ARM register, not r15 */
- OP_RRnpcb, /* ARM register, not r15, in square brackets */
- OP_RRw, /* ARM register, not r15, optional trailing ! */
- OP_RL, /* Thumb low register */
- OP_RLw, /* Thumb low register, optional trailing ! */
- OP_RCP, /* Coprocessor number */
- OP_RCN, /* Coprocessor register */
- OP_RF, /* FPA register */
- OP_RVS, /* VFP single precision register */
- OP_RVD, /* VFP double precision register */
- OP_RVC, /* VFP control register */
- OP_RMF, /* Maverick F register */
- OP_RMD, /* Maverick D register */
- OP_RMFX, /* Maverick FX register */
- OP_RMDX, /* Maverick DX register */
- OP_RMAX, /* Maverick AX register */
- OP_RMDS, /* Maverick DSPSC register */
- OP_RIWR, /* iWMMXt wR register */
- OP_RIWC, /* iWMMXt wC register */
- OP_RIWG, /* iWMMXt wCG register */
- OP_RXA, /* XScale accumulator register */
+ OP_RR, /* ARM register */
+ OP_RRnpc, /* ARM register, not r15 */
+ OP_RRnpcb, /* ARM register, not r15, in square brackets */
+ OP_RRw, /* ARM register, not r15, optional trailing ! */
+ OP_RL, /* Thumb low register */
+ OP_RLw, /* Thumb low register, optional trailing ! */
+ OP_RCP, /* Coprocessor number */
+ OP_RCN, /* Coprocessor register */
+ OP_RF, /* FPA register */
+ OP_RVS, /* VFP single precision register */
+ OP_RVD, /* VFP double precision register */
+ OP_RVC, /* VFP control register */
+ OP_RMF, /* Maverick F register */
+ OP_RMD, /* Maverick D register */
+ OP_RMFX, /* Maverick FX register */
+ OP_RMDX, /* Maverick DX register */
+ OP_RMAX, /* Maverick AX register */
+ OP_RMDS, /* Maverick DSPSC register */
+ OP_RIWR, /* iWMMXt wR register */
+ OP_RIWC, /* iWMMXt wC register */
+ OP_RIWG, /* iWMMXt wCG register */
+ OP_RXA, /* XScale accumulator register */
- OP_REGLST, /* ARM register list */
- OP_VRSLST, /* VFP single-precision register list */
- OP_VRDLST, /* VFP double-precision register list */
+ OP_REGLST, /* ARM register list */
+ OP_VRSLST, /* VFP single-precision register list */
+ OP_VRDLST, /* VFP double-precision register list */
- OP_I7, /* immediate value 0 .. 7 */
- OP_I15, /* 0 .. 15 */
- OP_I16, /* 1 .. 16 */
- OP_I31, /* 0 .. 31 */
- OP_I31w, /* 0 .. 31, optional trailing ! */
- OP_I32, /* 1 .. 32 */
- OP_I63s, /* -64 .. 63 */
- OP_I255, /* 0 .. 255 */
- OP_Iffff, /* 0 .. 65535 */
+ OP_I7, /* immediate value 0 .. 7 */
+ OP_I15, /* 0 .. 15 */
+ OP_I16, /* 1 .. 16 */
+ OP_I31, /* 0 .. 31 */
+ OP_I31w, /* 0 .. 31, optional trailing ! */
+ OP_I32, /* 1 .. 32 */
+ OP_I63s, /* -64 .. 63 */
+ OP_I255, /* 0 .. 255 */
+ OP_Iffff, /* 0 .. 65535 */
- OP_I4b, /* immediate, prefix optional, 1 .. 4 */
- OP_I7b, /* 0 .. 7 */
- OP_I15b, /* 0 .. 15 */
- OP_I31b, /* 0 .. 31 */
+ OP_I4b, /* immediate, prefix optional, 1 .. 4 */
+ OP_I7b, /* 0 .. 7 */
+ OP_I15b, /* 0 .. 15 */
+ OP_I31b, /* 0 .. 31 */
- OP_SH, /* shifter operand */
- OP_ADDR, /* Memory address expression (any mode) */
- OP_EXP, /* arbitrary expression */
- OP_EXPi, /* same, with optional immediate prefix */
- OP_EXPr, /* same, with optional relocation suffix */
+ OP_SH, /* shifter operand */
+ OP_ADDR, /* Memory address expression (any mode) */
+ OP_EXP, /* arbitrary expression */
+ OP_EXPi, /* same, with optional immediate prefix */
+ OP_EXPr, /* same, with optional relocation suffix */
- OP_CPSF, /* CPS flags */
- OP_ENDI, /* Endianness specifier */
- OP_PSR, /* CPSR/SPSR mask for msr */
+ OP_CPSF, /* CPS flags */
+ OP_ENDI, /* Endianness specifier */
+ OP_PSR, /* CPSR/SPSR mask for msr */
- OP_RR_EX, /* ARM register or expression */
- OP_RL_EXi, /* Thumb low register or expression with imm prefix */
- OP_RRnpc_I0, /* ARM register or literal 0 */
- OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
- OP_RR_EXi, /* ARM register or expression with imm prefix */
- OP_RF_IF, /* FPA register or immediate */
+ OP_RR_EX, /* ARM register or expression */
+ OP_RL_EXi, /* Thumb low register or expression with imm prefix */
+ OP_RRnpc_I0, /* ARM register or literal 0 */
+ OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
+ OP_RR_EXi, /* ARM register or expression with imm prefix */
+ OP_RF_IF, /* FPA register or immediate */
OP_RIWR_RIWC, /* iWMMXt R or C reg */
- /* Optional operands. All have the high bit set. */
- OP_oI7b = 128, /* immediate, prefix optional, 0 .. 7 */
- OP_oI31b, /* 0 .. 31 */
- OP_oI255b, /* 0 .. 255 */
- OP_oIffffb, /* 0 .. 65535 */
- OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
+ /* Optional operands. */
+ OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
+ OP_oI31b, /* 0 .. 31 */
+ OP_oI255b, /* 0 .. 255 */
+ OP_oIffffb, /* 0 .. 65535 */
+ OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
- OP_oRL, /* Thumb low register */
- OP_oRL_EXi, /* Thumb low register or expression */
- OP_oRR_EXi, /* ARM register or expression */
+ OP_oRL, /* Thumb low register */
+ OP_oRL_EXi, /* Thumb low register or expression */
+ OP_oRR_EXi, /* ARM register or expression */
- OP_oSHll, /* LSL immediate */
- OP_oSHar, /* ASR immediate */
- OP_oSHllar, /* LSL or ASR immediate */
- OP_oROR /* ROR 0/8/16/24 */
+ OP_oSHll, /* LSL immediate */
+ OP_oSHar, /* ASR immediate */
+ OP_oSHllar, /* LSL or ASR immediate */
+ OP_oROR, /* ROR 0/8/16/24 */
+
+ OP_FIRST_OPTIONAL = OP_oI7b
};
-/* Generic instruction operand parser. This does no encoding and no
+/* Generic instruction operand parser. This does no encoding and no
semantic validation; it merely squirrels values away in the inst
structure. Returns SUCCESS or FAIL depending on whether the
specified grammar matched. */
@@ -3876,7 +3863,7 @@
/* Check for a no-operand instruction, or an instruction with only
optional operands given none, and bypass the loop if so. */
- if (*p == OP_stop || ((*p & 0200) && *str == 0))
+ if (*p == OP_stop || (*p >= OP_FIRST_OPTIONAL && *str == 0))
goto done;
for (i = 0; ; i++)
@@ -3887,21 +3874,21 @@
case OP_RRnpc:
case OP_oRL:
case OP_RL:
- case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
- case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
- case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
- case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
- case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
- case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
- case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
- case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
- case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
- case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
- case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
- case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
- case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
- case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
- case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
+ case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
+ case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
+ case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
+ case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
+ case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
+ case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
+ case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
+ case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
+ case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
+ case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
+ case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
+ case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
+ case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
+ case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
+ case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
@@ -3919,23 +3906,23 @@
break;
/* Immediates */
- case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
- case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
- case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
- case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
- case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
- case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
- case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
- case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
+ case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
+ case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
+ case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
+ case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
+ case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
+ case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
+ case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
+ case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
- case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
+ case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
case OP_oI7b:
- case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
- case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
+ case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
+ case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
case OP_oI31b:
- case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
- case OP_oI255b: po_imm_or_fail ( 0, 255, TRUE); break;
- case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
+ case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
+ case OP_oI255b: po_imm_or_fail ( 0, 255, TRUE); break;
+ case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
/* Immediate variants */
case OP_oI255c:
@@ -3993,16 +3980,16 @@
break;
/* Register or expression */
- case OP_RR_EX: po_reg_or_goto (REG_TYPE_RN, EXP); break;
- case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
+ case OP_RR_EX: po_reg_or_goto (REG_TYPE_RN, EXP); break;
+ case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
case OP_oRL_EXi:
case OP_oRR_EXi:
case OP_RL_EXi:
- case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
+ case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
/* Register or immediate */
case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
- I0: po_imm_or_fail (0, 0, FALSE); break;
+ I0: po_imm_or_fail (0, 0, FALSE); break;
case OP_RF_IF:
@@ -4015,7 +4002,7 @@
if (val == FAIL)
return FAIL;
/* FPA immediates are encoded as registers 8-15.
- fpa_immediate has already applied the offset. */
+ fpa_immediate has already applied the offset. */
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
}
@@ -4091,7 +4078,7 @@
/* Various value-based sanity checks and shared operations. We
do not signal immediate failures for the register constraints;
- this allows a syntax error to take precedence. */
+ this allows a syntax error to take precedence. */
switch (*p)
{
case OP_RRnpc:
@@ -4126,8 +4113,8 @@
default:
break;
}
-
- /* If we get here, this operand was successfully parsed. */
+
+ /* If we get here, this operand was successfully parsed. */
inst.operands[i].present = 1;
if (*++p == OP_stop)
@@ -4135,7 +4122,7 @@
/* If this is an optional argument, and we have no further
operands, stop. */
- if ((*p & 0200) && *str == '\0')
+ if (*p >= OP_FIRST_OPTIONAL && *str == '\0')
break;
if (skip_past_comma (&str) == FAIL)
@@ -4228,12 +4215,12 @@
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+ inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
#ifndef TE_WINCE
inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
#endif
- inst.reloc.pc_rel = 1;
- inst.size = INSN_SIZE * 2;
+ inst.reloc.pc_rel = 1;
+ inst.size = INSN_SIZE * 2;
}
static void
@@ -4256,8 +4243,8 @@
/* The instruction encoding stores the LSB and MSB,
not the LSB and width. */
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].imm << 7);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].imm << 7;
inst.instruction |= (msb - 1) << 16;
}
@@ -4280,9 +4267,9 @@
/* The instruction encoding stores the LSB and MSB,
not the LSB and width. */
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].imm << 7);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].imm << 7;
inst.instruction |= (msb - 1) << 16;
}
@@ -4296,7 +4283,7 @@
}
inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 0;
+ inst.instruction |= inst.operands[1].reg;
inst.instruction |= inst.operands[2].imm << 7;
inst.instruction |= (inst.operands[3].imm - 1) << 16;
}
@@ -4327,7 +4314,7 @@
inst.error = _("the only suffix valid here is '(plt)'");
return;
}
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ inst.reloc.type = BFD_RELOC_ARM_PLT32;
inst.reloc.pc_rel = 0;
}
else
@@ -4357,7 +4344,7 @@
if (inst.operands[0].isreg)
{
/* Arg is a register; the opcode provided by insns[] is correct.
- It is not illegal to do "blx pc", just useless. */
+ It is not illegal to do "blx pc", just useless. */
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
@@ -4383,7 +4370,7 @@
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
- inst.instruction |= (inst.operands[0].reg << 0);
+ inst.instruction |= inst.operands[0].reg;
}
@@ -4395,12 +4382,12 @@
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in bxj is not really useful"));
- inst.instruction |= (inst.operands[0].reg << 0);
+ inst.instruction |= inst.operands[0].reg;
}
/* Co-processor data operation:
CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
- CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
+ CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
static void
do_cdp (void)
{
@@ -4408,20 +4395,20 @@
inst.instruction |= inst.operands[1].imm << 20;
inst.instruction |= inst.operands[2].reg << 12;
inst.instruction |= inst.operands[3].reg << 16;
- inst.instruction |= inst.operands[4].reg << 0;
+ inst.instruction |= inst.operands[4].reg;
inst.instruction |= inst.operands[5].imm << 5;
}
/* ARM V5 count-leading-zeroes instruction (argument parse)
CLZ{<cond>} <Rd>, <Rm>
Condition defaults to COND_ALWAYS.
- Error if Rd or Rm are R15. */
+ Error if Rd or Rm are R15. */
static void
do_clz (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
}
static void
@@ -4446,7 +4433,7 @@
inst.instruction |= inst.operands[1].imm << 21;
inst.instruction |= inst.operands[2].reg << 12;
inst.instruction |= inst.operands[3].reg << 16;
- inst.instruction |= inst.operands[4].reg << 0;
+ inst.instruction |= inst.operands[4].reg;
inst.instruction |= inst.operands[5].imm << 5;
}
@@ -4470,7 +4457,7 @@
inst.instruction |= inst.operands[1].imm << 4;
inst.instruction |= inst.operands[2].reg << 12;
inst.instruction |= inst.operands[3].reg << 16;
- inst.instruction |= inst.operands[4].reg << 0;
+ inst.instruction |= inst.operands[4].reg;
}
/* ARM V6 change processor state instruction (argument parse)
@@ -4507,7 +4494,7 @@
/* Check for unpredictable uses of writeback. */
if (inst.instruction & LOAD_BIT)
{
- /* Not allowed in LDM type 2. */
+ /* Not allowed in LDM type 2. */
if ((inst.instruction & LDM_TYPE_2_OR_3)
&& ((range & (1 << REG_PC)) == 0))
as_warn (_("writeback of base register is UNPREDICTABLE"));
@@ -4558,7 +4545,7 @@
{
/* encode_addr_mode_3_arm will diagnose overlap between the base
register and the first register written; we have to diagnose
- overlap between the base and the second register written here. */
+ overlap between the base and the second register written here. */
if ((inst.operands[1].reg == inst.operands[0].reg + 1)
&& (inst.operands[1].writeback || inst.operands[1].postind))
@@ -4566,7 +4553,7 @@
"second destination register"));
/* For an index-register load, the index register must not overlap the
- destination (even if not write-back). */
+ destination (even if not write-back). */
else if (inst.operands[1].immisreg
&& (inst.operands[1].imm == inst.operands[0].reg
|| inst.operands[1].imm == inst.operands[0].reg + 1))
@@ -4581,13 +4568,13 @@
LDREX{,B,D,H}{<cond>} <Rd>, [<Rn>]
Condition defaults to COND_ALWAYS.
Error if Rd or Rn are R15.
- See ARMARMv6 A4.1.27: LDREX. */
+ See ARMARMv6 A4.1.27: LDREX. */
static void
do_ldrex (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
@@ -4659,7 +4646,7 @@
}
/* Co-processor register load/store.
- Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
+ Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
static void
do_lstc (void)
{
@@ -4672,15 +4659,15 @@
do_mlas (void)
{
/* This restriction does not apply to mls (nor to mla in v6, but
- that's hard to detect at present). */
- if (inst.operands[0].reg == inst.operands[1].reg
+ that's hard to detect at present). */
+ if (inst.operands[0].reg == inst.operands[1].reg
&& !(inst.instruction & 0x00400000))
as_tsktsk (_("rd and rm should be different in mla"));
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 8);
- inst.instruction |= (inst.operands[3].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 8;
+ inst.instruction |= inst.operands[3].reg << 12;
}
@@ -4691,11 +4678,11 @@
encode_shifter_operand_arm (1);
}
-/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
+/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
static void
do_mov16 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
/* The value is in two pieces: 0:11, 16:19. */
inst.instruction |= (inst.operands[1].imm & 0x00000fff);
inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
@@ -4736,9 +4723,9 @@
static void
do_mul (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 8);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 8;
if (inst.operands[0].reg == inst.operands[1].reg)
as_tsktsk (_("rd and rm should be different in mul"));
@@ -4753,10 +4740,10 @@
static void
do_mull (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
- inst.instruction |= (inst.operands[3].reg << 8);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+ inst.instruction |= inst.operands[3].reg << 8;
/* rdhi, rdlo and rm must all be different. */
if (inst.operands[0].reg == inst.operands[1].reg
@@ -4786,7 +4773,7 @@
{
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg << 0;
+ inst.instruction |= inst.operands[2].reg;
if (inst.operands[3].present)
encode_shift_arm (3);
}
@@ -4802,14 +4789,14 @@
into pkhbt rd, rm, rn. */
inst.instruction &= 0xfff00010;
inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 0;
+ inst.instruction |= inst.operands[1].reg;
inst.instruction |= inst.operands[2].reg << 16;
}
else
{
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg << 0;
+ inst.instruction |= inst.operands[2].reg;
encode_shift_arm (3);
}
}
@@ -4855,9 +4842,9 @@
static void
do_qadd (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 16;
}
/* ARM V6 Perform Two Sixteen Bit Integer Additions. (argument parse).
@@ -4868,16 +4855,16 @@
static void
do_qadd16 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_rbit (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
}
/* ARM V6 REV (Byte Reverse Word) reverses the byte order in a 32-bit
@@ -4889,20 +4876,20 @@
static void
do_rev (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
}
/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
word at the specified address and the following word
respectively.
Unconditionally executed.
- Error if Rn is R15. */
+ Error if Rn is R15. */
static void
do_rfe (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 16;
if (inst.operands[0].writeback)
inst.instruction |= WRITE_BACK;
}
@@ -4914,7 +4901,7 @@
{
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= (inst.operands[1].imm - 1) << 16;
- inst.instruction |= inst.operands[2].reg << 0;
+ inst.instruction |= inst.operands[2].reg;
if (inst.operands[3].present)
encode_shift_arm (3);
@@ -4927,7 +4914,7 @@
{
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].imm << 16;
- inst.instruction |= inst.operands[2].reg << 0;
+ inst.instruction |= inst.operands[2].reg;
if (inst.operands[3].present)
encode_shift_arm (3);
@@ -4938,17 +4925,17 @@
static void
do_ssat16 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= ((inst.operands[1].imm - 1) << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_usat16 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].imm << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].imm << 16;
+ inst.instruction |= inst.operands[2].reg;
}
/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
@@ -4986,10 +4973,10 @@
static void
do_smla (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 8);
- inst.instruction |= (inst.operands[3].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 8;
+ inst.instruction |= inst.operands[3].reg << 12;
}
/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
@@ -5000,10 +4987,10 @@
static void
do_smlal (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
- inst.instruction |= (inst.operands[3].reg << 8);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+ inst.instruction |= inst.operands[3].reg << 8;
if (inst.operands[0].reg == inst.operands[1].reg)
as_tsktsk (_("rdhi and rdlo must be different"));
@@ -5016,12 +5003,12 @@
static void
do_smul (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 8);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 8;
}
-/* ARM V6 srs (argument parse). */
+/* ARM V6 srs (argument parse). */
static void
do_srs (void)
@@ -5039,17 +5026,17 @@
if (reject_overlap (2, 0,1, 0,2))
return;
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 16;
}
static void
do_swap (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 16;
}
/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
@@ -5063,10 +5050,10 @@
static void
do_sxtah (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
- inst.instruction |= (inst.operands[3].imm << 10);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+ inst.instruction |= inst.operands[3].imm << 10;
}
/* ARM V6 SXTH.
@@ -5078,9 +5065,9 @@
static void
do_sxth (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].imm << 10);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].imm << 10;
}
@@ -5100,7 +5087,7 @@
{
/* If there were three operands, operand 1 must be a register. */
if (!inst.operands[1].isreg)
- {
+ {
inst.error = BAD_ARGS;
return;
}
@@ -5121,7 +5108,7 @@
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
return;
}
- else /* Rd, Rs -> Rd, Rd, Rs */
+ else /* Rd, Rs -> Rd, Rd, Rs */
{
Rs = inst.operands[0].reg;
Rn = inst.operands[1].reg;
@@ -5136,7 +5123,7 @@
return;
}
- /* Can't do this for SUB. */
+ /* Can't do this for SUB. */
if (subtract)
{
inst.error = _("subtract valid only on lo regs");
@@ -5167,7 +5154,7 @@
/* Handle the Format 4 instructions that do not have equivalents in other
formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
- BIC and MVN. */
+ BIC and MVN. */
static void
do_t_arit (void)
@@ -5201,7 +5188,7 @@
}
/* THUMB V5 breakpoint instruction (argument parse)
- BKPT <immed_8>. */
+ BKPT <immed_8>. */
static void
do_t_bkpt (void)
@@ -5221,13 +5208,13 @@
{
if (inst.operands[0].isreg)
/* We have a register, so this is BLX(2). */
- inst.instruction |= (inst.operands[0].reg << 3);
+ inst.instruction |= inst.operands[0].reg << 3;
else
{
/* No register. This must be BLX(1). */
inst.instruction = 0xf7ffeffe;
inst.size = 4;
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
+ inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
inst.reloc.pc_rel = 1;
}
}
@@ -5255,8 +5242,8 @@
/* If the destination of the branch is a defined symbol which does not have
the THUMB_FUNC attribute, then we must be calling a function which has
the (interfacearm) attribute. We look for the Thumb entry point to that
- function and change the branch to refer to that function instead. */
- if ( inst.reloc.exp.X_op == O_symbol
+ function and change the branch to refer to that function instead. */
+ if ( inst.reloc.exp.X_op == O_symbol
&& inst.reloc.exp.X_add_symbol != NULL
&& S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
&& ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
@@ -5267,9 +5254,9 @@
static void
do_t_bx (void)
{
- inst.instruction |= (inst.operands[0].reg << 3);
- /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
- should cause the alignment to be checked once it is known. This is
+ inst.instruction |= inst.operands[0].reg << 3;
+ /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
+ should cause the alignment to be checked once it is known. This is
because BX PC only works if the instruction is word aligned. */
}
@@ -5287,7 +5274,7 @@
do_t_cpy (void)
{
inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
- inst.instruction |= (inst.operands[0].reg & 0x7) << 0;
+ inst.instruction |= (inst.operands[0].reg & 0x7);
inst.instruction |= inst.operands[1].reg << 3;
}
@@ -5391,7 +5378,7 @@
inst.error = BAD_HIREG;
return;
}
-
+
if (!inst.operands[1].immisreg)
{
/* Immediate offset. */
@@ -5489,11 +5476,11 @@
{
/* If there were three operands, operand 1 must be a register. */
if (!inst.operands[1].isreg)
- {
+ {
inst.error = BAD_ARGS;
return;
}
- else if (inst.operands[2].isreg) /* Rd, Rs, Rn */
+ else if (inst.operands[2].isreg) /* Rd, Rs, Rn */
{
if (inst.operands[0].reg != inst.operands[1].reg)
{
@@ -5517,7 +5504,7 @@
Rs = inst.operands[0].reg;
/* If we get here, we are doing a shift by an immediate. inst.operands[0].reg
- and Rs are the registers, and inst.reloc is the immediate. */
+ and Rs are the registers, and inst.reloc is the immediate. */
switch (inst.instruction)
{
case T_OPCODE_ASR_R: inst.instruction = T_OPCODE_ASR_I; break;
@@ -5582,8 +5569,8 @@
static void
do_vfp_dp_monadic (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
- inst.instruction |= (inst.operands[1].reg << VFP_REG_Dm);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
}
static void
@@ -5597,9 +5584,9 @@
static void
do_vfp_dp_dyadic (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
- inst.instruction |= (inst.operands[1].reg << VFP_REG_Dn);
- inst.instruction |= (inst.operands[2].reg << VFP_REG_Dm);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
@@ -5611,13 +5598,13 @@
static void
do_vfp_dp_compare_z (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
+ inst.instruction |= inst.operands[0].reg << 12;
}
static void
do_vfp_dp_sp_cvt (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
+ inst.instruction |= inst.operands[0].reg << 12;
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sm);
}
@@ -5625,13 +5612,13 @@
do_vfp_sp_dp_cvt (void)
{
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
- inst.instruction |= (inst.operands[1].reg << VFP_REG_Dm);
+ inst.instruction |= inst.operands[1].reg;
}
static void
do_vfp_reg_from_sp (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sn);
}
@@ -5644,8 +5631,8 @@
return;
}
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
vfp_sp_encode_reg (inst.operands[2].reg, VFP_REG_Sm);
}
@@ -5653,7 +5640,7 @@
do_vfp_sp_from_reg (void)
{
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sn);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[1].reg << 12;
}
static void
@@ -5666,52 +5653,52 @@
}
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sm);
- inst.instruction |= (inst.operands[1].reg << 12);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
}
static void
do_vfp_reg_from_dp (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << VFP_REG_Dn);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_vfp_reg2_from_dp (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << VFP_REG_Dm);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_vfp_dp_from_reg (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dn);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
}
static void
do_vfp_dp_from_reg2 (void)
{
- inst.instruction |= (inst.operands[0].reg << VFP_REG_Dm);
- inst.instruction |= (inst.operands[1].reg << 12);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
}
static void
do_vfp_reg_from_ctrl (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_vfp_ctrl_from_reg (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
}
static void
@@ -5724,7 +5711,7 @@
static void
do_vfp_dp_ldst (void)
{
- inst.instruction |= inst.operands[0].reg << VFP_REG_Dd;
+ inst.instruction |= inst.operands[0].reg << 12;
encode_cp_address_arm (1, FALSE, TRUE, 0);
}
@@ -5805,7 +5792,7 @@
}
-/* FPA instructions. Also in a logical order. */
+/* FPA instructions. Also in a logical order. */
/* FP control register read/write.
Format: <WFS|RFS|WFC|RFC>{cond} Rn */
@@ -5813,7 +5800,7 @@
static void
do_fpa_ctrl (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
}
static void
@@ -5841,32 +5828,32 @@
static void
do_fpa_from_reg (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
}
static void
do_fpa_to_reg (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg;
}
static void
do_fpa_ldst (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
encode_cp_address_arm (1, TRUE, TRUE, 0);
}
static void
do_fpa_ldmstm (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
switch (inst.operands[1].imm)
{
- case 1: inst.instruction |= CP_T_X; break;
- case 2: inst.instruction |= CP_T_Y; break;
+ case 1: inst.instruction |= CP_T_X; break;
+ case 2: inst.instruction |= CP_T_Y; break;
case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
case 4: break;
default: abort ();
@@ -5889,7 +5876,7 @@
if (inst.instruction & (PRE_INDEX | WRITE_BACK))
inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
else
- inst.instruction |= PRE_INDEX; /* prevent use of unindexed mode */
+ inst.instruction |= PRE_INDEX; /* prevent use of unindexed mode */
if (!(inst.instruction & INDEX_UP))
inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
@@ -5901,7 +5888,7 @@
}
-/* iWMMXt instructions: strictly in alphabetical order. */
+/* iWMMXt instructions: strictly in alphabetical order. */
static void
do_iwmmxt_tandorc (void)
@@ -5913,100 +5900,100 @@
static void
do_iwmmxt_tbcst (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_iwmmxt_textrc (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].imm;
}
static void
do_iwmmxt_textrm (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
inst.instruction |= inst.operands[2].imm;
}
static void
do_iwmmxt_tinsr (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
inst.instruction |= inst.operands[2].imm;
}
static void
do_iwmmxt_tmcr (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
}
static void
do_iwmmxt_tmcrr (void)
{
- inst.instruction |= (inst.operands[0].reg << 0);
- inst.instruction |= (inst.operands[1].reg << 12);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
}
static void
do_iwmmxt_tmia (void)
{
- inst.instruction |= (inst.operands[0].reg << 5);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 5;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 12;
}
static void
do_iwmmxt_tmovmsk (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_iwmmxt_tmrc (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_iwmmxt_tmrrc (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_iwmmxt_waligni (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
- inst.instruction |= (inst.operands[3].imm << 20);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+ inst.instruction |= inst.operands[3].imm << 20;
}
static void
do_iwmmxt_wmov (void)
{
/* WMOV rD, rN is an alias for WOR rD, rN, rN. */
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
}
static void
do_iwmmxt_wldst (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
encode_cp_address_arm (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
}
@@ -6032,31 +6019,31 @@
static void
do_iwmmxt_wrwr (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_iwmmxt_wrwrwcg (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_iwmmxt_wrwrwr (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
static void
do_iwmmxt_wshufh (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
inst.instruction |= (inst.operands[2].imm & 0x0f);
}
@@ -6065,28 +6052,28 @@
do_iwmmxt_wzero (void)
{
/* WZERO reg is an alias for WANDN reg, reg, reg. */
- inst.instruction |= (inst.operands[0].reg << 0);
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[0].reg << 16);
+ inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[0].reg << 16;
}
/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
operations first, then control, shift, and load/store. */
-/* Insn like "foo X,Y". */
+/* Insn like "foo X,Y". */
static void
do_mav_binops_1 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
static void
do_mav_binops_2 (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg << 12;
}
/* Insns like "foo X,Y,Z". */
@@ -6094,17 +6081,17 @@
static void
do_mav_triple_1 (void)
{
- inst.instruction |= (inst.operands[0].reg << 16);
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 16;
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 12;
}
static void
do_mav_triple_2 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
- inst.instruction |= (inst.operands[2].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
}
/* Insns like "foo W,X,Y,Z".
@@ -6113,24 +6100,24 @@
static void
do_mav_quad (void)
{
- inst.instruction |= (inst.operands[0].reg << 5);
- inst.instruction |= (inst.operands[1].reg << 12);
- inst.instruction |= (inst.operands[2].reg << 16);
- inst.instruction |= (inst.operands[3].reg << 0);
+ inst.instruction |= inst.operands[0].reg << 5;
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
+ inst.instruction |= inst.operands[3].reg;
}
/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
static void
do_mav_dspsc_1 (void)
{
- inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= inst.operands[1].reg << 12;
}
/* cfmv32sc<cond> MVDX[15:0],DSPSC. */
static void
do_mav_dspsc_0 (void)
{
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= inst.operands[0].reg << 12;
}
/* Maverick shift immediate instructions.
@@ -6147,7 +6134,7 @@
/* Bits 0-3 of the insn should have bits 0-3 of the immediate.
Bits 5-7 of the insn should have bits 4-6 of the immediate.
- Bit 4 should be 0. */
+ Bit 4 should be 0. */
imm = (imm & 0xf) | ((imm & 0x70) << 1);
inst.instruction |= imm;
@@ -6164,7 +6151,7 @@
encode_cp_address_arm (1, TRUE, TRUE, 0);
}
-/* XScale instructions. Also sorted arithmetic before move. */
+/* XScale instructions. Also sorted arithmetic before move. */
/* Xscale multiply-accumulate (argument parse)
MIAcc acc0,Rm,Rs
@@ -6174,8 +6161,8 @@
static void
do_xsc_mia (void)
{
- inst.instruction |= (inst.operands[1].reg << 0);
- inst.instruction |= (inst.operands[2].reg << 12);
+ inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= inst.operands[2].reg << 12;
}
/* Xscale move-accumulator-register (argument parse)
@@ -6185,8 +6172,8 @@
static void
do_xsc_mar (void)
{
- inst.instruction |= (inst.operands[1].reg << 12);
- inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= inst.operands[1].reg << 12;
+ inst.instruction |= inst.operands[2].reg << 16;
}
/* Xscale move-register-accumulator (argument parse)
@@ -6199,28 +6186,28 @@
if (reject_overlap (1, 0,1))
return;
- inst.instruction |= (inst.operands[0].reg << 12);
- inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
}
-/* Overall per-instruction processing. */
+/* Overall per-instruction processing. */
/* We need to be able to fix up arbitrary expressions in some statements.
This is so that we can handle symbols that are an arbitrary distance from
the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
which returns part of an address in a form which will be valid for
- a data instruction. We do this by pushing the expression into a symbol
+ a data instruction. We do this by pushing the expression into a symbol
in the expr_section, and creating a fix for that. */
static void
-fix_new_arm (fragS * frag,
- int where,
- short int size,
+fix_new_arm (fragS * frag,
+ int where,
+ short int size,
expressionS * exp,
- int pc_rel,
- int reloc)
+ int pc_rel,
+ int reloc)
{
- fixS * new_fix;
+ fixS * new_fix;
switch (exp->X_op)
{
@@ -6344,7 +6331,7 @@
return;
}
- mapping_state (MAP_ARM);
+ mapping_state (MAP_ARM);
inst.instruction = opcode->value;
inst.size = INSN_SIZE;
if (!parse_operands (p, opcode->operands))
@@ -6384,19 +6371,19 @@
/* Note - do not allow local symbols (.Lxxx) to be labeled
as Thumb functions. This is because these labels, whilst
they exist inside Thumb code, are not the entry points for
- possible ARM->Thumb calls. Also, these labels can be used
+ possible ARM->Thumb calls. Also, these labels can be used
as part of a computed goto or switch statement. eg gcc
can generate code that looks like this:
- ldr r2, [pc, .Laaa]
- lsl r3, r3, #2
- ldr r2, [r3, r2]
- mov pc, r2
+ ldr r2, [pc, .Laaa]
+ lsl r3, r3, #2
+ ldr r2, [r3, r2]
+ mov pc, r2
.Lbbb: .word .Lxxx
.Lccc: .word .Lyyy
..etc...
- .Laaa: .word Lbbb
+ .Laaa: .word Lbbb
The first instruction loads the address of the jump table.
The second instruction converts a table index into a byte offset.
@@ -6454,8 +6441,8 @@
/* Table of all register names defined by default. The user can
define additional names with .req. Note that all register names
- should appear in both upper and lowercase variants. Some registers
- also have mixed-case names. */
+ should appear in both upper and lowercase variants. Some registers
+ also have mixed-case names. */
#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
#define REGNUM(p,n,t) REGDEF(p##n, n, t)
@@ -6501,7 +6488,7 @@
REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
- /* VFP SP registers. */
+ /* VFP SP registers. */
REGSET(s,VFS),
REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
@@ -6514,7 +6501,7 @@
REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
- /* VFP DP Registers. */
+ /* VFP DP Registers. */
REGSET(d,VFD), REGSET(D,VFS),
/* VFP control registers. */
@@ -6533,12 +6520,12 @@
REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
REGDEF(DSPSC,0,DSPSC),
- /* iWMMXt data registers - p0, c0-15. */
+ /* iWMMXt data registers - p0, c0-15. */
REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
/* iWMMXt control registers - p1, c0-3. */
- REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
- REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
+ REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
+ REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
@@ -6565,11 +6552,11 @@
{"flg", PSR_f},
{"ctl", PSR_c},
- /* Individual flags. */
- {"f", PSR_f},
+ /* Individual flags. */
+ {"f", PSR_f},
{"c", PSR_c},
- {"x", PSR_x},
- {"s", PSR_s},
+ {"x", PSR_x},
+ {"s", PSR_s},
/* Combinations of flags. */
{"fs", PSR_f | PSR_s},
{"fx", PSR_f | PSR_x},
@@ -6633,32 +6620,32 @@
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
};
-/* Table of all shift-in-operand names. */
+/* Table of all shift-in-operand names. */
static const struct asm_shift_name shift_names [] =
{
- { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
- { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
- { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
- { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
- { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
- { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
+ { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
+ { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
+ { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
+ { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
+ { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
+ { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
};
/* Table of all explicit relocation names. */
static struct reloc_entry reloc_names[] =
{
#ifdef OBJ_ELF
- { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
- { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
- { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
- { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
- { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
- { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
+ { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
+ { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
+ { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
+ { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
+ { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
+ { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
#endif
};
/* Table of all conditional suffixes. 0xF... is for special-case,
- unconditional instructions. */
+ unconditional instructions. */
static const struct asm_cond conds[] =
{
{"eq", 0x00000000},
@@ -6678,22 +6665,22 @@
{"al", 0xe0000000}
};
-/* Table of ARM-format instructions. */
+/* Table of ARM-format instructions. */
-/* Macros for gluing together operand strings. */
-#define OPS0() { OP_stop, }
-#define OPS1(a) { OP_##a, }
-#define OPS2(a,b) { OP_##a,OP_##b, }
-#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
-#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
-#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
+/* Macros for gluing together operand strings. */
+#define OPS0() { OP_stop, }
+#define OPS1(a) { OP_##a, }
+#define OPS2(a,b) { OP_##a,OP_##b, }
+#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
+#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
+#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
/* These macros assemble the conditional variants of each instruction
- from its bare form. */
+ from its bare form. */
#define CE(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #mnem "eq", 0x0 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #mnem "ne", 0x1 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #mnem "cs", 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
@@ -6714,7 +6701,7 @@
{ #mnem "al", 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
#define CM(m1, m2, opc, nops, ops, aenc) \
- { #m1 #m2, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
+ { #m1 #m2, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #m1 "eq" #m2, 0x0 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #m1 "ne" #m2, 0x1 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
{ #m1 "cs" #m2, 0x2 ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }, \
@@ -6735,1153 +6722,1153 @@
{ #m1 "al" #m2, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
#define UE(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
#define UF(mnem, opc, nops, ops, aenc) \
- { #mnem, 0xf ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
+ { #mnem, 0xf ## opc, ARM_VARIANT, OPS##nops ops, do_ ## aenc }
static const struct asm_opcode insns[] =
{
#define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
- CE(and, 0000000, 3, (RR, RR, SH), arit),
- CM(and,s, 0100000, 3, (RR, RR, SH), arit),
- CE(eor, 0200000, 3, (RR, RR, SH), arit),
- CM(eor,s, 0300000, 3, (RR, RR, SH), arit),
- CE(sub, 0400000, 3, (RR, RR, SH), arit),
- CM(sub,s, 0500000, 3, (RR, RR, SH), arit),
- CE(rsb, 0600000, 3, (RR, RR, SH), arit),
- CM(rsb,s, 0700000, 3, (RR, RR, SH), arit),
- CE(add, 0800000, 3, (RR, RR, SH), arit),
- CM(add,s, 0900000, 3, (RR, RR, SH), arit),
- CE(adc, 0a00000, 3, (RR, RR, SH), arit),
- CM(adc,s, 0b00000, 3, (RR, RR, SH), arit),
- CE(sbc, 0c00000, 3, (RR, RR, SH), arit),
- CM(sbc,s, 0d00000, 3, (RR, RR, SH), arit),
- CE(rsc, 0e00000, 3, (RR, RR, SH), arit),
- CM(rsc,s, 0f00000, 3, (RR, RR, SH), arit),
- CE(orr, 1800000, 3, (RR, RR, SH), arit),
- CM(orr,s, 1900000, 3, (RR, RR, SH), arit),
- CE(bic, 1c00000, 3, (RR, RR, SH), arit),
- CM(bic,s, 1d00000, 3, (RR, RR, SH), arit),
-
- CE(tst, 1100000, 2, (RR, SH), cmp),
- CM(tst,s, 1100000, 2, (RR, SH), cmp),
- CM(tst,p, 110f000, 2, (RR, SH), cmp),
- CE(teq, 1300000, 2, (RR, SH), cmp),
- CM(teq,s, 1300000, 2, (RR, SH), cmp),
- CM(teq,p, 130f000, 2, (RR, SH), cmp),
- CE(cmp, 1500000, 2, (RR, SH), cmp),
- CM(cmp,s, 1500000, 2, (RR, SH), cmp),
- CM(cmp,p, 150f000, 2, (RR, SH), cmp),
- CE(cmn, 1700000, 2, (RR, SH), cmp),
- CM(cmn,s, 1700000, 2, (RR, SH), cmp),
- CM(cmn,p, 170f000, 2, (RR, SH), cmp),
+ CE(and, 0000000, 3, (RR, RR, SH), arit),
+ CM(and,s, 0100000, 3, (RR, RR, SH), arit),
+ CE(eor, 0200000, 3, (RR, RR, SH), arit),
+ CM(eor,s, 0300000, 3, (RR, RR, SH), arit),
+ CE(sub, 0400000, 3, (RR, RR, SH), arit),
+ CM(sub,s, 0500000, 3, (RR, RR, SH), arit),
+ CE(rsb, 0600000, 3, (RR, RR, SH), arit),
+ CM(rsb,s, 0700000, 3, (RR, RR, SH), arit),
+ CE(add, 0800000, 3, (RR, RR, SH), arit),
+ CM(add,s, 0900000, 3, (RR, RR, SH), arit),
+ CE(adc, 0a00000, 3, (RR, RR, SH), arit),
+ CM(adc,s, 0b00000, 3, (RR, RR, SH), arit),
+ CE(sbc, 0c00000, 3, (RR, RR, SH), arit),
+ CM(sbc,s, 0d00000, 3, (RR, RR, SH), arit),
+ CE(rsc, 0e00000, 3, (RR, RR, SH), arit),
+ CM(rsc,s, 0f00000, 3, (RR, RR, SH), arit),
+ CE(orr, 1800000, 3, (RR, RR, SH), arit),
+ CM(orr,s, 1900000, 3, (RR, RR, SH), arit),
+ CE(bic, 1c00000, 3, (RR, RR, SH), arit),
+ CM(bic,s, 1d00000, 3, (RR, RR, SH), arit),
- CE(mov, 1a00000, 2, (RR, SH), mov),
- CM(mov,s, 1b00000, 2, (RR, SH), mov),
- CE(mvn, 1e00000, 2, (RR, SH), mov),
- CM(mvn,s, 1f00000, 2, (RR, SH), mov),
+ CE(tst, 1100000, 2, (RR, SH), cmp),
+ CM(tst,s, 1100000, 2, (RR, SH), cmp),
+ CM(tst,p, 110f000, 2, (RR, SH), cmp),
+ CE(teq, 1300000, 2, (RR, SH), cmp),
+ CM(teq,s, 1300000, 2, (RR, SH), cmp),
+ CM(teq,p, 130f000, 2, (RR, SH), cmp),
+ CE(cmp, 1500000, 2, (RR, SH), cmp),
+ CM(cmp,s, 1500000, 2, (RR, SH), cmp),
+ CM(cmp,p, 150f000, 2, (RR, SH), cmp),
+ CE(cmn, 1700000, 2, (RR, SH), cmp),
+ CM(cmn,s, 1700000, 2, (RR, SH), cmp),
+ CM(cmn,p, 170f000, 2, (RR, SH), cmp),
- CE(ldr, 4100000, 2, (RR, ADDR), ldst),
- CM(ldr,b, 4500000, 2, (RR, ADDR), ldst),
- CM(ldr,t, 4300000, 2, (RR, ADDR), ldstt),
- CM(ldr,bt, 4700000, 2, (RR, ADDR), ldstt),
- CE(str, 4000000, 2, (RR, ADDR), ldst),
- CM(str,b, 4400000, 2, (RR, ADDR), ldst),
- CM(str,t, 4200000, 2, (RR, ADDR), ldstt),
- CM(str,bt, 4600000, 2, (RR, ADDR), ldstt),
+ CE(mov, 1a00000, 2, (RR, SH), mov),
+ CM(mov,s, 1b00000, 2, (RR, SH), mov),
+ CE(mvn, 1e00000, 2, (RR, SH), mov),
+ CM(mvn,s, 1f00000, 2, (RR, SH), mov),
- CM(stm,ia, 8800000, 2, (RRw, REGLST), ldmstm),
- CM(stm,ib, 9800000, 2, (RRw, REGLST), ldmstm),
- CM(stm,da, 8000000, 2, (RRw, REGLST), ldmstm),
- CM(stm,db, 9000000, 2, (RRw, REGLST), ldmstm),
- CM(stm,fd, 9000000, 2, (RRw, REGLST), ldmstm),
- CM(stm,fa, 9800000, 2, (RRw, REGLST), ldmstm),
- CM(stm,ea, 8800000, 2, (RRw, REGLST), ldmstm),
- CM(stm,ed, 8000000, 2, (RRw, REGLST), ldmstm),
+ CE(ldr, 4100000, 2, (RR, ADDR), ldst),
+ CM(ldr,b, 4500000, 2, (RR, ADDR), ldst),
+ CM(ldr,t, 4300000, 2, (RR, ADDR), ldstt),
+ CM(ldr,bt, 4700000, 2, (RR, ADDR), ldstt),
+ CE(str, 4000000, 2, (RR, ADDR), ldst),
+ CM(str,b, 4400000, 2, (RR, ADDR), ldst),
+ CM(str,t, 4200000, 2, (RR, ADDR), ldstt),
+ CM(str,bt, 4600000, 2, (RR, ADDR), ldstt),
- CM(ldm,ia, 8900000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,ib, 9900000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,da, 8100000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,db, 9100000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,fd, 8900000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,fa, 8100000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,ea, 9100000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,ed, 9900000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ia, 8800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ib, 9800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,da, 8000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,db, 9000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,fd, 9000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,fa, 9800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ea, 8800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ed, 8000000, 2, (RRw, REGLST), ldmstm),
- CE(swi, f000000, 1, (EXPi), swi),
+ CM(ldm,ia, 8900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ib, 9900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,da, 8100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,db, 9100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,fd, 8900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,fa, 8100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ea, 9100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ed, 9900000, 2, (RRw, REGLST), ldmstm),
+
+ CE(swi, f000000, 1, (EXPi), swi),
#ifdef TE_WINCE
- /* XXX This is the wrong place to do this. Think multi-arch. */
- CE(b, a000000, 1, (EXPr), branch),
- CE(bl, b000000, 1, (EXPr), branch),
+ /* XXX This is the wrong place to do this. Think multi-arch. */
+ CE(b, a000000, 1, (EXPr), branch),
+ CE(bl, b000000, 1, (EXPr), branch),
#else
- CE(b, afffffe, 1, (EXPr), branch),
- CE(bl, bfffffe, 1, (EXPr), branch),
+ CE(b, afffffe, 1, (EXPr), branch),
+ CE(bl, bfffffe, 1, (EXPr), branch),
#endif
/* Pseudo ops. */
- CE(adr, 28f0000, 2, (RR, EXP), adr),
- CM(adr,l, 28f0000, 2, (RR, EXP), adrl),
- CE(nop, 1a00000, 1, (oI255c), nop),
+ CE(adr, 28f0000, 2, (RR, EXP), adr),
+ CM(adr,l, 28f0000, 2, (RR, EXP), adrl),
+ CE(nop, 1a00000, 1, (oI255c), nop),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
- CE(mul, 0000090, 3, (RRnpc, RRnpc, RR), mul),
- CM(mul,s, 0100090, 3, (RRnpc, RRnpc, RR), mul),
- CE(mla, 0200090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
- CM(mla,s, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
+ CE(mul, 0000090, 3, (RRnpc, RRnpc, RR), mul),
+ CM(mul,s, 0100090, 3, (RRnpc, RRnpc, RR), mul),
+ CE(mla, 0200090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+ CM(mla,s, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
- /* Generic coprocessor instructions. */
- CE(cdp, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
- CE(ldc, c100000, 3, (RCP, RCN, ADDR), lstc),
- CM(ldc,l, c500000, 3, (RCP, RCN, ADDR), lstc),
- CE(stc, c000000, 3, (RCP, RCN, ADDR), lstc),
- CM(stc,l, c400000, 3, (RCP, RCN, ADDR), lstc),
- CE(mcr, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
- CE(mrc, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ /* Generic coprocessor instructions. */
+ CE(cdp, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
+ CE(ldc, c100000, 3, (RCP, RCN, ADDR), lstc),
+ CM(ldc,l, c500000, 3, (RCP, RCN, ADDR), lstc),
+ CE(stc, c000000, 3, (RCP, RCN, ADDR), lstc),
+ CM(stc,l, c400000, 3, (RCP, RCN, ADDR), lstc),
+ CE(mcr, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ CE(mrc, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
- CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), swap),
- CM(swp,b, 1400090, 3, (RRnpc, RRnpc, RRnpcb), swap),
+ CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), swap),
+ CM(swp,b, 1400090, 3, (RRnpc, RRnpc, RRnpcb), swap),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
- CE(mrs, 10f0000, 2, (RR, PSR), mrs),
- CE(msr, 120f000, 2, (PSR, RR_EXi), msr),
+#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
+ CE(mrs, 10f0000, 2, (RR, PSR), mrs),
+ CE(msr, 120f000, 2, (PSR, RR_EXi), msr),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
- CE(smull, 0c00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CE(umull, 0800090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CE(smlal, 0e00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CE(umlal, 0a00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
- CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
+ CE(smull, 0c00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(umull, 0800090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(smlal, 0e00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(umlal, 0a00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
- CM(ldr,h, 01000b0, 2, (RR, ADDR), ldstv4),
- CM(ldr,sh, 01000f0, 2, (RR, ADDR), ldstv4),
- CM(ldr,sb, 01000d0, 2, (RR, ADDR), ldstv4),
- CM(str,h, 00000b0, 2, (RR, ADDR), ldstv4),
+#define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
+ CM(ldr,h, 01000b0, 2, (RR, ADDR), ldstv4),
+ CM(ldr,sh, 01000f0, 2, (RR, ADDR), ldstv4),
+ CM(ldr,sb, 01000d0, 2, (RR, ADDR), ldstv4),
+ CM(str,h, 00000b0, 2, (RR, ADDR), ldstv4),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
/* ARM Architecture 4T. */
/* Note: bx (and blx) are required on V5, even if the processor does
- not support Thumb. */
- CE(bx, 12fff10, 1, (RR), bx),
+ not support Thumb. */
+ CE(bx, 12fff10, 1, (RR), bx),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
+#define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
/* Note: blx has 2 variants; the .value coded here is for
BLX(2). Only this variant has conditional execution. */
- CE(blx, 12fff30, 1, (RR_EXr), blx),
- CE(clz, 16f0f10, 2, (RRnpc, RRnpc), clz),
- UE(bkpt, 1200070, 1, (oIffffb), bkpt),
- UF(ldc2, c100000, 3, (RCP, RCN, ADDR), lstc),
- UF(ldc2l, c500000, 3, (RCP, RCN, ADDR), lstc),
- UF(stc2, c000000, 3, (RCP, RCN, ADDR), lstc),
- UF(stc2l, c400000, 3, (RCP, RCN, ADDR), lstc),
- UF(cdp2, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
- UF(mcr2, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
- UF(mrc2, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ CE(blx, 12fff30, 1, (RR_EXr), blx),
+ CE(clz, 16f0f10, 2, (RRnpc, RRnpc), clz),
+ UE(bkpt, 1200070, 1, (oIffffb), bkpt),
+ UF(ldc2, c100000, 3, (RCP, RCN, ADDR), lstc),
+ UF(ldc2l, c500000, 3, (RCP, RCN, ADDR), lstc),
+ UF(stc2, c000000, 3, (RCP, RCN, ADDR), lstc),
+ UF(stc2l, c400000, 3, (RCP, RCN, ADDR), lstc),
+ UF(cdp2, e000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp),
+ UF(mcr2, e000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
+ UF(mrc2, e100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
- CE(smlabb, 1000080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlatb, 10000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlabt, 10000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlatt, 10000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlabb, 1000080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlatb, 10000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlabt, 10000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlatt, 10000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlawb, 1200080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlawt, 12000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlawb, 1200080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlawt, 12000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlalbb, 1400080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlaltb, 14000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlalbt, 14000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlaltt, 14000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlalbb, 1400080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaltb, 14000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlalbt, 14000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaltt, 14000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smulbb, 1600080, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smultb, 16000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smulbt, 16000c0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smultt, 16000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulbb, 1600080, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smultb, 16000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulbt, 16000c0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smultt, 16000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smulwb, 12000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smulwt, 12000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulwb, 12000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulwt, 12000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(qadd, 1000050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qdadd, 1400050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qsub, 1200050, 3, (RRnpc, RRnpc, RRnpc), qadd),
- CE(qdsub, 1600050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qadd, 1000050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qdadd, 1400050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qsub, 1200050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qdsub, 1600050, 3, (RRnpc, RRnpc, RRnpc), qadd),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
- UF(pld, 450f000, 1, (ADDR), pld),
- CM(ldr,d, 00000d0, 2, (RR, ADDR), ldrd),
- CM(str,d, 00000f0, 2, (RR, ADDR), ldrd),
+ UF(pld, 450f000, 1, (ADDR), pld),
+ CM(ldr,d, 00000d0, 2, (RR, ADDR), ldrd),
+ CM(str,d, 00000f0, 2, (RR, ADDR), ldrd),
- CE(mcrr, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
- CE(mrrc, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(mcrr, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(mrrc, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
- CE(bxj, 12fff20, 1, (RR), bxj),
+ CE(bxj, 12fff20, 1, (RR), bxj),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
- UF(cps, 1020000, 1, (I31b), cps),
- UF(cpsie, 1080000, 2, (CPSF, oI31b), cpsi),
- UF(cpsid, 10c0000, 2, (CPSF, oI31b), cpsi),
- CE(ldrex, 1900f9f, 2, (RRnpc, RRnpcb), ldrex),
- UF(mcrr2, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
- UF(mrrc2, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
- CE(pkhbt, 6800010, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt),
- CE(pkhtb, 6800050, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb),
- CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qadd8, 6200f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qaddsubx, 6200f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsub16, 6200f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsub8, 6200ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(qsubaddx, 6200f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(sadd16, 6100f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(sadd8, 6100f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(saddsubx, 6100f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shadd16, 6300f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shadd8, 6300f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shaddsubx, 6300f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsub16, 6300f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsub8, 6300ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(shsubaddx, 6300f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssub16, 6100f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssub8, 6100ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(ssubaddx, 6100f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uadd16, 6500f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uadd8, 6500f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uaddsubx, 6500f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhadd16, 6700f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhadd8, 6700f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhaddsubx, 6700f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsub16, 6700f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsub8, 6700ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uhsubaddx, 6700f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqadd16, 6600f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqadd8, 6600f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqaddsubx, 6600f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsub16, 6600f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsub8, 6600ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(uqsubaddx, 6600f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usub16, 6500f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usub8, 6500ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(usubaddx, 6500f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- CE(rev, 6bf0f30, 2, (RRnpc, RRnpc), rev),
- CE(rev16, 6bf0fb0, 2, (RRnpc, RRnpc), rev),
- CE(revsh, 6ff0fb0, 2, (RRnpc, RRnpc), rev),
- UF(rfeia, 8900a00, 1, (RRw), rfe),
- UF(rfeib, 9900a00, 1, (RRw), rfe),
- UF(rfeda, 8100a00, 1, (RRw), rfe),
- UF(rfedb, 9100a00, 1, (RRw), rfe),
- UF(rfefd, 8900a00, 1, (RRw), rfe),
- UF(rfefa, 9900a00, 1, (RRw), rfe),
- UF(rfeea, 8100a00, 1, (RRw), rfe),
- UF(rfeed, 9100a00, 1, (RRw), rfe),
- CE(sxtah, 6b00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(sxtab16, 6800070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(sxtab, 6a00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(sxth, 6bf0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(sxtb16, 68f0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(sxtb, 6af0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(uxtah, 6f00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(uxtab16, 6c00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(uxtab, 6e00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
- CE(uxth, 6ff0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(uxtb16, 6cf0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(uxtb, 6ef0070, 3, (RRnpc, RRnpc, oROR), sxth),
- CE(sel, 68000b0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
- UF(setend, 1010000, 1, (ENDI), setend),
- CE(smlad, 7000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smladx, 7000030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlald, 7400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlaldx, 7400030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlsd, 7000050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlsdx, 7000070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlsld, 7400050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smlsldx, 7400070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smmla, 7500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smmlar, 7500030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smmls, 75000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smmlsr, 75000f0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smmul, 750f010, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smmulr, 750f030, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smuad, 700f010, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smuadx, 700f030, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smusd, 700f050, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smusdx, 700f070, 3, (RRnpc, RRnpc, RRnpc), smul),
- UF(srsia, 8cd0500, 1, (I31w), srs),
- UF(srsib, 9cd0500, 1, (I31w), srs),
- UF(srsda, 84d0500, 1, (I31w), srs),
- UF(srsdb, 94d0500, 1, (I31w), srs),
- CE(ssat, 6a00010, 4, (RRnpc, I32, RRnpc, oSHllar), ssat),
- CE(ssat16, 6a00f30, 3, (RRnpc, I16, RRnpc), ssat16),
- CE(strex, 1800f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
- CE(umaal, 0400090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(usad8, 780f010, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(usada8, 7800010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(usat, 6e00010, 4, (RRnpc, I31, RRnpc, oSHllar), usat),
- CE(usat16, 6e00f30, 3, (RRnpc, I15, RRnpc), usat16),
+ UF(cps, 1020000, 1, (I31b), cps),
+ UF(cpsie, 1080000, 2, (CPSF, oI31b), cpsi),
+ UF(cpsid, 10c0000, 2, (CPSF, oI31b), cpsi),
+ CE(ldrex, 1900f9f, 2, (RRnpc, RRnpcb), ldrex),
+ UF(mcrr2, c400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ UF(mrrc2, c500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(pkhbt, 6800010, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt),
+ CE(pkhtb, 6800050, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb),
+ CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qadd8, 6200f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qaddsubx, 6200f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsub16, 6200f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsub8, 6200ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsubaddx, 6200f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(sadd16, 6100f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(sadd8, 6100f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(saddsubx, 6100f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shadd16, 6300f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shadd8, 6300f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shaddsubx, 6300f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsub16, 6300f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsub8, 6300ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsubaddx, 6300f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssub16, 6100f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssub8, 6100ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssubaddx, 6100f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uadd16, 6500f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uadd8, 6500f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uaddsubx, 6500f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhadd16, 6700f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhadd8, 6700f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhaddsubx, 6700f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsub16, 6700f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsub8, 6700ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsubaddx, 6700f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqadd16, 6600f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqadd8, 6600f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqaddsubx, 6600f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsub16, 6600f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsub8, 6600ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsubaddx, 6600f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usub16, 6500f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usub8, 6500ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usubaddx, 6500f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(rev, 6bf0f30, 2, (RRnpc, RRnpc), rev),
+ CE(rev16, 6bf0fb0, 2, (RRnpc, RRnpc), rev),
+ CE(revsh, 6ff0fb0, 2, (RRnpc, RRnpc), rev),
+ UF(rfeia, 8900a00, 1, (RRw), rfe),
+ UF(rfeib, 9900a00, 1, (RRw), rfe),
+ UF(rfeda, 8100a00, 1, (RRw), rfe),
+ UF(rfedb, 9100a00, 1, (RRw), rfe),
+ UF(rfefd, 8900a00, 1, (RRw), rfe),
+ UF(rfefa, 9900a00, 1, (RRw), rfe),
+ UF(rfeea, 8100a00, 1, (RRw), rfe),
+ UF(rfeed, 9100a00, 1, (RRw), rfe),
+ CE(sxtah, 6b00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxtab16, 6800070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxtab, 6a00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxth, 6bf0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sxtb16, 68f0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sxtb, 6af0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtah, 6f00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxtab16, 6c00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxtab, 6e00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxth, 6ff0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtb16, 6cf0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtb, 6ef0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sel, 68000b0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ UF(setend, 1010000, 1, (ENDI), setend),
+ CE(smlad, 7000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smladx, 7000030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlald, 7400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaldx, 7400030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlsd, 7000050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlsdx, 7000070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlsld, 7400050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlsldx, 7400070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smmla, 7500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmlar, 7500030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmls, 75000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmlsr, 75000f0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmul, 750f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smmulr, 750f030, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smuad, 700f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smuadx, 700f030, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smusd, 700f050, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smusdx, 700f070, 3, (RRnpc, RRnpc, RRnpc), smul),
+ UF(srsia, 8cd0500, 1, (I31w), srs),
+ UF(srsib, 9cd0500, 1, (I31w), srs),
+ UF(srsda, 84d0500, 1, (I31w), srs),
+ UF(srsdb, 94d0500, 1, (I31w), srs),
+ CE(ssat, 6a00010, 4, (RRnpc, I32, RRnpc, oSHllar), ssat),
+ CE(ssat16, 6a00f30, 3, (RRnpc, I16, RRnpc), ssat16),
+ CE(strex, 1800f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ CE(umaal, 0400090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(usad8, 780f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(usada8, 7800010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(usat, 6e00010, 4, (RRnpc, I31, RRnpc, oSHllar), usat),
+ CE(usat16, 6e00f30, 3, (RRnpc, I15, RRnpc), usat16),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6K
- CE(ldrexb, 1d00f9f, 2, (RRnpc, RRnpcb), ldrex),
- CE(ldrexd, 1b00f9f, 2, (RRnpc, RRnpcb), ldrex),
- CE(ldrexh, 1f00f9f, 2, (RRnpc, RRnpcb), ldrex),
- CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
- CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
- CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
- UF(clrex, 57ff01f, 0, (), empty),
- CE(wfe, 320f002, 0, (), empty),
- CE(wfi, 320f003, 0, (), empty),
- CE(yield, 320f001, 0, (), empty),
- CE(sev, 320f004, 0, (), empty),
+ CE(ldrexb, 1d00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrexd, 1b00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(ldrexh, 1f00f9f, 2, (RRnpc, RRnpcb), ldrex),
+ CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, RRnpcb), strex),
+ UF(clrex, 57ff01f, 0, (), empty),
+ CE(wfe, 320f002, 0, (), empty),
+ CE(wfi, 320f003, 0, (), empty),
+ CE(yield, 320f001, 0, (), empty),
+ CE(sev, 320f004, 0, (), empty),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6Z
- CE(smi, 1600070, 1, (EXPi), smi),
+ CE(smi, 1600070, 1, (EXPi), smi),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6T2
- CE(bfc, 7c0001f, 3, (RRnpc, I31, I32), bfc),
- CE(bfi, 7c00010, 4, (RRnpc, RRnpc_I0, I31, I32), bfi),
- CE(sbfx, 7a00050, 4, (RR, RR, I31, I32), bfx),
- CE(ubfx, 7e00050, 4, (RR, RR, I31, I32), bfx),
+ CE(bfc, 7c0001f, 3, (RRnpc, I31, I32), bfc),
+ CE(bfi, 7c00010, 4, (RRnpc, RRnpc_I0, I31, I32), bfi),
+ CE(sbfx, 7a00050, 4, (RR, RR, I31, I32), bfx),
+ CE(ubfx, 7e00050, 4, (RR, RR, I31, I32), bfx),
- CE(mls, 0600090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
- CE(movw, 3000000, 2, (RRnpc, Iffff), mov16),
- CE(movt, 3400000, 2, (RRnpc, Iffff), mov16),
- CE(rbit, 3ff0f30, 2, (RR, RR), rbit),
+ CE(mls, 0600090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+ CE(movw, 3000000, 2, (RRnpc, Iffff), mov16),
+ CE(movt, 3400000, 2, (RRnpc, Iffff), mov16),
+ CE(rbit, 3ff0f30, 2, (RR, RR), rbit),
- CM(ldr,ht, 03000b0, 2, (RR, ADDR), ldsttv4),
- CM(ldr,sht, 03000f0, 2, (RR, ADDR), ldsttv4),
- CM(ldr,sbt, 03000d0, 2, (RR, ADDR), ldsttv4),
- CM(str,ht, 02000b0, 2, (RR, ADDR), ldsttv4),
+ CM(ldr,ht, 03000b0, 2, (RR, ADDR), ldsttv4),
+ CM(ldr,sht, 03000f0, 2, (RR, ADDR), ldsttv4),
+ CM(ldr,sbt, 03000d0, 2, (RR, ADDR), ldsttv4),
+ CM(str,ht, 02000b0, 2, (RR, ADDR), ldsttv4),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
- CE(wfs, e200110, 1, (RR), fpa_ctrl),
- CE(rfs, e300110, 1, (RR), fpa_ctrl),
- CE(wfc, e400110, 1, (RR), fpa_ctrl),
- CE(rfc, e500110, 1, (RR), fpa_ctrl),
+ CE(wfs, e200110, 1, (RR), fpa_ctrl),
+ CE(rfs, e300110, 1, (RR), fpa_ctrl),
+ CE(wfc, e400110, 1, (RR), fpa_ctrl),
+ CE(rfc, e500110, 1, (RR), fpa_ctrl),
- CM(ldf,s, c100100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,d, c108100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,e, c500100, 2, (RF, ADDR), fpa_ldst),
- CM(ldf,p, c508100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,s, c100100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,d, c108100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,e, c500100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,p, c508100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,s, c000100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,d, c008100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,e, c400100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,p, c408100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,s, c000100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,d, c008100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,e, c400100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,p, c408100, 2, (RF, ADDR), fpa_ldst),
- CM(mvf,s, e008100, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sp, e008120, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sm, e008140, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,sz, e008160, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,d, e008180, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dp, e0081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dm, e0081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,dz, e0081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,e, e088100, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,ep, e088120, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,em, e088140, 2, (RF, RF_IF), fpa_monadic),
- CM(mvf,ez, e088160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,s, e008100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sp, e008120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sm, e008140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sz, e008160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,d, e008180, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dp, e0081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dm, e0081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dz, e0081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,e, e088100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,ep, e088120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,em, e088140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,ez, e088160, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,s, e108100, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sp, e108120, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sm, e108140, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,sz, e108160, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,d, e108180, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dp, e1081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dm, e1081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,dz, e1081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,e, e188100, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,ep, e188120, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,em, e188140, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,ez, e188160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,s, e108100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sp, e108120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sm, e108140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sz, e108160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,d, e108180, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dp, e1081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dm, e1081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dz, e1081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,e, e188100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,ep, e188120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,em, e188140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,ez, e188160, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,s, e208100, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sp, e208120, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sm, e208140, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,sz, e208160, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,d, e208180, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dp, e2081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dm, e2081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,dz, e2081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,e, e288100, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,ep, e288120, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,em, e288140, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,ez, e288160, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,s, e208100, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sp, e208120, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sm, e208140, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sz, e208160, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,d, e208180, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dp, e2081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dm, e2081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dz, e2081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,e, e288100, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,ep, e288120, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,em, e288140, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,ez, e288160, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,s, e308100, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sp, e308120, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sm, e308140, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,sz, e308160, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,d, e308180, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dp, e3081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dm, e3081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,dz, e3081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,e, e388100, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,ep, e388120, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,em, e388140, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,ez, e388160, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,s, e308100, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sp, e308120, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sm, e308140, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sz, e308160, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,d, e308180, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dp, e3081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dm, e3081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dz, e3081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,e, e388100, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,ep, e388120, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,em, e388140, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,ez, e388160, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,s, e408100, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sp, e408120, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sm, e408140, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,sz, e408160, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,d, e408180, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dp, e4081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dm, e4081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,dz, e4081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,e, e488100, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,ep, e488120, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,em, e488140, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,ez, e488160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,s, e408100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sp, e408120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sm, e408140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sz, e408160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,d, e408180, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dp, e4081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dm, e4081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dz, e4081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,e, e488100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,ep, e488120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,em, e488140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,ez, e488160, 2, (RF, RF_IF), fpa_monadic),
- CM(log,s, e508100, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sp, e508120, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sm, e508140, 2, (RF, RF_IF), fpa_monadic),
- CM(log,sz, e508160, 2, (RF, RF_IF), fpa_monadic),
- CM(log,d, e508180, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dp, e5081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dm, e5081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,dz, e5081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(log,e, e588100, 2, (RF, RF_IF), fpa_monadic),
- CM(log,ep, e588120, 2, (RF, RF_IF), fpa_monadic),
- CM(log,em, e588140, 2, (RF, RF_IF), fpa_monadic),
- CM(log,ez, e588160, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,s, e508100, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sp, e508120, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sm, e508140, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sz, e508160, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,d, e508180, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dp, e5081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dm, e5081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dz, e5081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,e, e588100, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,ep, e588120, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,em, e588140, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,ez, e588160, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,s, e608100, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sp, e608120, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sm, e608140, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,sz, e608160, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,d, e608180, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dp, e6081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dm, e6081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,dz, e6081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,e, e688100, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,ep, e688120, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,em, e688140, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,ez, e688160, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,s, e608100, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sp, e608120, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sm, e608140, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sz, e608160, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,d, e608180, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dp, e6081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dm, e6081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dz, e6081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,e, e688100, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,ep, e688120, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,em, e688140, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,ez, e688160, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,s, e708100, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sp, e708120, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sm, e708140, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,sz, e708160, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,d, e708180, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dp, e7081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dm, e7081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dz, e7081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,e, e788100, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,ep, e788120, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,em, e788140, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,dz, e788160, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,s, e708100, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sp, e708120, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sm, e708140, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sz, e708160, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,d, e708180, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dp, e7081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dm, e7081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dz, e7081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,e, e788100, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,ep, e788120, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,em, e788140, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dz, e788160, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,s, e808100, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sp, e808120, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sm, e808140, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,sz, e808160, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,d, e808180, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dp, e8081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dm, e8081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,dz, e8081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,e, e888100, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,ep, e888120, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,em, e888140, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,ez, e888160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,s, e808100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sp, e808120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sm, e808140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sz, e808160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,d, e808180, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dp, e8081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dm, e8081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dz, e8081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,e, e888100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,ep, e888120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,em, e888140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,ez, e888160, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,s, e908100, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sp, e908120, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sm, e908140, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,sz, e908160, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,d, e908180, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dp, e9081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dm, e9081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,dz, e9081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,e, e988100, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,ep, e988120, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,em, e988140, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,ez, e988160, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,s, e908100, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sp, e908120, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sm, e908140, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sz, e908160, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,d, e908180, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dp, e9081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dm, e9081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dz, e9081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,e, e988100, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,ep, e988120, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,em, e988140, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,ez, e988160, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,s, ea08100, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sp, ea08120, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sm, ea08140, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,sz, ea08160, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,d, ea08180, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dp, ea081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dm, ea081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,dz, ea081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,e, ea88100, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,ep, ea88120, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,em, ea88140, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,ez, ea88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,s, ea08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sp, ea08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sm, ea08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sz, ea08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,d, ea08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dp, ea081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dm, ea081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dz, ea081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,e, ea88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,ep, ea88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,em, ea88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,ez, ea88160, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,s, eb08100, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sp, eb08120, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sm, eb08140, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,sz, eb08160, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,d, eb08180, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dp, eb081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dm, eb081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,dz, eb081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,e, eb88100, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,ep, eb88120, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,em, eb88140, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,ez, eb88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,s, eb08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sp, eb08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sm, eb08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sz, eb08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,d, eb08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dp, eb081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dm, eb081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dz, eb081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,e, eb88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,ep, eb88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,em, eb88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,ez, eb88160, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,s, ec08100, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sp, ec08120, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sm, ec08140, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,sz, ec08160, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,d, ec08180, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dp, ec081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dm, ec081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,dz, ec081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,e, ec88100, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,ep, ec88120, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,em, ec88140, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,ez, ec88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,s, ec08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sp, ec08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sm, ec08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sz, ec08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,d, ec08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dp, ec081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dm, ec081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dz, ec081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,e, ec88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,ep, ec88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,em, ec88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,ez, ec88160, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,s, ed08100, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sp, ed08120, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sm, ed08140, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,sz, ed08160, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,d, ed08180, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dp, ed081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dm, ed081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,dz, ed081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,e, ed88100, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,ep, ed88120, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,em, ed88140, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,ez, ed88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,s, ed08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sp, ed08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sm, ed08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sz, ed08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,d, ed08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dp, ed081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dm, ed081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dz, ed081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,e, ed88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,ep, ed88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,em, ed88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,ez, ed88160, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,s, ee08100, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sp, ee08120, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sm, ee08140, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,sz, ee08160, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,d, ee08180, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dp, ee081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dm, ee081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,dz, ee081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,e, ee88100, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,ep, ee88120, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,em, ee88140, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,ez, ee88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,s, ee08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sp, ee08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sm, ee08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sz, ee08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,d, ee08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dp, ee081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dm, ee081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dz, ee081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,e, ee88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,ep, ee88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,em, ee88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,ez, ee88160, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,s, ef08100, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sp, ef08120, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sm, ef08140, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,sz, ef08160, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,d, ef08180, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dp, ef081a0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dm, ef081c0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,dz, ef081e0, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,e, ef88100, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,ep, ef88120, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,em, ef88140, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,ez, ef88160, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,s, ef08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sp, ef08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sm, ef08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sz, ef08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,d, ef08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dp, ef081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dm, ef081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dz, ef081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,e, ef88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,ep, ef88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,em, ef88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,ez, ef88160, 2, (RF, RF_IF), fpa_monadic),
- CM(adf,s, e000100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sp, e000120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sm, e000140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,sz, e000160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,d, e000180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dp, e0001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dm, e0001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,dz, e0001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,e, e080100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,ep, e080120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,em, e080140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(adf,ez, e080160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,s, e000100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sp, e000120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sm, e000140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sz, e000160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,d, e000180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dp, e0001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dm, e0001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dz, e0001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,e, e080100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,ep, e080120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,em, e080140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,ez, e080160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,s, e200100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sp, e200120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sm, e200140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,sz, e200160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,d, e200180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dp, e2001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dm, e2001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,dz, e2001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,e, e280100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,ep, e280120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,em, e280140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,ez, e280160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,s, e200100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sp, e200120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sm, e200140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sz, e200160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,d, e200180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dp, e2001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dm, e2001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dz, e2001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,e, e280100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,ep, e280120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,em, e280140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,ez, e280160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,s, e300100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sp, e300120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sm, e300140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,sz, e300160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,d, e300180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dp, e3001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dm, e3001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,dz, e3001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,e, e380100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,ep, e380120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,em, e380140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,ez, e380160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,s, e300100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sp, e300120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sm, e300140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sz, e300160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,d, e300180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dp, e3001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dm, e3001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dz, e3001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,e, e380100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,ep, e380120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,em, e380140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,ez, e380160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,s, e100100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sp, e100120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sm, e100140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,sz, e100160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,d, e100180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dp, e1001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dm, e1001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,dz, e1001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,e, e180100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,ep, e180120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,em, e180140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,ez, e180160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,s, e100100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sp, e100120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sm, e100140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sz, e100160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,d, e100180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dp, e1001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dm, e1001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dz, e1001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,e, e180100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,ep, e180120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,em, e180140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,ez, e180160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,s, e400100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sp, e400120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sm, e400140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,sz, e400160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,d, e400180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dp, e4001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dm, e4001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,dz, e4001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,e, e480100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,ep, e480120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,em, e480140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,ez, e480160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,s, e400100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sp, e400120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sm, e400140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sz, e400160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,d, e400180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dp, e4001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dm, e4001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dz, e4001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,e, e480100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,ep, e480120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,em, e480140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,ez, e480160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,s, e500100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sp, e500120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sm, e500140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,sz, e500160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,d, e500180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dp, e5001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dm, e5001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,dz, e5001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,e, e580100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,ep, e580120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,em, e580140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,ez, e580160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,s, e500100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sp, e500120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sm, e500140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sz, e500160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,d, e500180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dp, e5001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dm, e5001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dz, e5001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,e, e580100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,ep, e580120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,em, e580140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,ez, e580160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,s, e600100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sp, e600120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sm, e600140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,sz, e600160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,d, e600180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dp, e6001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dm, e6001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,dz, e6001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,e, e680100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,ep, e680120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,em, e680140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,ez, e680160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,s, e600100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sp, e600120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sm, e600140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sz, e600160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,d, e600180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dp, e6001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dm, e6001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dz, e6001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,e, e680100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,ep, e680120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,em, e680140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,ez, e680160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,s, e700100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sp, e700120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sm, e700140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,sz, e700160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,d, e700180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dp, e7001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dm, e7001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,dz, e7001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,e, e780100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,ep, e780120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,em, e780140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,ez, e780160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,s, e700100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sp, e700120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sm, e700140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sz, e700160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,d, e700180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dp, e7001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dm, e7001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dz, e7001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,e, e780100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,ep, e780120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,em, e780140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,ez, e780160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,s, e800100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sp, e800120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sm, e800140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,sz, e800160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,d, e800180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dp, e8001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dm, e8001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,dz, e8001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,e, e880100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,ep, e880120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,em, e880140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,ez, e880160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,s, e800100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sp, e800120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sm, e800140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sz, e800160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,d, e800180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dp, e8001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dm, e8001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dz, e8001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,e, e880100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,ep, e880120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,em, e880140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,ez, e880160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,s, e900100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sp, e900120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sm, e900140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,sz, e900160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,d, e900180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dp, e9001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dm, e9001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,dz, e9001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,e, e980100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,ep, e980120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,em, e980140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,ez, e980160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,s, e900100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sp, e900120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sm, e900140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sz, e900160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,d, e900180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dp, e9001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dm, e9001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dz, e9001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,e, e980100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,ep, e980120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,em, e980140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,ez, e980160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,s, ea00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sp, ea00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sm, ea00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,sz, ea00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,d, ea00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dp, ea001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dm, ea001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,dz, ea001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,e, ea80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,ep, ea80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,em, ea80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,ez, ea80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,s, ea00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sp, ea00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sm, ea00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sz, ea00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,d, ea00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dp, ea001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dm, ea001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dz, ea001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,e, ea80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,ep, ea80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,em, ea80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,ez, ea80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,s, eb00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sp, eb00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sm, eb00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,sz, eb00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,d, eb00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dp, eb001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dm, eb001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,dz, eb001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,e, eb80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,ep, eb80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,em, eb80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,ez, eb80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,s, eb00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sp, eb00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sm, eb00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sz, eb00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,d, eb00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dp, eb001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dm, eb001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dz, eb001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,e, eb80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,ep, eb80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,em, eb80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,ez, eb80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,s, ec00100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sp, ec00120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sm, ec00140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,sz, ec00160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,d, ec00180, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dp, ec001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dm, ec001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,dz, ec001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,e, ec80100, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,ep, ec80120, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,em, ec80140, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,ez, ec80160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,s, ec00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sp, ec00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sm, ec00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sz, ec00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,d, ec00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dp, ec001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dm, ec001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dz, ec001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,e, ec80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,ep, ec80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,em, ec80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,ez, ec80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
- CM(cmf,e, ed0f110, 2, (RF, RF_IF), fpa_cmp),
- CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
- CM(cnf,e, ef0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
+ CM(cmf,e, ed0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
+ CM(cnf,e, ef0f110, 2, (RF, RF_IF), fpa_cmp),
/* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should
not be an optional suffix, but part of the instruction. To be
compatible, we accept either. */
- CE(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
- CE(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
- CM(flt,s, e000110, 2, (RF, RR), fpa_from_reg),
- CM(flt,sp, e000130, 2, (RF, RR), fpa_from_reg),
- CM(flt,sm, e000150, 2, (RF, RR), fpa_from_reg),
- CM(flt,sz, e000170, 2, (RF, RR), fpa_from_reg),
- CM(flt,d, e000190, 2, (RF, RR), fpa_from_reg),
- CM(flt,dp, e0001b0, 2, (RF, RR), fpa_from_reg),
- CM(flt,dm, e0001d0, 2, (RF, RR), fpa_from_reg),
- CM(flt,dz, e0001f0, 2, (RF, RR), fpa_from_reg),
- CM(flt,e, e080110, 2, (RF, RR), fpa_from_reg),
- CM(flt,ep, e080130, 2, (RF, RR), fpa_from_reg),
- CM(flt,em, e080150, 2, (RF, RR), fpa_from_reg),
- CM(flt,ez, e080170, 2, (RF, RR), fpa_from_reg),
+ CM(flt,s, e000110, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sp, e000130, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sm, e000150, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sz, e000170, 2, (RF, RR), fpa_from_reg),
+ CM(flt,d, e000190, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dp, e0001b0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dm, e0001d0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dz, e0001f0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,e, e080110, 2, (RF, RR), fpa_from_reg),
+ CM(flt,ep, e080130, 2, (RF, RR), fpa_from_reg),
+ CM(flt,em, e080150, 2, (RF, RR), fpa_from_reg),
+ CM(flt,ez, e080170, 2, (RF, RR), fpa_from_reg),
/* The implementation of the FIX instruction is broken on some
assemblers, in that it accepts a precision specifier as well as a
rounding specifier, despite the fact that this is meaningless.
To be more compatible, we accept it as well, though of course it
does not set any bits. */
- CE(fix, e100110, 2, (RR, RF), fpa_to_reg),
- CM(fix,p, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,m, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,z, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,sp, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,sm, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,sz, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,dp, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,dm, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,dz, e100170, 2, (RR, RF), fpa_to_reg),
- CM(fix,ep, e100130, 2, (RR, RF), fpa_to_reg),
- CM(fix,em, e100150, 2, (RR, RF), fpa_to_reg),
- CM(fix,ez, e100170, 2, (RR, RF), fpa_to_reg),
+ CE(fix, e100110, 2, (RR, RF), fpa_to_reg),
+ CM(fix,p, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,m, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,z, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sp, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sm, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sz, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dp, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dm, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dz, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,ep, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,em, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,ez, e100170, 2, (RR, RF), fpa_to_reg),
/* Instructions that were new with the real FPA, call them V2. */
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V2
- CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CM(lfm,fd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CM(lfm,ea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CM(sfm,fd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CM(sfm,ea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(lfm,fd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(lfm,ea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(sfm,fd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ CM(sfm,ea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
/* Moves and type conversions. */
- CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
- CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
- CE(fmstat, ef1fa10, 0, (), empty),
- CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fmrx, ef00a10, 2, (RR, RVC), vfp_reg_from_ctrl),
- CE(fmxr, ee00a10, 2, (RVC, RR), vfp_ctrl_from_reg),
+ CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
+ CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
+ CE(fmstat, ef1fa10, 0, (), empty),
+ CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fmrx, ef00a10, 2, (RR, RVC), vfp_reg_from_ctrl),
+ CE(fmxr, ee00a10, 2, (RVC, RR), vfp_ctrl_from_reg),
- /* Memory operations. */
- CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
- CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
- CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ /* Memory operations. */
+ CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
/* Monadic operations. */
- CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
- /* Dyadic operations. */
- CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ /* Dyadic operations. */
+ CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
/* Comparisons. */
- CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
- CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
+ CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
+ CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
/* Moves and type conversions. */
- CE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_from_reg),
- CE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_from_reg),
- CE(fmrdh, e300b10, 2, (RR, RVD), vfp_reg_from_dp),
- CE(fmrdl, e100b10, 2, (RR, RVD), vfp_reg_from_dp),
- CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_from_reg),
+ CE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_from_reg),
+ CE(fmrdh, e300b10, 2, (RR, RVD), vfp_reg_from_dp),
+ CE(fmrdl, e100b10, 2, (RR, RVD), vfp_reg_from_dp),
+ CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- /* Memory operations. */
- CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
- CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
- CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ /* Memory operations. */
+ CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
/* Monadic operations. */
- CE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_monadic),
- /* Dyadic operations. */
- CE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
- CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ /* Dyadic operations. */
+ CE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
/* Comparisons. */
- CE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_compare_z),
- CE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_monadic),
- CE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_compare_z),
+ CE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_compare_z),
+ CE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_compare_z),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V2
- CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
- CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
- CE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_from_reg2),
- CE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_reg2_from_dp),
+ CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
+ CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
+ CE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_from_reg2),
+ CE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_reg2_from_dp),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
- CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
- CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
+#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
+ CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
+ CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
- CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
- CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
- CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
- CE(tbcstb, e400010, 2, (RR, RIWR), iwmmxt_tbcst),
- CE(tbcsth, e400050, 2, (RR, RIWR), iwmmxt_tbcst),
- CE(tbcstw, e400090, 2, (RR, RIWR), iwmmxt_tbcst),
- CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrmub, e100070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmuh, e500070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmuw, e900070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsb, e100078, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsh, e500078, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsw, e900078, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tmcr, e000110, 2, (RIWC, RR), iwmmxt_tmcr),
- CE(tmcrr, c400000, 3, (RIWR, RR, RR), iwmmxt_tmcrr),
- CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmovmskb, e100030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmovmskh, e500030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmovmskw, e900030, 2, (RR, RIWR), iwmmxt_tmovmsk),
- CE(tmrc, e100110, 2, (RR, RIWC), iwmmxt_tmrc),
- CE(tmrrc, c500000, 3, (RR, RR, RIWR), iwmmxt_tmrrc),
- CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
- CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
- CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
- CE(waccb, e0001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wacch, e4001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(waccw, e8001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
- CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wand, e200000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
- CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wor, e000000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
- CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
- CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
- CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
- CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
+ CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
+ CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
+ CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
+ CE(tbcstb, e400010, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(tbcsth, e400050, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(tbcstw, e400090, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrmub, e100070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmuh, e500070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmuw, e900070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsb, e100078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsh, e500078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsw, e900078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tmcr, e000110, 2, (RIWC, RR), iwmmxt_tmcr),
+ CE(tmcrr, c400000, 3, (RIWR, RR, RR), iwmmxt_tmcrr),
+ CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmovmskb, e100030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmovmskh, e500030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmovmskw, e900030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmrc, e100110, 2, (RR, RIWC), iwmmxt_tmrc),
+ CE(tmrrc, c500000, 3, (RR, RR, RIWR), iwmmxt_tmrrc),
+ CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
+ CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
+ CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
+ CE(waccb, e0001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wacch, e4001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(waccw, e8001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
+ CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wand, e200000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
+ CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wor, e000000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
+ CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
#undef ARM_VARIANT
-#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
- CE(cfldrs, c100400, 2, (RMF, ADDR), mav_ldst),
- CE(cfldrd, c500400, 2, (RMD, ADDR), mav_ldst),
- CE(cfldr32, c100500, 2, (RMFX, ADDR), mav_ldst),
- CE(cfldr64, c500500, 2, (RMDX, ADDR), mav_ldst),
- CE(cfstrs, c000400, 2, (RMF, ADDR), mav_ldst),
- CE(cfstrd, c400400, 2, (RMD, ADDR), mav_ldst),
- CE(cfstr32, c000500, 2, (RMFX, ADDR), mav_ldst),
- CE(cfstr64, c400500, 2, (RMDX, ADDR), mav_ldst),
- CE(cfmvsr, e000450, 2, (RMF, RR), mav_binops_2),
- CE(cfmvrs, e100450, 2, (RR, RMF), mav_binops_1),
- CE(cfmvdlr, e000410, 2, (RMD, RR), mav_binops_2),
- CE(cfmvrdl, e100410, 2, (RR, RMD), mav_binops_1),
- CE(cfmvdhr, e000430, 2, (RMD, RR), mav_binops_2),
- CE(cfmvrdh, e100430, 2, (RR, RMD), mav_binops_1),
- CE(cfmv64lr, e000510, 2, (RMDX, RR), mav_binops_2),
- CE(cfmvr64l, e100510, 2, (RR, RMDX), mav_binops_1),
- CE(cfmv64hr, e000530, 2, (RMDX, RR), mav_binops_2),
- CE(cfmvr64h, e100530, 2, (RR, RMDX), mav_binops_1),
- CE(cfmval32, e200440, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32al, e100440, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmvam32, e200460, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32am, e100460, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmvah32, e200480, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32ah, e100480, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmva32, e2004a0, 2, (RMAX, RMFX), mav_binops_1),
- CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), mav_binops_1),
- CE(cfmva64, e2004c0, 2, (RMAX, RMDX), mav_binops_1),
- CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), mav_binops_1),
- CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc_1),
- CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), mav_dspsc_0),
- CE(cfcpys, e000400, 2, (RMF, RMF), mav_binops_1),
- CE(cfcpyd, e000420, 2, (RMD, RMD), mav_binops_1),
- CE(cfcvtsd, e000460, 2, (RMD, RMF), mav_binops_1),
- CE(cfcvtds, e000440, 2, (RMF, RMD), mav_binops_1),
- CE(cfcvt32s, e000480, 2, (RMF, RMFX), mav_binops_1),
- CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), mav_binops_1),
- CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), mav_binops_1),
- CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), mav_binops_1),
- CE(cfcvts32, e100580, 2, (RMFX, RMF), mav_binops_1),
- CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), mav_binops_1),
- CE(cftruncs32,e1005c0, 2, (RMFX, RMF), mav_binops_1),
- CE(cftruncd32,e1005e0, 2, (RMFX, RMD), mav_binops_1),
- CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple_1),
- CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple_1),
- CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
- CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
- CE(cfcmps, e100490, 3, (RR, RMF, RMF), mav_triple_2),
- CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), mav_triple_2),
- CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), mav_triple_2),
- CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), mav_triple_2),
- CE(cfabss, e300400, 2, (RMF, RMF), mav_binops_1),
- CE(cfabsd, e300420, 2, (RMD, RMD), mav_binops_1),
- CE(cfnegs, e300440, 2, (RMF, RMF), mav_binops_1),
- CE(cfnegd, e300460, 2, (RMD, RMD), mav_binops_1),
- CE(cfadds, e300480, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfmuls, e100400, 3, (RMF, RMF, RMF), mav_triple_2),
- CE(cfmuld, e100420, 3, (RMD, RMD, RMD), mav_triple_2),
- CE(cfabs32, e300500, 2, (RMFX, RMFX), mav_binops_1),
- CE(cfabs64, e300520, 2, (RMDX, RMDX), mav_binops_1),
- CE(cfneg32, e300540, 2, (RMFX, RMFX), mav_binops_1),
- CE(cfneg64, e300560, 2, (RMDX, RMDX), mav_binops_1),
- CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), mav_triple_2),
- CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), mav_triple_2),
- CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
- CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
+ CE(cfldrs, c100400, 2, (RMF, ADDR), mav_ldst),
+ CE(cfldrd, c500400, 2, (RMD, ADDR), mav_ldst),
+ CE(cfldr32, c100500, 2, (RMFX, ADDR), mav_ldst),
+ CE(cfldr64, c500500, 2, (RMDX, ADDR), mav_ldst),
+ CE(cfstrs, c000400, 2, (RMF, ADDR), mav_ldst),
+ CE(cfstrd, c400400, 2, (RMD, ADDR), mav_ldst),
+ CE(cfstr32, c000500, 2, (RMFX, ADDR), mav_ldst),
+ CE(cfstr64, c400500, 2, (RMDX, ADDR), mav_ldst),
+ CE(cfmvsr, e000450, 2, (RMF, RR), mav_binops_2),
+ CE(cfmvrs, e100450, 2, (RR, RMF), mav_binops_1),
+ CE(cfmvdlr, e000410, 2, (RMD, RR), mav_binops_2),
+ CE(cfmvrdl, e100410, 2, (RR, RMD), mav_binops_1),
+ CE(cfmvdhr, e000430, 2, (RMD, RR), mav_binops_2),
+ CE(cfmvrdh, e100430, 2, (RR, RMD), mav_binops_1),
+ CE(cfmv64lr, e000510, 2, (RMDX, RR), mav_binops_2),
+ CE(cfmvr64l, e100510, 2, (RR, RMDX), mav_binops_1),
+ CE(cfmv64hr, e000530, 2, (RMDX, RR), mav_binops_2),
+ CE(cfmvr64h, e100530, 2, (RR, RMDX), mav_binops_1),
+ CE(cfmval32, e200440, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32al, e100440, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmvam32, e200460, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32am, e100460, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmvah32, e200480, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32ah, e100480, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmva32, e2004a0, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmva64, e2004c0, 2, (RMAX, RMDX), mav_binops_1),
+ CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), mav_binops_1),
+ CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc_1),
+ CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), mav_dspsc_0),
+ CE(cfcpys, e000400, 2, (RMF, RMF), mav_binops_1),
+ CE(cfcpyd, e000420, 2, (RMD, RMD), mav_binops_1),
+ CE(cfcvtsd, e000460, 2, (RMD, RMF), mav_binops_1),
+ CE(cfcvtds, e000440, 2, (RMF, RMD), mav_binops_1),
+ CE(cfcvt32s, e000480, 2, (RMF, RMFX), mav_binops_1),
+ CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), mav_binops_1),
+ CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), mav_binops_1),
+ CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), mav_binops_1),
+ CE(cfcvts32, e100580, 2, (RMFX, RMF), mav_binops_1),
+ CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), mav_binops_1),
+ CE(cftruncs32,e1005c0, 2, (RMFX, RMF), mav_binops_1),
+ CE(cftruncd32,e1005e0, 2, (RMFX, RMD), mav_binops_1),
+ CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple_1),
+ CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple_1),
+ CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
+ CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
+ CE(cfcmps, e100490, 3, (RR, RMF, RMF), mav_triple_2),
+ CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), mav_triple_2),
+ CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), mav_triple_2),
+ CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), mav_triple_2),
+ CE(cfabss, e300400, 2, (RMF, RMF), mav_binops_1),
+ CE(cfabsd, e300420, 2, (RMD, RMD), mav_binops_1),
+ CE(cfnegs, e300440, 2, (RMF, RMF), mav_binops_1),
+ CE(cfnegd, e300460, 2, (RMD, RMD), mav_binops_1),
+ CE(cfadds, e300480, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfmuls, e100400, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfmuld, e100420, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfabs32, e300500, 2, (RMFX, RMFX), mav_binops_1),
+ CE(cfabs64, e300520, 2, (RMDX, RMDX), mav_binops_1),
+ CE(cfneg32, e300540, 2, (RMFX, RMFX), mav_binops_1),
+ CE(cfneg64, e300560, 2, (RMDX, RMDX), mav_binops_1),
+ CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
};
@@ -7899,90 +7886,90 @@
static const struct asm_opcode tinsns[] =
{
#define THUMB_VARIANT ARM_EXT_V4T /* Thumb v1 (ARMv4T). */
- TI(adc, 4140, 3, (RL, RL, oRL), t_arit),
+ TI(adc, 4140, 3, (RL, RL, oRL), t_arit),
TI(add, 0000, 3, (RR, RR_EXi, oRR_EXi), t_add_sub),
- TI(and, 4000, 3, (RL, RL, oRL), t_arit),
+ TI(and, 4000, 3, (RL, RL, oRL), t_arit),
TI(asr, 4100, 3, (RL, RL_EXi, oRL_EXi), t_shift),
- TI(b, e7fe, 1, (EXP), t_branch12),
- TI(beq, d0fe, 1, (EXP), t_branch9),
- TI(bne, d1fe, 1, (EXP), t_branch9),
- TI(bcs, d2fe, 1, (EXP), t_branch9),
- TI(bhs, d2fe, 1, (EXP), t_branch9),
- TI(bcc, d3fe, 1, (EXP), t_branch9),
- TI(bul, d3fe, 1, (EXP), t_branch9),
- TI(blo, d3fe, 1, (EXP), t_branch9),
- TI(bmi, d4fe, 1, (EXP), t_branch9),
- TI(bpl, d5fe, 1, (EXP), t_branch9),
- TI(bvs, d6fe, 1, (EXP), t_branch9),
- TI(bvc, d7fe, 1, (EXP), t_branch9),
- TI(bhi, d8fe, 1, (EXP), t_branch9),
- TI(bls, d9fe, 1, (EXP), t_branch9),
- TI(bge, dafe, 1, (EXP), t_branch9),
- TI(blt, dbfe, 1, (EXP), t_branch9),
- TI(bgt, dcfe, 1, (EXP), t_branch9),
- TI(ble, ddfe, 1, (EXP), t_branch9),
- TI(bal, defe, 1, (EXP), t_branch9),
- TI(bic, 4380, 3, (RL, RL, oRL), t_arit),
- TI(bl, f7fffffe, 1, (EXP), t_branch23),
- TI(bx, 4700, 1, (RR), t_bx),
- TI(cmn, 42c0, 3, (RL, RL, oRL), t_arit),
- TI(cmp, 4280, 2, (RR, RR_EXi), t_mov_cmp),
- TI(eor, 4040, 3, (RL, RL, oRL), t_arit),
- TI(ldmia, c800, 2, (RLw, REGLST), t_ldmstm),
- TI(ldr, 5800, 2, (RL, ADDR), t_ldst),
- TI(ldrb, 5c00, 2, (RL, ADDR), t_ldst),
- TI(ldrh, 5a00, 2, (RL, ADDR), t_ldst),
- TI(ldrsb, 5600, 2, (RL, ADDR), t_lds),
- TI(ldrsh, 5e00, 2, (RL, ADDR), t_lds),
- TI(ldsb, 5600, 2, (RL, ADDR), t_lds),
- TI(ldsh, 5e00, 2, (RL, ADDR), t_lds),
+ TI(b, e7fe, 1, (EXP), t_branch12),
+ TI(beq, d0fe, 1, (EXP), t_branch9),
+ TI(bne, d1fe, 1, (EXP), t_branch9),
+ TI(bcs, d2fe, 1, (EXP), t_branch9),
+ TI(bhs, d2fe, 1, (EXP), t_branch9),
+ TI(bcc, d3fe, 1, (EXP), t_branch9),
+ TI(bul, d3fe, 1, (EXP), t_branch9),
+ TI(blo, d3fe, 1, (EXP), t_branch9),
+ TI(bmi, d4fe, 1, (EXP), t_branch9),
+ TI(bpl, d5fe, 1, (EXP), t_branch9),
+ TI(bvs, d6fe, 1, (EXP), t_branch9),
+ TI(bvc, d7fe, 1, (EXP), t_branch9),
+ TI(bhi, d8fe, 1, (EXP), t_branch9),
+ TI(bls, d9fe, 1, (EXP), t_branch9),
+ TI(bge, dafe, 1, (EXP), t_branch9),
+ TI(blt, dbfe, 1, (EXP), t_branch9),
+ TI(bgt, dcfe, 1, (EXP), t_branch9),
+ TI(ble, ddfe, 1, (EXP), t_branch9),
+ TI(bal, defe, 1, (EXP), t_branch9),
+ TI(bic, 4380, 3, (RL, RL, oRL), t_arit),
+ TI(bl, f7fffffe, 1, (EXP), t_branch23),
+ TI(bx, 4700, 1, (RR), t_bx),
+ TI(cmn, 42c0, 3, (RL, RL, oRL), t_arit),
+ TI(cmp, 4280, 2, (RR, RR_EXi), t_mov_cmp),
+ TI(eor, 4040, 3, (RL, RL, oRL), t_arit),
+ TI(ldmia, c800, 2, (RLw, REGLST), t_ldmstm),
+ TI(ldr, 5800, 2, (RL, ADDR), t_ldst),
+ TI(ldrb, 5c00, 2, (RL, ADDR), t_ldst),
+ TI(ldrh, 5a00, 2, (RL, ADDR), t_ldst),
+ TI(ldrsb, 5600, 2, (RL, ADDR), t_lds),
+ TI(ldrsh, 5e00, 2, (RL, ADDR), t_lds),
+ TI(ldsb, 5600, 2, (RL, ADDR), t_lds),
+ TI(ldsh, 5e00, 2, (RL, ADDR), t_lds),
TI(lsl, 4080, 3, (RL, RL_EXi, oRL_EXi), t_shift),
TI(lsr, 40c0, 3, (RL, RL_EXi, oRL_EXi), t_shift),
- TI(mov, 4600, 2, (RR, RR_EXi), t_mov_cmp),
- TI(mul, 4340, 3, (RL, RL, oRL), t_arit),
- TI(mvn, 43c0, 3, (RL, RL, oRL), t_arit),
- TI(neg, 4240, 3, (RL, RL, oRL), t_arit),
- TI(orr, 4300, 3, (RL, RL, oRL), t_arit),
- TI(pop, bc00, 1, (REGLST), t_push_pop),
- TI(push, b400, 1, (REGLST), t_push_pop),
- TI(ror, 41c0, 3, (RL, RL, oRL), t_arit),
- TI(sbc, 4180, 3, (RL, RL, oRL), t_arit),
- TI(stmia, c000, 2, (RLw, REGLST), t_ldmstm),
- TI(str, 5000, 2, (RL, ADDR), t_ldst),
- TI(strb, 5400, 2, (RL, ADDR), t_ldst),
- TI(strh, 5200, 2, (RL, ADDR), t_ldst),
- TI(swi, df00, 1, (EXP), t_swi),
+ TI(mov, 4600, 2, (RR, RR_EXi), t_mov_cmp),
+ TI(mul, 4340, 3, (RL, RL, oRL), t_arit),
+ TI(mvn, 43c0, 3, (RL, RL, oRL), t_arit),
+ TI(neg, 4240, 3, (RL, RL, oRL), t_arit),
+ TI(orr, 4300, 3, (RL, RL, oRL), t_arit),
+ TI(pop, bc00, 1, (REGLST), t_push_pop),
+ TI(push, b400, 1, (REGLST), t_push_pop),
+ TI(ror, 41c0, 3, (RL, RL, oRL), t_arit),
+ TI(sbc, 4180, 3, (RL, RL, oRL), t_arit),
+ TI(stmia, c000, 2, (RLw, REGLST), t_ldmstm),
+ TI(str, 5000, 2, (RL, ADDR), t_ldst),
+ TI(strb, 5400, 2, (RL, ADDR), t_ldst),
+ TI(strh, 5200, 2, (RL, ADDR), t_ldst),
+ TI(swi, df00, 1, (EXP), t_swi),
TI(sub, 8000, 3, (RR, RR_EXi, oRR_EXi), t_add_sub),
- TI(tst, 4200, 3, (RL, RL, oRL), t_arit),
+ TI(tst, 4200, 3, (RL, RL, oRL), t_arit),
/* Pseudo ops: */
- TI(adr, 000f, 2, (RL, EXP), t_adr),
- TI(nop, 46c0, 0, (), empty), /* mov r8,r8 */
+ TI(adr, 000f, 2, (RL, EXP), t_adr),
+ TI(nop, 46c0, 0, (), empty), /* mov r8,r8 */
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V5T /* Thumb v2 (ARMv5T). */
- TI(blx, 4780, 1, (RR_EX), t_blx),
- TI(bkpt, be00, 1, (oI255b), t_bkpt),
+ TI(blx, 4780, 1, (RR_EX), t_blx),
+ TI(bkpt, be00, 1, (oI255b), t_bkpt),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6
- TI(cpsie, b660, 1, (CPSF), t_cps),
- TI(cpsid, b670, 1, (CPSF), t_cps),
- TI(cpy, 4600, 2, (RR, RR), t_cpy),
- TI(rev, ba00, 3, (RL, RL, oRL), t_arit),
- TI(rev16, ba40, 3, (RL, RL, oRL), t_arit),
- TI(revsh, bac0, 3, (RL, RL, oRL), t_arit),
- TI(setend, b650, 1, (ENDI), t_setend),
- TI(sxth, b200, 3, (RL, RL, oRL), t_arit),
- TI(sxtb, b240, 3, (RL, RL, oRL), t_arit),
- TI(uxth, b280, 3, (RL, RL, oRL), t_arit),
- TI(uxtb, b2c0, 3, (RL, RL, oRL), t_arit),
+ TI(cpsie, b660, 1, (CPSF), t_cps),
+ TI(cpsid, b670, 1, (CPSF), t_cps),
+ TI(cpy, 4600, 2, (RR, RR), t_cpy),
+ TI(rev, ba00, 3, (RL, RL, oRL), t_arit),
+ TI(rev16, ba40, 3, (RL, RL, oRL), t_arit),
+ TI(revsh, bac0, 3, (RL, RL, oRL), t_arit),
+ TI(setend, b650, 1, (ENDI), t_setend),
+ TI(sxth, b200, 3, (RL, RL, oRL), t_arit),
+ TI(sxtb, b240, 3, (RL, RL, oRL), t_arit),
+ TI(uxth, b280, 3, (RL, RL, oRL), t_arit),
+ TI(uxtb, b2c0, 3, (RL, RL, oRL), t_arit),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6K
- TI(sev, bf40, 0, (), empty),
- TI(wfe, bf20, 0, (), empty),
- TI(wfi, bf30, 0, (), empty),
- TI(yield, bf10, 0, (), empty),
+ TI(sev, bf40, 0, (), empty),
+ TI(wfe, bf20, 0, (), empty),
+ TI(wfi, bf30, 0, (), empty),
+ TI(yield, bf10, 0, (), empty),
};
#undef THUMB_VARIANT
#undef TI
@@ -8002,7 +7989,7 @@
This knows about the endian-ness of the target machine and does
THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
2 (short) and 4 (long) Floating numbers are put out as a series of
- LITTLENUMS (shorts, here at least). */
+ LITTLENUMS (shorts, here at least). */
void
md_number_to_chars (char * buf, valueT val, int n)
@@ -8049,21 +8036,21 @@
return 1;
}
-/* Round up a section size to the appropriate boundary. */
+/* Round up a section size to the appropriate boundary. */
valueT
-md_section_align (segT segment ATTRIBUTE_UNUSED,
+md_section_align (segT segment ATTRIBUTE_UNUSED,
valueT size)
{
#ifdef OBJ_ELF
return size;
#else
- /* Round all sects to multiple of 4. */
+ /* Round all sects to multiple of 4. */
return (size + 3) & ~3;
#endif
}
-/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
+/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
of an rs_align_code fragment. */
void
@@ -8165,7 +8152,7 @@
{
flagword flags;
- /* Link an unlinked unwind index table section to the .text section. */
+ /* Link an unlinked unwind index table section to the .text section. */
if (elf_section_type (now_seg) == SHT_ARM_EXIDX
&& elf_linked_to_section (now_seg) == NULL)
elf_linked_to_section (now_seg) = text_section;
@@ -8192,7 +8179,7 @@
}
-/* Code to deal with unwinding tables. */
+/* Code to deal with unwinding tables. */
static void add_unwind_adjustsp (offsetT);
@@ -8216,7 +8203,7 @@
static void
add_unwind_opcode (valueT op, int length)
{
- /* Add any deferred stack adjustment. */
+ /* Add any deferred stack adjustment. */
if (unwind.pending_offset)
flush_pending_unwind ();
@@ -8261,7 +8248,7 @@
if (o == 0)
add_unwind_opcode (0, 1);
- /* Calculate the uleb128 encoding of the offset. */
+ /* Calculate the uleb128 encoding of the offset. */
n = 0;
while (o)
{
@@ -8271,7 +8258,7 @@
bytes[n] |= 0x80;
n++;
}
- /* Add the insn. */
+ /* Add the insn. */
for (; n; n--)
add_unwind_opcode (bytes[n - 1], 1);
add_unwind_opcode (0xb2, 1);
@@ -8285,7 +8272,7 @@
}
else if (offset > 0)
{
- /* Short opcode. */
+ /* Short opcode. */
op = (offset - 4) >> 2;
add_unwind_opcode (op, 1);
}
@@ -8302,7 +8289,7 @@
}
}
-/* Finish the list of unwind opcodes for this function. */
+/* Finish the list of unwind opcodes for this function. */
static void
finish_unwind_opcodes (void)
{
@@ -8382,12 +8369,12 @@
{
group_name = elf_group_name (text_seg);
if (group_name == NULL)
- {
- as_bad ("Group section `%s' has no group signature",
- segment_name (text_seg));
- ignore_rest_of_line ();
- return;
- }
+ {
+ as_bad ("Group section `%s' has no group signature",
+ segment_name (text_seg));
+ ignore_rest_of_line ();
+ return;
+ }
flags |= SHF_GROUP;
linkonce = 1;
}
@@ -8400,7 +8387,7 @@
}
-/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
+/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
personality routine data. Returns zero, or the index table value for
and inline entry. */
@@ -8410,14 +8397,14 @@
int size;
addressT where;
char *ptr;
- /* The current word of data. */
+ /* The current word of data. */
valueT data;
/* The number of bytes left in this word. */
int n;
finish_unwind_opcodes ();
- /* Remember the current text section. */
+ /* Remember the current text section. */
unwind.saved_seg = now_seg;
unwind.saved_subseg = now_subseg;
@@ -8468,11 +8455,11 @@
size = 0;
}
else
- /* We get two opcodes "free" in the first word. */
+ /* We get two opcodes "free" in the first word. */
size = unwind.opcode_count - 2;
}
else
- /* An extra byte is required for the opcode count. */
+ /* An extra byte is required for the opcode count. */
size = unwind.opcode_count + 1;
size = (size + 3) >> 2;
@@ -8483,7 +8470,7 @@
record_alignment (now_seg, 2);
unwind.table_entry = expr_build_dot ();
- /* Allocate the table entry. */
+ /* Allocate the table entry. */
ptr = frag_more ((size << 2) + 4);
where = frag_now_fix () - ((size << 2) + 4);
@@ -8495,9 +8482,9 @@
fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
BFD_RELOC_ARM_PREL31);
- /* Indicate dependency to linker. */
- {
- char *name = "__aeabi_unwind_cpp_pr0";
+ /* Indicate dependency to linker. */
+ {
+ char *name = "__aeabi_unwind_cpp_pr0";
symbolS *pr = symbol_find_or_make (name);
fix_new (frag_now, where, 4, pr, 0, 1, BFD_RELOC_NONE);
}
@@ -8505,7 +8492,7 @@
where += 4;
ptr += 4;
- /* Set the first byte to the number of additional words. */
+ /* Set the first byte to the number of additional words. */
data = size - 1;
n = 3;
break;
@@ -8528,7 +8515,7 @@
{
/* Indicate dependency to linker. */
char *name[] = { "__aeabi_unwind_cpp_pr0",
- "__aeabi_unwind_cpp_pr1",
+ "__aeabi_unwind_cpp_pr1",
"__aeabi_unwind_cpp_pr2" };
symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
fix_new (frag_now, where, 4, pr, 0, 1, BFD_RELOC_NONE);
@@ -8556,7 +8543,7 @@
data = (data << 8) | unwind.opcodes[unwind.opcode_count];
}
- /* Finish off the last word. */
+ /* Finish off the last word. */
if (n < 4)
{
/* Pad with "finish" opcodes. */
@@ -8602,7 +8589,7 @@
/* MD interface: Symbol and relocation handling. */
/* The knowledge of the PC's pipeline offset is built into the insns
- themselves. */
+ themselves. */
long
md_pcrel_from (fixS * fixP)
@@ -8622,7 +8609,7 @@
#ifdef TE_WINCE
/* The pattern was adjusted to accommodate CE's off-by-one fixups,
- so we un-adjust here to compensate for the accommodation. */
+ so we un-adjust here to compensate for the accommodation. */
return fixP->fx_where + fixP->fx_frag->fr_address + 8;
#else
return fixP->fx_where + fixP->fx_frag->fr_address;
@@ -8655,10 +8642,10 @@
return 0;
}
-/* Subroutine of md_apply_fix3. Check to see if an immediate can be
+/* Subroutine of md_apply_fix3. Check to see if an immediate can be
computed as two separate immediate values, added together. We
already know that this value cannot be computed by just one ARM
- instruction. */
+ instruction. */
static unsigned int
validate_immediate_twopart (unsigned int val,
@@ -8702,20 +8689,20 @@
return val;
}
-/* Subroutine of md_apply_fix3. Do those data_ops which can take a
+/* Subroutine of md_apply_fix3. Do those data_ops which can take a
negative immediate constant by altering the instruction. A bit of
a hack really.
- MOV <-> MVN
- AND <-> BIC
- ADC <-> SBC
- by inverting the second operand, and
- ADD <-> SUB
- CMP <-> CMN
- by negating the second operand. */
+ MOV <-> MVN
+ AND <-> BIC
+ ADC <-> SBC
+ by inverting the second operand, and
+ ADD <-> SUB
+ CMP <-> CMN
+ by negating the second operand. */
static int
negate_data_op (unsigned long * instruction,
- unsigned long value)
+ unsigned long value)
{
int op, new_inst;
unsigned long negated, inverted;
@@ -8726,8 +8713,8 @@
op = (*instruction >> DATA_OP_SHIFT) & 0xf;
switch (op)
{
- /* First negates. */
- case OPCODE_SUB: /* ADD <-> SUB */
+ /* First negates. */
+ case OPCODE_SUB: /* ADD <-> SUB */
new_inst = OPCODE_ADD;
value = negated;
break;
@@ -8737,7 +8724,7 @@
value = negated;
break;
- case OPCODE_CMP: /* CMP <-> CMN */
+ case OPCODE_CMP: /* CMP <-> CMN */
new_inst = OPCODE_CMN;
value = negated;
break;
@@ -8748,7 +8735,7 @@
break;
/* Now Inverted ops. */
- case OPCODE_MOV: /* MOV <-> MVN */
+ case OPCODE_MOV: /* MOV <-> MVN */
new_inst = OPCODE_MVN;
value = inverted;
break;
@@ -8758,7 +8745,7 @@
value = inverted;
break;
- case OPCODE_AND: /* AND <-> BIC */
+ case OPCODE_AND: /* AND <-> BIC */
new_inst = OPCODE_BIC;
value = inverted;
break;
@@ -8768,7 +8755,7 @@
value = inverted;
break;
- case OPCODE_ADC: /* ADC <-> SBC */
+ case OPCODE_ADC: /* ADC <-> SBC */
new_inst = OPCODE_SBC;
value = inverted;
break;
@@ -8778,7 +8765,7 @@
value = inverted;
break;
- /* We cannot do anything. */
+ /* We cannot do anything. */
default:
return FAIL;
}
@@ -8792,18 +8779,18 @@
}
void
-md_apply_fix3 (fixS * fixP,
+md_apply_fix3 (fixS * fixP,
valueT * valP,
- segT seg)
+ segT seg)
{
- offsetT value = * valP;
- offsetT newval;
- unsigned int newimm;
- unsigned long temp;
- int sign;
- char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+ offsetT value = * valP;
+ offsetT newval;
+ unsigned int newimm;
+ unsigned long temp;
+ int sign;
+ char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
/* The double cast here prevents warnings about converting a pointer
- to an integer of different size. We know the value is 0, 1, or 2. */
+ to an integer of different size. We know the value is 0, 1, or 2. */
int fix_is_thumb = (int) (size_t) fixP->tc_fix_data;
assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
@@ -8875,16 +8862,16 @@
temp = md_chars_to_number (buf, INSN_SIZE);
/* If the instruction will fail, see if we can fix things up by
- changing the opcode. */
+ changing the opcode. */
if (newimm == (unsigned int) FAIL
&& (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
{
/* No ? OK - try using two ADD instructions to generate
- the value. */
+ the value. */
newimm = validate_immediate_twopart (value, & highpart);
/* Yes - then make sure that the second instruction is
- also an add. */
+ also an add. */
if (newimm != (unsigned int) FAIL)
newinsn = temp;
/* Still No ? Try using a negated value. */
@@ -8976,7 +8963,7 @@
}
if (value == 0)
- /* Shifts of zero must be done as lsl. */
+ /* Shifts of zero must be done as lsl. */
newval &= ~0x60;
else if (value == 32)
value = 0;
@@ -9036,14 +9023,14 @@
/* We are going to store value (shifted right by two) in the
instruction, in a 24 bit, signed field. Thus we need to check
that none of the top 8 bits of the shifted value (top 7 bits of
- the unshifted, unsigned value) are set, or that they are all set. */
+ the unshifted, unsigned value) are set, or that they are all set. */
if ((value & ~ ((offsetT) 0x1ffffff)) != 0
&& ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
{
#ifdef OBJ_ELF
/* Normally we would be stuck at this point, since we cannot store
the absolute address that is the destination of the branch in the
- 24 bits of the branch instruction. If however, we happen to know
+ 24 bits of the branch instruction. If however, we happen to know
that the destination of the branch is in the same section as the
branch instruction itself, then we can compute the relocation for
ourselves and not have to bother the linker with it.
@@ -9059,7 +9046,7 @@
/* Permit a backward branch provided that enough bits
are set. Allow a forwards branch, provided that
- enough bits are clear. */
+ enough bits are clear. */
if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
|| (value & ~ ((offsetT) 0x1ffffff)) == 0)
fixP->fx_done = 1;
@@ -9124,7 +9111,7 @@
}
break;
- case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
+ case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
newval = md_chars_to_number (buf, THUMB_SIZE);
{
addressT diff = (newval & 0xff) << 1;
@@ -9180,7 +9167,7 @@
offsetT newval2;
addressT diff;
- newval = md_chars_to_number (buf, THUMB_SIZE);
+ newval = md_chars_to_number (buf, THUMB_SIZE);
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
if (diff & 0x400000)
@@ -9314,8 +9301,8 @@
case BFD_RELOC_ARM_CP_OFF_IMM_S2:
if (value < -255 || value > 255)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("co-processor offset out of range"));
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("co-processor offset out of range"));
goto cp_off_common;
case BFD_RELOC_ARM_THUMB_OFFSET:
@@ -9371,7 +9358,7 @@
newval |= value << 6;
break;
- case 8: /* Halfword load/store. */
+ case 8: /* Halfword load/store. */
if (value & ~0x3e)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid offset, value too big (0x%08lX)"),
@@ -9390,15 +9377,15 @@
case BFD_RELOC_ARM_THUMB_ADD:
/* This is a complicated relocation, since we use it for all of
- the following immediate relocations:
+ the following immediate relocations:
3bit ADD/SUB
8bit ADD/SUB
9bit ADD/SUB SP word-aligned
10bit ADD PC/SP word-aligned
- The type of instruction being processed is encoded in the
- instruction field:
+ The type of instruction being processed is encoded in the
+ instruction field:
0x8000 SUB
0x00F0 Rd
@@ -9411,7 +9398,7 @@
int subtract = !!(newval & 0x8000);
/* Check for HI regs, only very restricted cases allowed:
- Adjusting SP, and using PC or SP to get an address. */
+ Adjusting SP, and using PC or SP to get an address. */
if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
|| (rs > 7 && rs != REG_SP && rs != REG_PC))
as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -9476,13 +9463,13 @@
break;
case BFD_RELOC_ARM_THUMB_SHIFT:
- /* 5bit shift value (0..32). LSL cannot take 32. */
+ /* 5bit shift value (0..32). LSL cannot take 32. */
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
temp = newval & 0xf800;
if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid shift value: %ld"), (long) value);
- /* Shifts of zero must be encoded as LSL. */
+ /* Shifts of zero must be encoded as LSL. */
if (value == 0)
newval = (newval & 0x003f) | T_OPCODE_LSL_I;
/* Shifts of 32 are encoded as zero. */
@@ -9509,7 +9496,7 @@
arelent *
tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
- fixS * fixp)
+ fixS * fixp)
{
arelent * reloc;
bfd_reloc_code_real_type code;
@@ -9618,18 +9605,18 @@
switch (fixp->fx_r_type)
{
- case BFD_RELOC_NONE: type = "NONE"; break;
+ case BFD_RELOC_NONE: type = "NONE"; break;
case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
- case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
- case BFD_RELOC_ARM_SMI: type = "SMI"; break;
- case BFD_RELOC_ARM_SWI: type = "SWI"; break;
- case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
- case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
- case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
+ case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
+ case BFD_RELOC_ARM_SMI: type = "SMI"; break;
+ case BFD_RELOC_ARM_SWI: type = "SWI"; break;
+ case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
+ case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
+ case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
- case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
+ case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
- default: type = _("<unknown>"); break;
+ default: type = _("<unknown>"); break;
}
as_bad_where (fixp->fx_file, fixp->fx_line,
_("cannot represent %s relocation in this object file format"),
@@ -9666,12 +9653,12 @@
return reloc;
}
-/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
+/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
void
-cons_fix_new_arm (fragS * frag,
- int where,
- int size,
+cons_fix_new_arm (fragS * frag,
+ int where,
+ int size,
expressionS * exp)
{
bfd_reloc_code_real_type type;
@@ -9706,7 +9693,7 @@
/* If the destination of the branch is a defined symbol which does not have
the THUMB_FUNC attribute, then we must be calling a function which has
the (interfacearm) attribute. We look for the Thumb entry point to that
- function and change the branch to refer to that function instead. */
+ function and change the branch to refer to that function instead. */
if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
&& fixP->fx_addsy != NULL
&& S_IS_DEFINED (fixP->fx_addsy)
@@ -9769,7 +9756,7 @@
which currently is not: Taking the address of a label (rather
than a function) and then later jumping to that address. Such
addresses also ought to have their bottom bit set (assuming that
- they reside in Thumb code), but at the moment they will not. */
+ they reside in Thumb code), but at the moment they will not. */
bfd_boolean
arm_fix_adjustable (fixS * fixP)
@@ -9782,11 +9769,11 @@
return 0;
/* We need the symbol name for the VTABLE entries. */
- if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
- /* Don't allow symbols to be discarded on GOT related relocs. */
+ /* Don't allow symbols to be discarded on GOT related relocs. */
if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
|| fixP->fx_r_type == BFD_RELOC_ARM_GOT32
|| fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
@@ -9823,7 +9810,7 @@
}
#endif
-/* MD interface: Finalization. */
+/* MD interface: Finalization. */
/* A good place to do this, although this was probably not intended
for this kind of use. We need to dump the literal pool before
@@ -9862,7 +9849,7 @@
{
/* Mark the symbol as a Thumb function. */
if ( S_GET_STORAGE_CLASS (sym) == C_STAT
- || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
+ || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
@@ -9894,7 +9881,7 @@
#endif
#ifdef OBJ_ELF
symbolS * sym;
- char bind;
+ char bind;
for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
{
@@ -9936,7 +9923,7 @@
unsigned mach;
unsigned int i;
- if ( (arm_ops_hsh = hash_new ()) == NULL
+ if ( (arm_ops_hsh = hash_new ()) == NULL
|| (arm_tops_hsh = hash_new ()) == NULL
|| (arm_cond_hsh = hash_new ()) == NULL
|| (arm_shift_hsh = hash_new ()) == NULL
@@ -10027,7 +10014,7 @@
if (uses_apcs_26) flags |= F_APCS26;
if (support_interwork) flags |= F_INTERWORK;
if (uses_apcs_float) flags |= F_APCS_FLOAT;
- if (pic_code) flags |= F_PIC;
+ if (pic_code) flags |= F_PIC;
if ((cpu_variant & FPU_ANY) == FPU_NONE
|| (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
flags |= F_SOFT_FLOAT;
@@ -10045,7 +10032,7 @@
break;
}
- /* Using VFP conventions (even if soft-float). */
+ /* Using VFP conventions (even if soft-float). */
if (cpu_variant & FPU_VFP_EXT_NONE)
flags |= F_VFP_FLOAT;
@@ -10055,7 +10042,7 @@
break;
case EF_ARM_EABI_VER4:
- /* No additional flags to set. */
+ /* No additional flags to set. */
break;
default:
@@ -10066,7 +10053,7 @@
/* We have run out flags in the COFF header to encode the
status of ATPCS support, so instead we create a dummy,
- empty, debug section called .arm.atpcs. */
+ empty, debug section called .arm.atpcs. */
if (atpcs)
{
asection * sec;
@@ -10091,11 +10078,11 @@
mach = bfd_mach_arm_2;
break;
- case ARM_3: /* Also ARM_250. */
+ case ARM_3: /* Also ARM_250. */
mach = bfd_mach_arm_2a;
break;
- case ARM_6: /* Also ARM_7. */
+ case ARM_6: /* Also ARM_7. */
mach = bfd_mach_arm_3;
break;
@@ -10167,23 +10154,23 @@
The remaining options are only supported for back-wards compatibility.
Cpu variants, the arm part is optional:
- -m[arm]1 Currently not supported.
- -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
- -m[arm]3 Arm 3 processor
- -m[arm]6[xx], Arm 6 processors
- -m[arm]7[xx][t][[d]m] Arm 7 processors
- -m[arm]8[10] Arm 8 processors
- -m[arm]9[20][tdmi] Arm 9 processors
- -mstrongarm[110[0]] StrongARM processors
- -mxscale XScale processors
- -m[arm]v[2345[t[e]]] Arm architectures
- -mall All (except the ARM1)
+ -m[arm]1 Currently not supported.
+ -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
+ -m[arm]3 Arm 3 processor
+ -m[arm]6[xx], Arm 6 processors
+ -m[arm]7[xx][t][[d]m] Arm 7 processors
+ -m[arm]8[10] Arm 8 processors
+ -m[arm]9[20][tdmi] Arm 9 processors
+ -mstrongarm[110[0]] StrongARM processors
+ -mxscale XScale processors
+ -m[arm]v[2345[t[e]]] Arm architectures
+ -mall All (except the ARM1)
FP variants:
- -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
- -mfpe-old (No float load/store multiples)
+ -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
+ -mfpe-old (No float load/store multiples)
-mvfpxd VFP Single precision
-mvfp All VFP
- -mno-fpu Disable all floating point instructions
+ -mno-fpu Disable all floating point instructions
The following CPU names are recognized:
arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
@@ -10226,15 +10213,15 @@
{
char *option; /* Option name to match. */
char *help; /* Help information. */
- int *var; /* Variable to change. */
- int value; /* What to change it to. */
+ int *var; /* Variable to change. */
+ int value; /* What to change it to. */
char *deprecated; /* If non-null, print this message. */
};
struct arm_option_table arm_opts[] =
{
- {"k", N_("generate PIC code"), &pic_code, 1, NULL},
- {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
+ {"k", N_("generate PIC code"), &pic_code, 1, NULL},
+ {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
{"mthumb-interwork", N_("support ARM/Thumb interworking"),
&support_interwork, 1, NULL},
{"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
@@ -10247,7 +10234,7 @@
{"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 1,
NULL},
- /* These are recognized by the assembler, but have no affect on code. */
+ /* These are recognized by the assembler, but have no affect on code. */
{"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
{"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
@@ -10330,7 +10317,7 @@
N_("use -mcpu=strongarm1110")},
{"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
{"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
- {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
+ {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
/* Architecture variants -- don't add any more to this list either. */
{"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
@@ -10352,7 +10339,7 @@
{"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
{"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
- /* Floating point variants -- don't add any more to this list either. */
+ /* Floating point variants -- don't add any more to this list either. */
{"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
{"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
{"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
@@ -10365,10 +10352,10 @@
struct arm_cpu_option_table
{
char *name;
- int value;
+ int value;
/* For some CPUs we assume an FPU unless the user explicitly sets
- -mfpu=... */
- int default_fpu;
+ -mfpu=... */
+ int default_fpu;
};
/* This list should, at a minimum, contain all the cpu names
@@ -10420,14 +10407,14 @@
{"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
{"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
/* For V5 or later processors we default to using VFP; but the user
- should really set the FPU type explicitly. */
+ should really set the FPU type explicitly. */
{"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
- {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
- {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
+ {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
{"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
@@ -10437,14 +10424,14 @@
{"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
{"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
{"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
- {"arm1136js", ARM_ARCH_V6, FPU_NONE},
- {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
- {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
- {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
- {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
- {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
- {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
- {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
+ {"arm1136js", ARM_ARCH_V6, FPU_NONE},
+ {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
+ {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
+ {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
+ {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
+ {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
+ {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
+ {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
/* ??? XSCALE is really an architecture. */
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
/* ??? iwmmxt is not a processor. */
@@ -10458,8 +10445,8 @@
struct arm_arch_option_table
{
char *name;
- int value;
- int default_fpu;
+ int value;
+ int default_fpu;
};
/* This list should, at a minimum, contain all the architecture names
@@ -10482,15 +10469,15 @@
{"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
{"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
{"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
- {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
- {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
- {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
- {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
- {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
- {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
- {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
- {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
- {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
+ {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
+ {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
+ {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
+ {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
+ {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
+ {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
+ {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
+ {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
+ {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
{"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
@@ -10515,7 +10502,7 @@
struct arm_fpu_option_table
{
char *name;
- int value;
+ int value;
};
/* This list should, at a minimum, contain all the fpu names
@@ -10577,7 +10564,7 @@
struct arm_long_option_table
{
- char * option; /* Substring to match. */
+ char * option; /* Substring to match. */
char * help; /* Help information. */
int (* func) (char * subopt); /* Function to decode sub-option. */
char * deprecated; /* If non-null, print this message. */
@@ -10788,7 +10775,7 @@
case 'a':
/* Listing option. Just ignore these, we don't support additional
- ones. */
+ ones. */
return 0;
default: