bfd/ChangeLog 2004-03-09 James E Wilson * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mips_apollo. * archures.c (bfd_mach_mips_apollo): Added. * bfd-in2.h: Rebuilt. * cpu-mips.c (I_apollo): Define. (arch_info_struct): Add apollo. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_APOLLO. (mips_set_isa_flags): Handle bfd_mach_mips_apollo. (mips_mach_extension): Document Apollo absence. binutils/ChangeLog 2004-03-09 James E Wilson * readelf.c (get_machine_flags): Handle E_MIPS_MACH_APOLLO. gas/ChangeLog 2004-03-09 James E Wilson * config/tc-mips.c (branch_delay_slots): New. (append_insn): Check branch_delay_slots. (macro_start): Likewise. (mips_cpu_info): Add apollo. * doc/c-mips.texi: Add apollo. gas/testsuite/ChangeLog 2004-03-09 James E Wilson * gas/mips/mips.exp: Add apollo test. * gas/mips/apollo.d: New file. * gas/mips/apollo.s: New file. include/elf/ChangeLog 2004-03-09 James E Wilson * mips.h (E_MIPS_MACH_APOLLO): New. include/opcode/ChangeLog 2004-03-09 James E Wilson * mips.h (INSN_APOLLO): New. (CPU_APOLLO): New. (OPCODE_IS_MEMBER): Handle CPU_APOLLO. opcode/ChangeLog 2004-03-09 James E Wilson * mips-dis.c (mips_arch_choices): Add apollo. * mips-opc.c (AP): New. (mips_builtin_opcodes): Add Apollo support. Index: bfd/aoutx.h =================================================================== RCS file: /cvs/src/src/bfd/aoutx.h,v retrieving revision 1.45 diff -p -r1.45 aoutx.h *** bfd/aoutx.h 24 Nov 2003 18:06:39 -0000 1.45 --- bfd/aoutx.h 10 Mar 2004 07:31:12 -0000 *************** NAME(aout,machine_type) (arch, machine, *** 803,808 **** --- 803,809 ---- case bfd_mach_mipsisa64: case bfd_mach_mipsisa64r2: case bfd_mach_mips_sb1: + case bfd_mach_mips_apollo: /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ arch_flags = M_MIPS2; break; Index: bfd/archures.c =================================================================== RCS file: /cvs/src/src/bfd/archures.c,v retrieving revision 1.88 diff -p -r1.88 archures.c *** bfd/archures.c 3 Dec 2003 17:38:48 -0000 1.88 --- bfd/archures.c 10 Mar 2004 07:31:13 -0000 *************** DESCRIPTION *** 150,155 **** --- 150,156 ---- .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa64 64 .#define bfd_mach_mipsisa64r2 65 + .#define bfd_mach_mips_apollo 101160157 {* octal 'Apo' *} . bfd_arch_i386, {* Intel 386 *} .#define bfd_mach_i386_i386 1 .#define bfd_mach_i386_i8086 2 Index: bfd/bfd-in2.h =================================================================== RCS file: /cvs/src/src/bfd/bfd-in2.h,v retrieving revision 1.257 diff -p -r1.257 bfd-in2.h *** bfd/bfd-in2.h 16 Feb 2004 18:46:40 -0000 1.257 --- bfd/bfd-in2.h 10 Mar 2004 07:31:17 -0000 *************** enum bfd_architecture *** 1582,1587 **** --- 1582,1588 ---- #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa64 64 #define bfd_mach_mipsisa64r2 65 + #define bfd_mach_mips_apollo 101160157 /* octal 'Apo' */ bfd_arch_i386, /* Intel 386 */ #define bfd_mach_i386_i386 1 #define bfd_mach_i386_i8086 2 Index: bfd/cpu-mips.c =================================================================== RCS file: /cvs/src/src/bfd/cpu-mips.c,v retrieving revision 1.21 diff -p -r1.21 cpu-mips.c *** bfd/cpu-mips.c 8 Dec 2003 20:04:34 -0000 1.21 --- bfd/cpu-mips.c 10 Mar 2004 07:31:18 -0000 *************** enum *** 85,90 **** --- 85,91 ---- I_mipsisa64, I_mipsisa64r2, I_sb1, + I_apollo, }; #define NN(index) (&arch_info_struct[(index) + 1]) *************** static const bfd_arch_info_type arch_inf *** 116,122 **** N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), ! N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0), }; /* The default architecture is mips:3000, but with a machine number of --- 117,124 ---- N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), ! N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), ! N (32, 32, bfd_mach_mips_apollo, "mips:apollo", FALSE, 0), }; /* The default architecture is mips:3000, but with a machine number of Index: bfd/elfxx-mips.c =================================================================== RCS file: /cvs/src/src/bfd/elfxx-mips.c,v retrieving revision 1.90 diff -p -r1.90 elfxx-mips.c *** bfd/elfxx-mips.c 17 Feb 2004 10:19:23 -0000 1.90 --- bfd/elfxx-mips.c 10 Mar 2004 07:31:28 -0000 *************** _bfd_elf_mips_mach (flagword flags) *** 4103,4108 **** --- 4103,4111 ---- case E_MIPS_MACH_SB1: return bfd_mach_mips_sb1; + case E_MIPS_MACH_APOLLO: + return bfd_mach_mips_apollo; + default: switch (flags & EF_MIPS_ARCH) { *************** mips_set_isa_flags (bfd *abfd) *** 7185,7190 **** --- 7188,7197 ---- case bfd_mach_mipsisa64r2: val = E_MIPS_ARCH_64R2; break; + + case bfd_mach_mips_apollo: + val = E_MIPS_ARCH_2 | E_MIPS_MACH_APOLLO; + break; } elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH); elf_elfheader (abfd)->e_flags |= val; *************** static const struct mips_mach_extension *** 8915,8920 **** --- 8922,8930 ---- /* MIPS I extensions. */ { bfd_mach_mips6000, bfd_mach_mips3000 }, { bfd_mach_mips3900, bfd_mach_mips3000 } + + /* Apollo is deliberately not in this list, as the lack of delay slots + means it isn't compatible with anything else. */ }; Index: binutils/readelf.c =================================================================== RCS file: /cvs/src/src/binutils/readelf.c,v retrieving revision 1.230 diff -p -r1.230 readelf.c *** binutils/readelf.c 29 Jan 2004 00:27:30 -0000 1.230 --- binutils/readelf.c 10 Mar 2004 07:31:37 -0000 *************** get_machine_flags (unsigned e_flags, uns *** 1895,1900 **** --- 1895,1901 ---- case E_MIPS_MACH_5400: strcat (buf, ", 5400"); break; case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break; case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break; + case E_MIPS_MACH_APOLLO: strcat (buf, ", apollo"); break; case 0: /* We simply ignore the field in this case to avoid confusion: MIPS ELF does not specify EF_MIPS_MACH, it is a GNU Index: gas/config/tc-mips.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-mips.c,v retrieving revision 1.253 diff -p -r1.253 tc-mips.c *** gas/config/tc-mips.c 2 Feb 2004 12:48:19 -0000 1.253 --- gas/config/tc-mips.c 10 Mar 2004 07:31:52 -0000 *************** static int mips_32bitmode = 0; *** 386,391 **** --- 386,396 ---- requires at MIPS ISA level I. */ #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) + /* Does the target have branch delay slots? */ + /* ??? We still add nops when relaxing branches, but this is harmless, and + presumably rare. */ + #define branch_delay_slots (mips_opts.arch != CPU_APOLLO) + /* Is this a mfhi or mflo instruction? */ #define MF_HILO_INSN(PINFO) \ ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) *************** append_insn (struct mips_cl_insn *ip, ex *** 2323,2330 **** do if the previous instruction does not set up a condition that the branch tests and if the branch is not itself the target of any branch. */ ! if ((pinfo & INSN_UNCOND_BRANCH_DELAY) ! || (pinfo & INSN_COND_BRANCH_DELAY)) { if (mips_optimize < 2 /* If we have seen .set volatile or .set nomove, don't --- 2328,2336 ---- do if the previous instruction does not set up a condition that the branch tests and if the branch is not itself the target of any branch. */ ! if (((pinfo & INSN_UNCOND_BRANCH_DELAY) ! || (pinfo & INSN_COND_BRANCH_DELAY)) ! && branch_delay_slots) { if (mips_optimize < 2 /* If we have seen .set volatile or .set nomove, don't *************** append_insn (struct mips_cl_insn *ip, ex *** 2691,2697 **** prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; prev_insn_extended = 0; } ! else if (pinfo & INSN_COND_BRANCH_LIKELY) { /* We don't yet optimize a branch likely. What we should do is look at the target, copy the instruction found there --- 2697,2704 ---- prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; prev_insn_extended = 0; } ! else if ((pinfo & INSN_COND_BRANCH_LIKELY) ! && branch_delay_slots) { /* We don't yet optimize a branch likely. What we should do is look at the target, copy the instruction found there *************** macro_start (void) *** 2910,2915 **** --- 2917,2923 ---- { memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); mips_macro_warning.delay_slot_p = (mips_opts.noreorder + && branch_delay_slots && (prev_insn.insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY *************** static const struct mips_cpu_info mips_c *** 14164,14169 **** --- 14172,14180 ---- /* Broadcom SB-1 CPU core */ { "sb1", 0, ISA_MIPS64, CPU_SB1 }, + + /* Juniper Apollo core */ + { "apollo", 0, ISA_MIPS2, CPU_APOLLO }, /* End marker */ { NULL, 0, 0, 0 } Index: gas/doc/c-mips.texi =================================================================== RCS file: /cvs/src/src/gas/doc/c-mips.texi,v retrieving revision 1.30 diff -p -r1.30 c-mips.texi *** gas/doc/c-mips.texi 9 Jan 2004 02:34:04 -0000 1.30 --- gas/doc/c-mips.texi 10 Mar 2004 07:31:53 -0000 *************** rm9000, *** 187,192 **** --- 187,193 ---- 12000, mips32-4k, sb1 + apollo @end quotation @item -mtune=@var{cpu} Index: gas/testsuite/gas/mips/mips.exp =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v retrieving revision 1.87 diff -p -r1.87 mips.exp *** gas/testsuite/gas/mips/mips.exp 23 Jan 2004 13:01:07 -0000 1.87 --- gas/testsuite/gas/mips/mips.exp 10 Mar 2004 07:31:55 -0000 *************** if { [istarget mips*-*-*] } then { *** 560,565 **** --- 560,566 ---- run_dump_test "vr5400" run_dump_test "vr5500" run_dump_test "rm7000" + run_dump_test "apollo" run_dump_test "perfcount" run_dump_test "lineno" run_dump_test "sync" Index: include/elf/mips.h =================================================================== RCS file: /cvs/src/src/include/elf/mips.h,v retrieving revision 1.21 diff -p -r1.21 mips.h *** include/elf/mips.h 30 Sep 2003 16:17:14 -0000 1.21 --- include/elf/mips.h 10 Mar 2004 07:31:58 -0000 *************** END_RELOC_NUMBERS (R_MIPS_maxext) *** 189,194 **** --- 189,195 ---- #define E_MIPS_MACH_SB1 0x008a0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5500 0x00980000 + #define E_MIPS_MACH_APOLLO 0x00990000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these Index: include/opcode/mips.h =================================================================== RCS file: /cvs/src/src/include/opcode/mips.h,v retrieving revision 1.38 diff -p -r1.38 mips.h *** include/opcode/mips.h 18 Nov 2003 21:22:56 -0000 1.38 --- include/opcode/mips.h 10 Mar 2004 07:32:00 -0000 *************** struct mips_opcode *** 433,438 **** --- 433,440 ---- #define INSN_5400 0x01000000 /* NEC VR5500 instruction. */ #define INSN_5500 0x02000000 + /* Juniper Apollo instruction. */ + #define INSN_APOLLO 0x04000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ *************** struct mips_opcode *** 479,484 **** --- 481,487 ---- #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ + #define CPU_APOLLO 101160157 /* octal 'Apo'. */ /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified *************** struct mips_opcode *** 499,504 **** --- 502,508 ---- || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || (cpu == CPU_APOLLO && ((insn)->membership & INSN_APOLLO) != 0) \ || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. Index: opcodes/mips-dis.c =================================================================== RCS file: /cvs/src/src/opcodes/mips-dis.c,v retrieving revision 1.46 diff -p -r1.46 mips-dis.c *** opcodes/mips-dis.c 30 Sep 2003 16:17:15 -0000 1.46 --- opcodes/mips-dis.c 10 Mar 2004 07:32:04 -0000 *************** const struct mips_arch_choice mips_arch_ *** 396,401 **** --- 396,405 ---- mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), mips_hwr_names_numeric }, + {"apollo", 1, bfd_mach_mips_apollo, CPU_APOLLO, + ISA_MIPS2 | INSN_APOLLO, + mips_cp0_names_numeric, NULL, 9, mips_hwr_names_numeric }, + /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, Index: opcodes/mips-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/mips-opc.c,v retrieving revision 1.45 diff -p -r1.45 mips-opc.c *** opcodes/mips-opc.c 18 Nov 2003 21:22:57 -0000 1.45 --- opcodes/mips-opc.c 10 Mar 2004 07:32:07 -0000 *************** Software Foundation, 59 Temple Place - S *** 109,114 **** --- 109,115 ---- #define N5 (INSN_5400 | INSN_5500) #define N54 INSN_5400 #define N55 INSN_5500 + #define AP INSN_APOLLO #define G1 (T3 \ ) *************** const struct mips_opcode mips_builtin_op *** 138,144 **** them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, membership */ ! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 }, {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */ {"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */ --- 139,145 ---- them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, membership */ ! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3|AP }, {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */ {"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */ *************** const struct mips_opcode mips_builtin_op *** 153,158 **** --- 154,161 ---- {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ + {"shrel", "t,o(b)", 0xf4000000, 0xfc000000, SM|RD_t|RD_b, AP }, /* sdc1 */ + {"swrel", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, AP }, /* sd */ {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, *************** const struct mips_opcode mips_builtin_op *** 436,442 **** {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, ! {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3}, {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, --- 439,445 ---- {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, ! {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3|AP}, {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, *************** const struct mips_opcode mips_builtin_op *** 476,481 **** --- 479,487 ---- {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, {"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 }, + {"dbrr", "s,d", 0x0000000e, 0xfc1f07ff, WR_d|RD_s, AP }, + {"dbrw", "s,t", 0x0000000a, 0xfc00ffff, RD_s|RD_t, AP }, + {"dbrwa", "s,t", 0x0000000b, 0xfc00ffff, RD_s|RD_t, AP }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, /* dctr and dctw are used on the r5000. */ *************** const struct mips_opcode mips_builtin_op *** 601,607 **** {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 }, {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 }, ! {"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 }, {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 }, {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, --- 607,613 ---- {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 }, {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 }, ! {"eret", "", 0x42000018, 0xffffffff, 0, I3|I32|AP }, {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 }, {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, *************** const struct mips_opcode mips_builtin_op *** 611,616 **** --- 617,623 ---- {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, {"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, + {"halt", "", 0x4200001b, 0xffffffff, 0, AP }, {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, I33 }, {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, I33 }, *************** const struct mips_opcode mips_builtin_op *** 970,975 **** --- 977,983 ---- {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, + {"sbrel", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|RD_b, AP }, {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, *************** const struct mips_opcode mips_builtin_op *** 1028,1033 **** --- 1036,1042 ---- {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, + {"sipi", "s,t", 0x00000015, 0xfc00ffff, RD_s|RD_t, AP }, {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, *************** const struct mips_opcode mips_builtin_op *** 1089,1094 **** --- 1098,1104 ---- {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, + {"swcr", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, AP }, {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, New file gas/testsuite/gas/mips/apollo.d: #objdump: -dr #name: Apollo #as: -march=apollo .*: +file format .*mips.* Disassembly of section \.text: 0+000 <\.text>: + 0: cc800040 pref 0x0,64\(a0\) + 4: cc810000 pref 0x1,0\(a0\) + 8: bca00040 cache 0x0,64\(a1\) + c: bca10000 cache 0x1,0\(a1\) +10: fe900000 swrel s0,0\(s4\) +14: f6b10020 shrel s1,32\(s5\) +18: f2d20040 sbrel s2,64\(s6\) +1c: 7ef30080 swcr s3,128\(s7\) +20: 00850015 sipi a0,a1 +24: 00c0380e dbrr a2,a3 +28: 0109000a dbrw t0,t1 +2c: 014b000b dbrwa t2,t3 +30: 4200001b halt New file gas/testsuite/gas/mips/apollo.s: pref 0,64($4) pref 1,0($4) cache 0,64($5) cache 1,0($5) swrel $16,0($20) shrel $17,32($21) sbrel $18,64($22) swcr $19,128($23) sipi $4,$5 dbrr $6,$7 dbrw $8,$9 dbrwa $10,$11 halt