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Macro name and comment fixes for gas/tc-mips.c
- From: Ian Lance Taylor <ian at wasabisystems dot com>
- To: binutils at sources dot redhat dot com
- Date: 7 Jan 2004 16:46:45 -0500
- Subject: Macro name and comment fixes for gas/tc-mips.c
I spent some time being confused by the macro ISA_HAS_COPROC_DELAYS
because I thought it meant something like ``this ISA requires delays
for co-processor instructions.'' In fact, as the comment explains, it
means something rather different, namely that the ISA requires delays
in a variety of different situations.
I propose that we rename the macro to ISA_HAS_NONBRANCH_DELAYS to
avoid such confusion. This patch does that rename, and also fixes the
comment for this macro and for the gpr_interlocks macro.
Any objections to this patch?
Ian
2004-01-07 Ian Lance Taylor <ian@wasabisystems.com>
* config/tc-mips.c (ISA_HAS_NONBRANCH_DELAYS): Rename from
ISA_HAS_COPROC_DELAYS. Change all uses.
Index: config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.242
diff -p -u -r1.242 tc-mips.c
--- config/tc-mips.c 18 Dec 2003 10:23:09 -0000 1.242
+++ config/tc-mips.c 7 Jan 2004 21:46:28 -0000
@@ -1,6 +1,6 @@
/* tc-mips.c -- assemble code for a MIPS chip.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- Free Software Foundation, Inc.
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004 Free Software Foundation, Inc.
Contributed by the OSF and Ralph Campbell.
Written by Keith Knowles and Ralph Campbell, working independently.
Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
@@ -237,15 +237,15 @@ static const char *mips_tune_string;
/* True when generating 32-bit code for a 64-bit processor. */
static int mips_32bitmode = 0;
-/* Some ISA's have delay slots for instructions which read or write
- from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
- Return true if instructions marked INSN_LOAD_COPROC_DELAY,
- INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
- delay slot in this ISA. The uses of this macro assume that any
- ISA that has delay slots for one of these, has them for all. They
- also assume that ISAs which don't have delays for these insns, don't
- have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
-#define ISA_HAS_COPROC_DELAYS(ISA) ( \
+/* The earlier MIPS ISAs have delay slots for various cases. This
+ macro returns true if at least some of the instructions marked
+ INSN_LOAD_MEMORY_DELAY, INSN_LOAD_COPROC_DELAY,
+ INSN_COPROC_MOVE_DELAY, INSN_COPROC_MEMORY_DELAY, or
+ INSN_WRITE_COND_CODE require a delay before the value may be used.
+ It returns false if none of these instruction types require a
+ delay. Note that this does not affect delays required between
+ reading and writing the HI and LO registers. */
+#define ISA_HAS_NONBRANCH_DELAYS(ISA) ( \
(ISA) == ISA_MIPS1 \
|| (ISA) == ISA_MIPS2 \
|| (ISA) == ISA_MIPS3 \
@@ -350,7 +350,10 @@ static int mips_32bitmode = 0;
)
/* Whether the processor uses hardware interlocks to protect reads
- from the GPRs, and thus does not require nops to be inserted. */
+ from the GPRs after they are loaded from memory, and thus does not
+ require nops to be inserted. This applies to instructions marked
+ INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
+ level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
|| mips_opts.arch == CPU_VR5400 \
@@ -1479,7 +1482,7 @@ reg_needs_delay (unsigned int reg)
prev_pinfo = prev_insn.insn_mo->pinfo;
if (! mips_opts.noreorder
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
@@ -1580,7 +1583,7 @@ append_insn (char *place, struct mips_cl
/* The previous insn might require a delay slot, depending upon
the contents of the current insn. */
if (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
&& ! cop_interlocks)
|| (! gpr_interlocks
@@ -1600,7 +1603,7 @@ append_insn (char *place, struct mips_cl
++nops;
}
else if (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
|| (mips_opts.isa == ISA_MIPS1
@@ -1659,7 +1662,7 @@ append_insn (char *place, struct mips_cl
}
}
else if (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (prev_pinfo & INSN_WRITE_COND_CODE)
&& ! cop_interlocks)
{
@@ -1766,7 +1769,7 @@ append_insn (char *place, struct mips_cl
instruction, we must check for these cases compared to the
instruction previous to the previous instruction. */
if ((! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
&& (pinfo & INSN_READ_COND_CODE)
@@ -2285,13 +2288,13 @@ append_insn (char *place, struct mips_cl
we can not swap, and I don't feel like handling that
case. */
|| (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (pinfo & INSN_READ_COND_CODE))
/* We can not swap with an instruction that requires a
delay slot, because the target of the branch might
interfere with that instruction. */
|| (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (prev_pinfo
/* Itbl support may require additional care here. */
& (INSN_LOAD_COPROC_DELAY
@@ -2411,7 +2414,7 @@ append_insn (char *place, struct mips_cl
delay, and sets a register that the branch reads, we
can not swap. */
|| (! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
/* Itbl support may require additional care here. */
&& ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
@@ -2684,7 +2687,7 @@ mips_emit_delays (bfd_boolean insns)
nops = 0;
if ((! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& (prev_insn.insn_mo->pinfo
& (INSN_LOAD_COPROC_DELAY
@@ -2706,7 +2709,7 @@ mips_emit_delays (bfd_boolean insns)
/* Itbl support may require additional care here. */
++nops;
if ((! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
@@ -2718,7 +2721,7 @@ mips_emit_delays (bfd_boolean insns)
nops = 0;
}
else if ((! mips_opts.mips16
- && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
+ && ISA_HAS_NONBRANCH_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks