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Add Toshiba TX49 support
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: binutils at sources dot redhat dot com
- Date: Mon, 11 Nov 2002 21:21:44 +0000
- Subject: Add Toshiba TX49 support
Hi
the attached patch adds support for the toshiba TX49 mipsIII variant.
That CPU adds a few additional instructions (also available in other
mips variants). I picked -m4900 as the cpu flag, and picked 0x008b0000
as the magic elf ident, E_MIPS_MACH_4900.
built on i686-pc-linux-gnu, and tested as a cross assembler. ok?
This work has been supported by Wind River Systems
nathan
--
Dr Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
'But that's a lie.' - 'Yes it is. What's your point?'
nathan@codesourcery.com : http://www.cs.bris.ac.uk/~nathan/ : nathan@acm.org
2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
bdf:
* aoutx.h (aout_@var{size}_machine_type): Add bfd_mach_mips4900.
* archures.c (bfd_mach_mips4900): New #define.
* bfd-in2.h: Regenerated.
* cpu-mips.h (I_mips4900): New enum value.
(arch_info_struct): Add 4900
* elfxx-mips.c (elf_mips_mach): Add E_MIPS_MACH_4900.
(_bfd_mips_elf_final_write_processing): Add bfd_mach_mips4900.
binutils:
* readelf.c (get_machine_flags): Add E_MIPS_MACH_4900.
gas:
* config/tc-mips.c (OPTION_M4900, OPTION_NO_M4900): New options.
(md_parse_option): Add 4900 options.
(mips_cpu_info_table): Add r4900.
(md_show_usage): Show 4900.
* doc/c-mips.texi (-m4900, -no-m4900): Document.
gas/testsuite:
* gas/mips/mips.exp: Add mips4900 test.
* gas/mips/mips4900.[sd]: Test 4900 instructions.
include:
* elf/mips.h (E_MIPS_MACH_4900): New machine variant.
* opcode/mips.h (INSN_4900): New variant mask.
(CPU_R4900): New cpu number.
(COMPUTE_MEMBERS_MASK): Adjust.
opcodes:
* mips-dis.c (mips_isa_type): Add bfd_mach_mips4900.
* mips-opc.c (T4): New shorthand mask.
(mips_builtin_opcodes): Enable 4900 specific variants.
Index: bfd/ChangeLog
===================================================================
RCS file: /cvs/src/src/bfd/ChangeLog,v
retrieving revision 1.1809
diff -c -3 -p -r1.1809 ChangeLog
*** bfd/ChangeLog 11 Nov 2002 05:05:22 -0000 1.1809
--- bfd/ChangeLog 11 Nov 2002 20:35:10 -0000
***************
*** 1,3 ****
--- 1,13 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * aoutx.h (aout_@var{size}_machine_type): Add bfd_mach_mips4900.
+ * archures.c (bfd_mach_mips4900): New #define.
+ * bfd-in2.h: Regenerated.
+ * cpu-mips.h (I_mips4900): New enum value.
+ (arch_info_struct): Add 4900
+ * elfxx-mips.c (elf_mips_mach): Add E_MIPS_MACH_4900.
+ (_bfd_mips_elf_final_write_processing): Add bfd_mach_mips4900.
+
2002-11-11 Kazu Hirata <kazu@cs.umass.edu>
* coff-h8300.c: Fix formatting.
Index: bfd/aoutx.h
===================================================================
RCS file: /cvs/src/src/bfd/aoutx.h,v
retrieving revision 1.36
diff -c -3 -p -r1.36 aoutx.h
*** bfd/aoutx.h 25 Oct 2002 02:45:53 -0000 1.36
--- bfd/aoutx.h 11 Nov 2002 20:35:13 -0000
*************** NAME(aout,machine_type) (arch, machine,
*** 791,796 ****
--- 791,797 ----
case bfd_mach_mips4400:
case bfd_mach_mips4600:
case bfd_mach_mips4650:
+ case bfd_mach_mips4900:
case bfd_mach_mips8000:
case bfd_mach_mips10000:
case bfd_mach_mips12000:
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.58
diff -c -3 -p -r1.58 archures.c
*** bfd/archures.c 6 Nov 2002 13:26:26 -0000 1.58
--- bfd/archures.c 11 Nov 2002 20:35:13 -0000
*************** DESCRIPTION
*** 134,139 ****
--- 134,140 ----
.#define bfd_mach_mips4400 4400
.#define bfd_mach_mips4600 4600
.#define bfd_mach_mips4650 4650
+ .#define bfd_mach_mips4900 4900 {* Toshiba TX49 *}
.#define bfd_mach_mips5000 5000
.#define bfd_mach_mips5400 5400
.#define bfd_mach_mips5500 5500
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.179
diff -c -3 -p -r1.179 bfd-in2.h
*** bfd/bfd-in2.h 6 Nov 2002 13:26:26 -0000 1.179
--- bfd/bfd-in2.h 11 Nov 2002 20:35:17 -0000
*************** enum bfd_architecture
*** 1525,1530 ****
--- 1525,1531 ----
#define bfd_mach_mips4400 4400
#define bfd_mach_mips4600 4600
#define bfd_mach_mips4650 4650
+ #define bfd_mach_mips4900 4900 /* Toshiba TX49 */
#define bfd_mach_mips5000 5000
#define bfd_mach_mips5400 5400
#define bfd_mach_mips5500 5500
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.15
diff -c -3 -p -r1.15 cpu-mips.c
*** bfd/cpu-mips.c 30 Sep 2002 11:53:56 -0000 1.15
--- bfd/cpu-mips.c 11 Nov 2002 20:35:17 -0000
*************** enum
*** 72,77 ****
--- 72,78 ----
I_mips4400,
I_mips4600,
I_mips4650,
+ I_mips4900,
I_mips5000,
I_mips5400,
I_mips5500,
*************** static const bfd_arch_info_type arch_inf
*** 101,106 ****
--- 102,108 ----
N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
+ N (64, 64, bfd_mach_mips4900, "mips:4900", false, NN(I_mips4900)),
N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
N (64, 64, bfd_mach_mips5400, "mips:5400", false, NN(I_mips5400)),
N (64, 64, bfd_mach_mips5500, "mips:5500", false, NN(I_mips5500)),
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.29
diff -c -3 -p -r1.29 elfxx-mips.c
*** bfd/elfxx-mips.c 22 Oct 2002 22:17:11 -0000 1.29
--- bfd/elfxx-mips.c 11 Nov 2002 20:35:22 -0000
*************** _bfd_elf_mips_mach (flags)
*** 3092,3097 ****
--- 3092,3100 ----
case E_MIPS_MACH_5500:
return bfd_mach_mips5500;
+ case E_MIPS_MACH_4900:
+ return bfd_mach_mips4900;
+
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
*************** _bfd_mips_elf_final_write_processing (ab
*** 5965,5970 ****
--- 5968,5977 ----
case bfd_mach_mips5500:
val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
+ break;
+
+ case bfd_mach_mips4900:
+ val = E_MIPS_ARCH_3 | E_MIPS_MACH_4900;
break;
case bfd_mach_mips5000:
Index: binutils/ChangeLog
===================================================================
RCS file: /cvs/src/src/binutils/ChangeLog,v
retrieving revision 1.562
diff -c -3 -p -r1.562 ChangeLog
*** binutils/ChangeLog 11 Nov 2002 16:53:18 -0000 1.562
--- binutils/ChangeLog 11 Nov 2002 20:35:24 -0000
***************
*** 1,3 ****
--- 1,7 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * readelf.c (get_machine_flags): Add E_MIPS_MACH_4900.
+
2002-11-11 Christopher Faylor <cgf@redhat.com>
* MAINTAINERS: Reinstate DJ Delorie as COFF maintainer. Drop COFF from
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.180
diff -c -3 -p -r1.180 readelf.c
*** binutils/readelf.c 7 Nov 2002 08:33:15 -0000 1.180
--- binutils/readelf.c 11 Nov 2002 20:35:29 -0000
*************** get_machine_flags (e_flags, e_machine)
*** 1852,1857 ****
--- 1852,1858 ----
case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
case E_MIPS_MACH_4120: strcat (buf, ", 4120"); break;
case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
+ case E_MIPS_MACH_4900: strcat (buf, ", 4900"); break;
case E_MIPS_MACH_5400: strcat (buf, ", 5400"); break;
case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
Index: gas/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.1551
diff -c -3 -p -r1.1551 ChangeLog
*** gas/ChangeLog 11 Nov 2002 17:21:33 -0000 1.1551
--- gas/ChangeLog 11 Nov 2002 20:35:32 -0000
***************
*** 1,3 ****
--- 1,11 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * config/tc-mips.c (OPTION_M4900, OPTION_NO_M4900): New options.
+ (md_parse_option): Add 4900 options.
+ (mips_cpu_info_table): Add r4900.
+ (md_show_usage): Show 4900.
+ * doc/c-mips.texi (-m4900, -no-m4900): Document.
+
2002-11-11 Christopher Faylor <cgf@redhat.com>
* configure.in: Use .gdbinit under Cygwin.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.177
diff -c -3 -p -r1.177 tc-mips.c
*** gas/config/tc-mips.c 7 Nov 2002 02:29:32 -0000 1.177
--- gas/config/tc-mips.c 11 Nov 2002 20:35:39 -0000
*************** struct option md_longopts[] =
*** 10269,10276 ****
#define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
{"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
{"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
#ifdef OBJ_ELF
! #define OPTION_ELF_BASE (OPTION_MD_BASE + 41)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
--- 10269,10280 ----
#define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
{"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
{"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
+ #define OPTION_M4900 (OPTION_MD_BASE + 41)
+ #define OPTION_NO_M4900 (OPTION_MD_BASE + 42)
+ {"m4900", no_argument, NULL, OPTION_M4900},
+ {"no-m4900", no_argument, NULL, OPTION_NO_M4900},
#ifdef OBJ_ELF
! #define OPTION_ELF_BASE (OPTION_MD_BASE + 43)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
*************** md_parse_option (c, arg)
*** 10435,10440 ****
--- 10439,10452 ----
case OPTION_NO_M3900:
break;
+ case OPTION_M4900:
+ mips_set_option_string (&mips_arch_string, "4900");
+ mips_set_option_string (&mips_tune_string, "4900");
+ break;
+
+ case OPTION_NO_M4900:
+ break;
+
case OPTION_MDMX:
mips_opts.ase_mdmx = 1;
break;
*************** static const struct mips_cpu_info mips_c
*** 14283,14288 ****
--- 14295,14301 ----
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
+ { "r4900", 0, ISA_MIPS3, CPU_R4900 },
/* MIPS IV */
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
*************** MIPS options:\n\
*** 14507,14512 ****
--- 14520,14526 ----
show (stream, "4010", &column, &first);
show (stream, "4100", &column, &first);
show (stream, "4650", &column, &first);
+ show (stream, "4900", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.24
diff -c -3 -p -r1.24 c-mips.texi
*** gas/doc/c-mips.texi 30 Sep 2002 12:04:31 -0000 1.24
--- gas/doc/c-mips.texi 11 Nov 2002 20:35:40 -0000
*************** instructions around accesses to the @sam
*** 141,146 ****
--- 141,148 ----
@itemx -no-m3900
@itemx -m4100
@itemx -no-m4100
+ @itemx -m4900
+ @itemx -no-m4900
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
*************** vr4181,
*** 165,170 ****
--- 167,173 ----
4400,
4600,
4650,
+ 4900,
5000,
rm5200,
rm5230,
Index: gas/testsuite/ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/testsuite/ChangeLog,v
retrieving revision 1.394
diff -c -3 -p -r1.394 ChangeLog
*** gas/testsuite/ChangeLog 7 Nov 2002 09:20:09 -0000 1.394
--- gas/testsuite/ChangeLog 11 Nov 2002 20:35:43 -0000
***************
*** 1,3 ****
--- 1,8 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * gas/mips/mips.exp: Add mips4900 test.
+ * gas/mips/mips4900.[sd]: Test 4900 instructions.
+
2002-11-07 Nick Clifton <nickc@redhat.com>
* gas/all/gas.exp: Only run fastcall test for x86 PE targets.
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.50
diff -c -3 -p -r1.50 mips.exp
*** gas/testsuite/gas/mips/mips.exp 21 Oct 2002 14:59:30 -0000 1.50
--- gas/testsuite/gas/mips/mips.exp 11 Nov 2002 20:35:44 -0000
*************** if { [istarget mips*-*-*] } then {
*** 153,158 ****
--- 153,159 ----
run_dump_test "mips4010"
run_dump_test "mips4650"
run_dump_test "mips4100"
+ run_dump_test "mips4900"
run_dump_test "vr4111"
run_dump_test "vr4120"
run_dump_test "vr4122"
Index: include/ChangeLog
===================================================================
RCS file: /cvs/src/src/include/ChangeLog,v
retrieving revision 1.180
diff -c -3 -p -r1.180 ChangeLog
*** include/ChangeLog 11 Nov 2002 14:29:01 -0000 1.180
--- include/ChangeLog 11 Nov 2002 20:35:46 -0000
***************
*** 1,3 ****
--- 1,10 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * elf/mips.h (E_MIPS_MACH_4900): New machine variant.
+ * opcode/mips.h (INSN_4900): New variant mask.
+ (CPU_R4900): New cpu number.
+ (COMPUTE_MEMBERS_MASK): Adjust.
+
2002-11-11 Svein E. Seldal <Svein.Seldal@solidas.com>
* opcode/tic4x.h: Added new opcodes and corrected some bugs. Add
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.17
diff -c -3 -p -r1.17 mips.h
*** include/elf/mips.h 30 Sep 2002 11:53:55 -0000 1.17
--- include/elf/mips.h 11 Nov 2002 20:35:47 -0000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 178,183 ****
--- 178,184 ----
#define E_MIPS_MACH_4120 0x00870000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
+ #define E_MIPS_MACH_4900 0x008b0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.29
diff -c -3 -p -r1.29 mips.h
*** include/opcode/mips.h 30 Sep 2002 11:58:09 -0000 1.29
--- include/opcode/mips.h 11 Nov 2002 20:35:48 -0000
*************** struct mips_opcode
*** 380,385 ****
--- 380,387 ----
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
+ /* Toshiba R4900 instruction. */
+ #define INSN_4900 0x04000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
*************** struct mips_opcode
*** 406,411 ****
--- 408,414 ----
#define CPU_R4400 4400
#define CPU_R4600 4600
#define CPU_R4650 4650
+ #define CPU_R4900 4900
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
*************** struct mips_opcode
*** 430,435 ****
--- 433,439 ----
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
+ || (cpu == CPU_R4900 && ((insn)->membership & INSN_4900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
Index: opcodes/ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.498
diff -c -3 -p -r1.498 ChangeLog
*** opcodes/ChangeLog 8 Nov 2002 00:46:21 -0000 1.498
--- opcodes/ChangeLog 11 Nov 2002 20:35:51 -0000
***************
*** 1,3 ****
--- 1,9 ----
+ 2002-11-11 Nathan Sidwell <nathan@codesourcery.com>
+
+ * mips-dis.c (mips_isa_type): Add bfd_mach_mips4900.
+ * mips-opc.c (T4): New shorthand mask.
+ (mips_builtin_opcodes): Enable 4900 specific variants.
+
2002-11-07 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c (EVUIMM_4): Change bit size to 32.
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.34
diff -c -3 -p -r1.34 mips-dis.c
*** opcodes/mips-dis.c 30 Sep 2002 11:58:10 -0000 1.34
--- opcodes/mips-dis.c 11 Nov 2002 20:35:51 -0000
*************** mips_isa_type (mach, isa, cputype)
*** 406,411 ****
--- 406,415 ----
*cputype = CPU_R4650;
*isa = ISA_MIPS3;
break;
+ case bfd_mach_mips4900:
+ *cputype = CPU_R4900;
+ *isa = ISA_MIPS3;
+ break;
case bfd_mach_mips5000:
*cputype = CPU_R5000;
*isa = ISA_MIPS4;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.39
diff -c -3 -p -r1.39 mips-opc.c
*** opcodes/mips-opc.c 30 Sep 2002 11:58:10 -0000 1.39
--- opcodes/mips-opc.c 11 Nov 2002 20:35:52 -0000
*************** Software Foundation, 59 Temple Place - S
*** 99,104 ****
--- 99,105 ----
#define L1 INSN_4010
#define V1 (INSN_4100 | INSN_4111 | INSN_4120)
#define T3 INSN_3900
+ #define T4 INSN_4900
#define M1 INSN_10000
#define SB1 INSN_SB1
#define N411 INSN_4111
*************** const struct mips_opcode mips_builtin_op
*** 135,141 ****
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 },
--- 136,142 ----
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3|T4 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 },
*************** const struct mips_opcode mips_builtin_op
*** 538,544 ****
--- 539,547 ----
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
+ {"dmult", "d,s,t", 0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, T4 },
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
+ {"dmultu", "d,s,t", 0x0000001d, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, T4 },
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
*************** const struct mips_opcode mips_builtin_op
*** 689,700 ****
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
! {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
! {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
! {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
! {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N411 },
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
--- 692,703 ----
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
! {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1|T4 },
! {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1|T4 },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
! {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1|T4 },
! {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1|T4 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N411 },
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
*************** const struct mips_opcode mips_builtin_op
*** 818,826 ****
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
! {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
! {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
--- 821,829 ----
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
! {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1|T4 },
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
! {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1|T4 },
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
*************** const struct mips_opcode mips_builtin_op
*** 932,940 ****
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
! {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
! {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 },
! {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 },
{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
--- 935,943 ----
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
! {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|T4 },
! {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|T4 },
! {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|T4 },
{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },