This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
Fix opcode definitions for Book-E
- From: Nick Clifton <nickc at redhat dot com>
- To: binutils at sources dot redhat dot com
- Date: 13 Sep 2002 10:08:32 +0100
- Subject: Fix opcode definitions for Book-E
Hi Guys,
I am applying the patch below to fix up several problems with the
opcode definitions for the Book-E series of PowerPC processors.
Cheers
Nick
2002-09-13 Nick Clifton <nickc@redhat.com>
* ppc-opc.c (MFDEC2): Include Book-E.
(PPCCHLK64): New opcode mask.
(evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
Book-E instructions.
(evfsneg): Fix opcode value.
(dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
mask.
(mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
Book-E.
(extsw): Restrict to 64-bit PPC instruction sets.
(extsw.): Does not exist in 64-bit Book-E.
(powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
they are no longer needed.
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.37
diff -c -3 -p -w -r1.37 ppc-opc.c
*** opcodes/ppc-opc.c 4 Sep 2002 12:37:30 -0000 1.37
--- opcodes/ppc-opc.c 13 Sep 2002 08:50:07 -0000
*************** extract_tbr (insn, dialect, invalid)
*** 1766,1772 ****
#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
#define MFDEC1 PPC_OPCODE_POWER
! #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
#define BOOKE PPC_OPCODE_BOOKE
#define BOOKE64 PPC_OPCODE_BOOKE64
#define CLASSIC PPC_OPCODE_CLASSIC
--- 1766,1772 ----
#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
#define MFDEC1 PPC_OPCODE_POWER
! #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
#define BOOKE PPC_OPCODE_BOOKE
#define BOOKE64 PPC_OPCODE_BOOKE64
#define CLASSIC PPC_OPCODE_CLASSIC
*************** extract_tbr (insn, dialect, invalid)
*** 1776,1781 ****
--- 1776,1782 ----
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCCHLK PPC_OPCODE_CACHELCK
+ #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
/* The opcode table.
*************** const struct powerpc_opcode powerpc_opco
*** 2089,2095 ****
--- 2090,2098 ----
{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RD, RB, UIMM } },
{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RD, RB, RA } },
{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RD, UIMM, RB } },
+ { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RD, RB, UIMM } },
{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RD, RA } },
{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RD, RA } },
{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RD, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2102,2112 ****
--- 2105,2117 ----
{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RD, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2171,2177 ****
{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
! { "evfsneg", VX(4, 656), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },
--- 2176,2182 ----
{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
! { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3255,3260 ****
--- 3260,3268 ----
{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
+ { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
+ { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
+ { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3406,3412 ****
{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
! { "dcbtstlse",X(31,142),X_MASK, PPCCHLK, { CT, RA, RB }},
{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
--- 3414,3420 ----
{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
! { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
*************** const struct powerpc_opcode powerpc_opco
*** 3434,3440 ****
{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
! { "dcbtlse", X(31,174), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
--- 3442,3448 ----
{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
! { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
*************** const struct powerpc_opcode powerpc_opco
*** 3514,3520 ****
{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
! { "icblce", X(31,238), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
--- 3522,3528 ----
{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
! { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3636,3641 ****
--- 3644,3655 ----
{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
+ { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
+ { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
+ { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
+ { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
+ { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
+ { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3653,3662 ****
--- 3667,3679 ----
{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
+ { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
+ { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
+ { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3664,3671 ****
--- 3681,3720 ----
{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
+ { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
+ { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
+ { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
+ { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
+ { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
+ { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
+ { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
+ { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
+ { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
+ { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
+ { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
+ { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
+ { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
+ { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
+ { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
+ { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
+ { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3676,3681 ****
--- 3725,3733 ----
{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
+ { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
+ { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
+ { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3698,3707 ****
{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
- { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
- { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
- { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
- { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
--- 3750,3755 ----
*************** const struct powerpc_opcode powerpc_opco
*** 3709,3714 ****
--- 3757,3765 ----
{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
+ { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
+ { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
+ { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3725,3730 ****
--- 3776,3782 ----
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
+ { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3742,3758 ****
{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
- { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
- { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
- { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
- { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
- { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
--- 3794,3810 ----
{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
+ { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
+ { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
+ { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
+ { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
+ { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3783,3788 ****
--- 3835,3841 ----
{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
+ { "mftb", X(31,371), X_MASK, BOOKE, { RT, TBR } },
{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3801,3807 ****
{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
! { "dcblce", X(31,398), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
--- 3854,3860 ----
{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
! { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3903,3908 ****
--- 3956,3968 ----
{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
+ { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
+ { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
+ { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
+ { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
+ { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
+ { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
+ { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3920,3943 ****
--- 3980,4049 ----
{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
+ { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
+ { "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
+ { "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
+ { "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
+ { "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
+ { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
+ { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
+ { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
+ { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
+ { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
+ { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
+ { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
+ { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
+ { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
+ { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
+ { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
+ { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
+ { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
+ { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
+ { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RT } },
+ { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
+ { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
+ { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
+ { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
+ { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
+ { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
+ { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
+ { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
+ { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
+ { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
+ { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3945,3955 ****
--- 4051,4068 ----
{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
+ { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
+ { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
+ { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
+ { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
+ { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
+ { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
+ { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 3968,3998 ****
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
- { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
- { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
- { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
- { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
- { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
- { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
- { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
- { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
- { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
- { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
- { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
- { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
- { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
- { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
- { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
- { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
- { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
- { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
- { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
--- 4081,4097 ----
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
+ { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
+ { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
+ { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
+ { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
+ { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 4028,4034 ****
{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
! { "icbtlse", X(31,494), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
--- 4127,4133 ----
{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
! { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
*************** const struct powerpc_opcode powerpc_opco
*** 4039,4045 ****
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
! { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
--- 4138,4144 ----
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
! { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 4152,4158 ****
{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
! { "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
--- 4251,4257 ----
{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
! { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 4189,4196 ****
{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
! { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
! { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE, { RA, RB } },
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
--- 4288,4295 ----
{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
! { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
! { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 4238,4245 ****
{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
! { "extsw", XRC(31,986,0), XRB_MASK, PPC | BOOKE64, { RA, RS } },
! { "extsw.", XRC(31,986,1), XRB_MASK, PPC | BOOKE64, { RA, RS } },
{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
--- 4337,4344 ----
{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
! { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
! { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
*************** const struct powerpc_macro powerpc_macro
*** 4557,4566 ****
{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
-
- { "mftbl", 1, BOOKE, "mfspr %0,tbl" },
- { "mftbu", 1, BOOKE, "mfspr %0,tbu" },
- { "mftb", 2, BOOKE, "mfspr %0,%1" },
};
const int powerpc_num_macros =
--- 4656,4661 ----