This is the mail archive of the mailing list for the binutils project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: include/dis-asm.h patch for cgen disassemblers

Hi -

cagney wrote:
> [...]
> GDB at the moment uses an arch/mach pair to select an architecture.  It 
> assumes that, just like in FSF BFD, bfd_architecture indicates a related 
> family of instruction set architectures.  [...]

That's good (except that persistent "isa" == "processor architecture"
confusion).  gdb still ranks bfd_arch above arch/mach pairs in some
contexts (e.g., gdbarch_register), but that looks changeable should
the desire arise.

> Here I consider GDB to simply be reflecting the status quo.  I don't 
> think what you've described of the PS2 is consistent with this, I don't 
> see it as my problem to nudge the great bfd ship forward.  Rather it is 
> your problem to change the the direction of the entire binutils+gdb 
> toolchain.

Dude, you're the one who brought up PS2, an irrelevant aside
to my original posting!  If gdb has no multiarch problem with
the current arrangement after all, then I have little residual
curiosity toward further discussions.  Please carry it off to
another thread.

> >> Can I assume, for instance, that INSTRUCTION_SUBSETS, wouldn't be used 
> >> to select orthogonal ISAs that run on different compute engines?
> >
> > I have no such intent -- as I've had to say too many times now, I need
> > the field to further refine the set of instructions identified by some
> > given bfd_arch/bfd_mach pair.
> No, you ducked the question.  

(What, by saying "no such intent"?  I wish others "ducked questions"
with as much clarity.)

> Please clearly document this as a comment 
> that goes with the addition of this field.

Right.  Here is the version I'm about to commit.  Wording
quibbles are welcome, I guess as follow-up patches.

- FChE

Index: opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2002-02-04  Frank Ch. Eigler  <>
+	* (print_insn_@arch@): Support disassemble_info.insn_sets.

Index: opcodes/
@@ -386,7 +386,7 @@
   isa = CGEN_COMPUTE_ISA (info);
-  isa = 0;
+  isa = info->insn_sets;
   /* If we've switched cpu's, close the current table and open a new one.  */

Index: include/ChangeLog
+2002-02-04  Frank Ch. Eigler  <>
+	* dis-asm.h (disassemble_info): New field `insn_sets'.

Index: include/dis-asm.h
@@ -73,6 +73,11 @@
   unsigned long mach;
   /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
   enum bfd_endian endian;
+  /* An arch/mach-specific bitmask of selected instruction subsets, mainly
+     for processors with run-time-switchable instruction sets.  The default,
+     zero, means that there is no constraint.  CGEN-based opcodes ports
+     may use ISA_foo masks.  */
+  unsigned long insn_sets;
   /* Some targets need information about the current section to accurately
      display insns.  If this is NULL, the target disassembler function
@@ -271,6 +276,7 @@
   (INFO).flavour = bfd_target_unknown_flavour, \
   (INFO).arch = bfd_arch_unknown, \
   (INFO).mach = 0, \
+  (INFO).insn_sets = 0, \
   (INFO).endian = BFD_ENDIAN_UNKNOWN, \
   (INFO).octets_per_byte = 1, \

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]