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binutils patch
- To: binutils at sources dot redhat dot com
- Subject: binutils patch
- From: Daniel Egger <egger at suse dot de>
- Date: 16 Aug 2001 22:36:16 +0200
Hija,
I've a small problem and I'll post it here for people with more binutils
hacking experience than me.
I'm trying to add the missing AltiVec (PPC) functions to the opcodes
part of binutils. So far everything works nicely, the "data stream
touch" operations are properly coded into the object file and objdump
can even decipher it again (I checked that the bits are set accordingly
in the binary and the executable runs fine and even shows a speedup).
However I failed to get the "transient" type of the opcodes to work.
The encoding is the same except that the 7th MSB is set to one and
although I do what everyone else is doing - shifting an one by 25
to the left and or'ing it to the opcode - I always end up with the
normal version of the opcode which is also okay according to the
manuals but has a slightly different notion and for speed sakeness
I'd like to get it correct.
The patch is:
--- opcodes/ppc-opc.c.orig Thu Aug 9 16:16:28 2001
+++ opcodes/ppc-opc.c Thu Aug 9 20:30:31 2001
@@ -375,8 +375,12 @@
#define SR SPRG + 1
{ 4, 16, 0, 0, 0 },
+ /* The STRM field in an X form instruction. */
+#define STRM SR + 1
+ { 2, 21, 0, 0, 0 },
+
/* The SV field in a POWER SC form instruction. */
-#define SV SR + 1
+#define SV STRM + 1
{ 14, 2, 0, 0, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
@@ -1180,6 +1184,10 @@
/* An X_MASK with the RT and RA fields fixed. */
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
+/* An X_MASK with the T field fixed. */
+#define T_MASK ((unsigned long)0x1 << 25)
+#define XT_MASK (X_MASK | T_MASK)
+
/* An X form comparison instruction. */
#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) &
1) << 21)
@@ -3199,6 +3207,13 @@
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
+
+{ "dss", X(31,822), X_MASK, PPCVEC, { STRM }
},
+{ "dssall", X(31,822), XT_MASK, PPCVEC, { STRM } },
+{ "dst", X(31,342), X_MASK, PPCVEC, { RA,
RB, STRM }+{ "dstt", X(31,342), XT_MASK, PPCVEC, { RA,
RB, STRM } },
+{ "dstst", X(31,374), X_MASK, PPCVEC, { RA,
RB, STRM }+{ "dststt", X(31,374), XT_MASK, PPCVEC, { RA,
RB, STRM } },
{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB }
},
{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB }
},
In case this is messed up for you I'll attach the patch.
Any ideas?
Please reply to my personal address as I'm not subscribed.
Servus,
Daniel
--- opcodes/ppc-opc.c.orig Thu Aug 9 16:16:28 2001
+++ opcodes/ppc-opc.c Thu Aug 9 20:30:31 2001
@@ -375,8 +375,12 @@
#define SR SPRG + 1
{ 4, 16, 0, 0, 0 },
+ /* The STRM field in an X form instruction. */
+#define STRM SR + 1
+ { 2, 21, 0, 0, 0 },
+
/* The SV field in a POWER SC form instruction. */
-#define SV SR + 1
+#define SV STRM + 1
{ 14, 2, 0, 0, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
@@ -1180,6 +1184,10 @@
/* An X_MASK with the RT and RA fields fixed. */
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
+/* An X_MASK with the T field fixed. */
+#define T_MASK ((unsigned long)0x1 << 25)
+#define XT_MASK (X_MASK | T_MASK)
+
/* An X form comparison instruction. */
#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
@@ -3199,6 +3207,13 @@
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
+
+{ "dss", X(31,822), X_MASK, PPCVEC, { STRM } },
+{ "dssall", X(31,822), XT_MASK, PPCVEC, { STRM } },
+{ "dst", X(31,342), X_MASK, PPCVEC, { RA, RB, STRM } },
+{ "dstt", X(31,342), XT_MASK, PPCVEC, { RA, RB, STRM } },
+{ "dstst", X(31,374), X_MASK, PPCVEC, { RA, RB, STRM } },
+{ "dststt", X(31,374), XT_MASK, PPCVEC, { RA, RB, STRM } },
{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },