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[binutils-gdb] RX: include - Add RXv3 support.
- From: Yoshinori Sato <ysato at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 5 Jan 2019 13:54:34 -0000
- Subject: [binutils-gdb] RX: include - Add RXv3 support.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=59581069b4d070ab0ac61047177ee119110d678e
commit 59581069b4d070ab0ac61047177ee119110d678e
Author: Yoshinori Sato <ysato@users.sourceforge.jp>
Date: Tue Dec 25 20:44:15 2018 +0900
RX: include - Add RXv3 support.
* elf/rx.h (EF_RX_CPU_MASK): Update new bits.
(E_FLAG_RX_V3): New RXv3 type.
* opcode/rx.h (RX_Size): Add double size.
(RX_Operand_Type): Add double FPU registers.
(RX_Opcode_ID): Add new instuctions.
Diff:
---
include/ChangeLog | 9 +++++++++
include/elf/rx.h | 3 ++-
include/opcode/rx.h | 32 ++++++++++++++++++++++++++++++++
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/include/ChangeLog b/include/ChangeLog
index 3fc4606..939eec9 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,12 @@
+2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * elf/rx.h (EF_RX_CPU_MASK): Update new bits.
+ (E_FLAG_RX_V3): New RXv3 type.
+ * opcode/rx.h (RX_Size): Add double size.
+ (RX_Operand_Type): Add double FPU registers.
+ (RX_Opcode_ID): Add new instuctions.
+
+
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
diff --git a/include/elf/rx.h b/include/elf/rx.h
index 4248823..82b1817 100644
--- a/include/elf/rx.h
+++ b/include/elf/rx.h
@@ -111,7 +111,7 @@ START_RELOC_NUMBERS (elf_rx_reloc_type)
END_RELOC_NUMBERS (R_RX_max)
#define EF_RX_CPU_RX 0x00000079 /* FIXME: this collides with the E_FLAG_RX_... values below. */
-#define EF_RX_CPU_MASK 0x0000007F /* specific cpu bits. */
+#define EF_RX_CPU_MASK 0x000003FF /* specific cpu bits. */
#define EF_RX_ALL_FLAGS (EF_RX_CPU_MASK)
/* Values for the e_flags field in the ELF header. */
@@ -124,6 +124,7 @@ END_RELOC_NUMBERS (R_RX_max)
#define E_FLAG_RX_SINSNS_NO 0 /* Bit-5 if this binary must not be linked with a string instruction using binary. */
#define E_FLAG_RX_SINSNS_MASK (3 << 6) /* Mask of bits used to determine string instruction use. */
#define E_FLAG_RX_V2 (1 << 8) /* RX v2 instructions */
+#define E_FLAG_RX_V3 (1 << 9) /* RX v3 instructions */
/* These define the addend field of R_RX_RH_RELAX relocations. */
#define RX_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */
diff --git a/include/opcode/rx.h b/include/opcode/rx.h
index a1519ae..8b27fe5 100644
--- a/include/opcode/rx.h
+++ b/include/opcode/rx.h
@@ -38,6 +38,7 @@ typedef enum
RX_SWord,
RX_3Byte,
RX_Long,
+ RX_Double,
RX_Bad_Size,
RX_MAX_SIZE
} RX_Size;
@@ -54,6 +55,11 @@ typedef enum
RX_Operand_Condition, /* eq, gtu, etc */
RX_Operand_Flag, /* [UIOSZC] */
RX_Operand_TwoReg, /* [Rn + scale*R2] */
+ RX_Operand_DoubleReg, /* DRn */
+ RX_Operand_DoubleRegH,/* DRHn */
+ RX_Operand_DoubleRegL,/* DRLn */
+ RX_Operand_DoubleCReg,/* DCRxx */
+ RX_Operand_DoubleCond,/* UN/EQ/LE/LT */
} RX_Operand_Type;
typedef enum
@@ -180,6 +186,32 @@ typedef enum
RXO_racl,
RXO_rdacl,
RXO_rdacw,
+
+ RXO_bfmov,
+ RXO_bfmovz,
+ RXO_rstr,
+ RXO_save,
+ RXO_dmov,
+ RXO_dpopm,
+ RXO_dpushm,
+ RXO_mvfdc,
+ RXO_mvfdr,
+ RXO_mvtdc,
+ RXO_dabs,
+ RXO_dadd,
+ RXO_dcmp,
+ RXO_ddiv,
+ RXO_dmul,
+ RXO_dneg,
+ RXO_dround,
+ RXO_dsqrt,
+ RXO_dsub,
+ RXO_dtoi,
+ RXO_dtof,
+ RXO_dtou,
+ RXO_ftod,
+ RXO_itod,
+ RXO_utod
} RX_Opcode_ID;
/* Condition bitpatterns, as registers. */