From 7b12776584c51dbecb1033e107f6b9f45de47a1b Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Mon, 27 Nov 2023 17:02:55 +0000 Subject: [PATCH] aarch64: Improve special-case handling in AdvSIMD double-precision libmvec routines Avoids emitting many saves/restores of vector registers, reduces the amount of code generated around the scalar fallback. --- sysdeps/aarch64/fpu/v_math.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sysdeps/aarch64/fpu/v_math.h b/sysdeps/aarch64/fpu/v_math.h index cfc87f8dd0..d286eb81b3 100644 --- a/sysdeps/aarch64/fpu/v_math.h +++ b/sysdeps/aarch64/fpu/v_math.h @@ -137,7 +137,13 @@ v_lookup_u64 (const uint64_t *tab, uint64x2_t idx) static inline float64x2_t v_call_f64 (double (*f) (double), float64x2_t x, float64x2_t y, uint64x2_t p) { - return (float64x2_t){ p[0] ? f (x[0]) : y[0], p[1] ? f (x[1]) : y[1] }; + double p1 = p[1]; + double x1 = x[1]; + if (__glibc_likely (p[0])) + y[0] = f (x[0]); + if (__glibc_likely (p1)) + y[1] = f (x1); + return y; } static inline float64x2_t v_call2_f64 (double (*f) (double, double), float64x2_t x1, float64x2_t x2, -- 2.43.5