From 5b710a88a83910a45c659bcf5fd2969fd1ee2c02 Mon Sep 17 00:00:00 2001 From: Paul Floyd Date: Sat, 30 Sep 2023 16:34:45 +0200 Subject: [PATCH] coverity: mostly unsigned >= 0 comparisons --- VEX/priv/guest_arm64_toIR.c | 16 ++++++++-------- VEX/priv/guest_arm_toIR.c | 2 +- VEX/priv/guest_ppc_helpers.c | 2 ++ VEX/priv/host_amd64_isel.c | 5 ++++- VEX/priv/host_arm_defs.c | 2 +- VEX/priv/host_generic_reg_alloc3.c | 4 ++-- VEX/priv/host_ppc_isel.c | 1 - VEX/priv/host_s390_defs.c | 4 ++++ VEX/priv/host_x86_isel.c | 1 - callgrind/jumps.c | 2 +- coregrind/m_debuginfo/image.c | 2 +- coregrind/m_debuginfo/storage.c | 2 +- coregrind/m_execontext.c | 2 +- coregrind/m_main.c | 2 +- coregrind/m_mallocfree.c | 2 +- coregrind/m_scheduler/scheduler.c | 2 +- coregrind/m_seqmatch.c | 9 ++++----- coregrind/m_threadstate.c | 2 +- coregrind/m_translate.c | 2 +- coregrind/m_transtab.c | 4 ++-- helgrind/hg_main.c | 4 ++-- helgrind/hg_wordset.c | 2 -- helgrind/libhb_core.c | 7 ++++--- memcheck/mc_main.c | 2 +- 24 files changed, 44 insertions(+), 39 deletions(-) diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 505b66f30f..a6f5272b9c 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -2747,7 +2747,7 @@ Bool dis_ARM64_data_processing_immediate(/*MB_OUT*/DisResult* dres, nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), shift); return True; } - if (!is64 && immS >= 0 && immS <= 30 + if (!is64 && immS <= 30 && immR == immS + 1 && opc == BITS2(1,0)) { // 32-bit shift left UInt shift = 32 - immR; @@ -3690,7 +3690,7 @@ Bool dis_ARM64_data_processing_register(/*MB_OUT*/DisResult* dres, vassert(0); } - vassert(ix >= 0 && ix <= 7); + vassert(ix <= 7); putIReg64orZR( dd, @@ -8424,7 +8424,7 @@ static IRTemp math_TBL_TBX ( IRTemp tab[4], UInt len, IRTemp src, UInt tabent; for (tabent = 0; tabent <= len; tabent++) { - vassert(tabent >= 0 && tabent < 4); + vassert(tabent < 4); IRTemp bias = newTempV128(); assign(bias, mkexpr(tabent == 0 ? allZero : allXX[tabent-1])); @@ -10351,7 +10351,7 @@ Bool dis_AdvSIMD_scalar_shift_by_imm(/*MB_OUT*/DisResult* dres, UInt insn) if (bitU == 1 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) { /* -------- 1,1xxx,01010 SLI d_d_#imm -------- */ UInt sh = immhb - 64; - vassert(sh >= 0 && sh < 64); + vassert(sh < 64); if (sh == 0) { putQReg128(dd, unop(Iop_ZeroHI64ofV128, getQReg128(nn))); } else { @@ -11529,7 +11529,7 @@ Bool dis_AdvSIMD_scalar_x_indexed_element(/*MB_OUT*/DisResult* dres, UInt insn) case BITS4(0,1,1,1): ks = 2; break; default: vassert(0); } - vassert(ks >= 0 && ks <= 2); + vassert(ks <= 2); UInt mm = 32; // invalid UInt ix = 16; // invalid switch (size) { @@ -11736,7 +11736,7 @@ Bool dis_AdvSIMD_shift_by_immediate(/*MB_OUT*/DisResult* dres, UInt insn) Bool isAcc = opcode == BITS5(0,0,1,1,0); Bool ok = getLaneInfo_IMMH_IMMB(&shift, &size, immh, immb); if (!ok || (bitQ == 0 && size == X11)) return False; - vassert(size >= 0 && size <= 3); + vassert(size <= 3); UInt lanebits = 8 << size; vassert(shift >= 1 && shift <= lanebits); IROp op = isU ? mkVecRSHU(size) : mkVecRSHS(size); @@ -12336,7 +12336,7 @@ Bool dis_AdvSIMD_three_different(/*MB_OUT*/DisResult* dres, UInt insn) case BITS4(1,0,1,1): ks = 2; break; default: vassert(0); } - vassert(ks >= 0 && ks <= 2); + vassert(ks <= 2); if (size == X00 || size == X11) return False; vassert(size <= 2); IRTemp vecN, vecM, vecD, res, sat1q, sat1n, sat2q, sat2n; @@ -14305,7 +14305,7 @@ Bool dis_AdvSIMD_vector_x_indexed_elem(/*MB_OUT*/DisResult* dres, UInt insn) case BITS4(0,1,1,1): ks = 2; break; default: vassert(0); } - vassert(ks >= 0 && ks <= 2); + vassert(ks <= 2); Bool is2 = bitQ == 1; UInt mm = 32; // invalid UInt ix = 16; // invalid diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index cdc1265f0d..5e9e49568c 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -1340,7 +1340,7 @@ void setFlags_D1_D2_ND ( UInt cc_op, IRTemp t_dep1, vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32)); vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32)); vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32)); - // strictly unsigned cc_op must always be >= 0, keeong for readability + // strictly unsigned cc_op must always be >= 0, keeping for readability vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER); if (guardT == IRTemp_INVALID) { /* unconditional */ diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index bfdb11b14c..1a8e9fbf71 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -1776,6 +1776,8 @@ void vsx_matrix_8bit_ger_dirty_helper( VexGuestPPC64State* gst, else if ( inst == XVI8GER4SPP ) result[j] = clampS64toS32(sum + acc_word[j]); + // @todo PJF Coverity complains that if none of the abofe ifs are true + // then result gets used uninitialized } else { result[j] = 0; } diff --git a/VEX/priv/host_amd64_isel.c b/VEX/priv/host_amd64_isel.c index 5104e7dbe7..7623519617 100644 --- a/VEX/priv/host_amd64_isel.c +++ b/VEX/priv/host_amd64_isel.c @@ -619,7 +619,7 @@ void doHelperCall ( /*OUT*/UInt* stackAdjustAfterCall, addInstr(env, mk_iMOVsd_RR( hregAMD64_RSP(), r_vecRetAddr )); } - vassert(n_args >= 0 && n_args <= 6); + vassert(n_args <= 6); for (i = 0; i < n_args; i++) { IRExpr* arg = args[i]; if (UNLIKELY(arg->tag == Iex_GSPTR)) { @@ -2610,8 +2610,11 @@ static HReg iselCondCode_R_wrk ( ISelEnv* env, const IRExpr* e ) addInstr(env, AMD64Instr_Set64(cc, res)); return res; + // PJF old debug code? - unreachable + /* ppIRExpr(e); vpanic("iselCondCode_R(amd64)"); + */ } diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c index 8d17238e3c..e30336583d 100644 --- a/VEX/priv/host_arm_defs.c +++ b/VEX/priv/host_arm_defs.c @@ -417,7 +417,7 @@ void ppARMAModeN ( ARMAModeN* am ) { /* --------- Reg or imm-8x4 operands --------- */ static UInt ROR32 ( UInt x, UInt sh ) { - vassert(sh >= 0 && sh < 32); + vassert(sh < 32); if (sh == 0) return x; else diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index f1eb4c9b18..b7446921a4 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -148,9 +148,9 @@ typedef } RRegLRState; -/* v is always unsigned, wish we could static assert that */ +/* v and r are always unsigned, wish we could static assert that */ #define IS_VALID_VREGNO(v) ((v) < n_vregs) -#define IS_VALID_RREGNO(r) ((r) >= 0 && (r) < n_rregs) +#define IS_VALID_RREGNO(r) ((r) < n_rregs) #define FREE_VREG(v) \ do { \ diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 75a753f75a..34b6afe7cf 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -308,7 +308,6 @@ static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO, ISelEnv* env, IRTemp tmp ) { - vassert(tmp >= 0); vassert(tmp < env->n_vregmap); vassert(! hregIsInvalid(env->vregmapMedLo[tmp])); *vrLO = env->vregmapLo[tmp]; diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index c811dc5b80..471be8cb23 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -11709,8 +11709,12 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn) case S390_VEC_FLOAT_COMPARE_EQUAL: return s390_emit_VFCE(buf, v1, v2, v3, s390_getM_from_size(size), 0, 0); case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL: + // PJF I assume that CHE is cmpare higher or equal so the order need swapping + // coverity[SWAPPED_ARGUMENTS:FALSE] return s390_emit_VFCHE(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0); case S390_VEC_FLOAT_COMPARE_LESS: + // PJF as above but this time compare higher + // coverity[SWAPPED_ARGUMENTS:FALSE] return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0); default: diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c index 391b3b4834..e89b145327 100644 --- a/VEX/priv/host_x86_isel.c +++ b/VEX/priv/host_x86_isel.c @@ -190,7 +190,6 @@ typedef static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) { - vassert(tmp >= 0); vassert(tmp < env->n_vregmap); return env->vregmap[tmp]; } diff --git a/callgrind/jumps.c b/callgrind/jumps.c index ad01254905..5a0d32e9e4 100644 --- a/callgrind/jumps.c +++ b/callgrind/jumps.c @@ -155,7 +155,7 @@ static jCC* new_jcc(BBCC* from, UInt jmp, BBCC* to) if (from) { /* Prohibit corruption by array overrun */ - CLG_ASSERT((0 <= jmp) && (jmp <= from->bb->cjmp_count)); + CLG_ASSERT(jmp <= from->bb->cjmp_count); jcc->next_from = from->jmp[jmp].jcc_list; from->jmp[jmp].jcc_list = jcc; } diff --git a/coregrind/m_debuginfo/image.c b/coregrind/m_debuginfo/image.c index 5c9d722467..70c3bd859a 100644 --- a/coregrind/m_debuginfo/image.c +++ b/coregrind/m_debuginfo/image.c @@ -1322,7 +1322,7 @@ UInt ML_(img_calc_gnu_debuglink_crc32)(DiImage* img) DiOffT img_szB = ML_(img_size)(img); DiOffT curr_off = 0; while (1) { - vg_assert(curr_off >= 0 && curr_off <= img_szB); + vg_assert(curr_off <= img_szB); if (curr_off == img_szB) break; DiOffT avail = img_szB - curr_off; vg_assert(avail > 0 && avail <= img_szB); diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c index 80c4b77bb5..ace485c157 100644 --- a/coregrind/m_debuginfo/storage.c +++ b/coregrind/m_debuginfo/storage.c @@ -748,7 +748,7 @@ DiCfSI_m* ML_(get_cfsi_m) (const DebugInfo* di, UInt pos) { UInt cfsi_m_ix; - vg_assert(pos >= 0 && pos < di->cfsi_used); + vg_assert(pos < di->cfsi_used); switch (di->sizeof_cfsi_m_ix) { case 1: cfsi_m_ix = ((UChar*) di->cfsi_m_ix)[pos]; break; case 2: cfsi_m_ix = ((UShort*) di->cfsi_m_ix)[pos]; break; diff --git a/coregrind/m_execontext.c b/coregrind/m_execontext.c index 227c3c3dc7..9305f316ef 100644 --- a/coregrind/m_execontext.c +++ b/coregrind/m_execontext.c @@ -352,7 +352,7 @@ static void resize_ec_htab ( void ) SizeT new_size; ExeContext** new_ec_htab; - vg_assert(ec_htab_size_idx >= 0 && ec_htab_size_idx < N_EC_PRIMES); + vg_assert(ec_htab_size_idx < N_EC_PRIMES); if (ec_htab_size_idx == N_EC_PRIMES-1) return; /* out of primes - can't resize further */ diff --git a/coregrind/m_main.c b/coregrind/m_main.c index 9087aafb02..1cedaaf2e3 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -1945,7 +1945,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) //-------------------------------------------------------------- VG_(debugLog)(1, "main", "Initialise scheduler (phase 1)\n"); tid_main = VG_(scheduler_init_phase1)(); - vg_assert(tid_main >= 0 && tid_main < VG_N_THREADS + vg_assert(tid_main < VG_N_THREADS && tid_main != VG_INVALID_THREADID); /* Tell the tool about tid_main */ VG_TRACK( pre_thread_ll_create, VG_INVALID_THREADID, tid_main ); diff --git a/coregrind/m_mallocfree.c b/coregrind/m_mallocfree.c index 44beb3d8b5..96104c8d57 100644 --- a/coregrind/m_mallocfree.c +++ b/coregrind/m_mallocfree.c @@ -971,7 +971,7 @@ Superblock* findSb ( Arena* a, Block* b ) Superblock * sb; SizeT pos = min + (max - min)/2; - vg_assert(pos >= 0 && pos < a->sblocks_used); + vg_assert(pos < a->sblocks_used); sb = a->sblocks[pos]; if ((Block*)&sb->payload_bytes[0] <= b && b < (Block*)&sb->payload_bytes[sb->n_payload_bytes]) diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c index 3062c1afc3..f8b3b46c1e 100644 --- a/coregrind/m_scheduler/scheduler.c +++ b/coregrind/m_scheduler/scheduler.c @@ -595,7 +595,7 @@ void mostly_clear_thread_record ( ThreadId tid ) { vki_sigset_t savedmask; - vg_assert(tid >= 0 && tid < VG_N_THREADS); + vg_assert(tid < VG_N_THREADS); VG_(cleanup_thread)(&VG_(threads)[tid].arch); VG_(threads)[tid].tid = tid; diff --git a/coregrind/m_seqmatch.c b/coregrind/m_seqmatch.c index 06151ee0f8..09abbca092 100644 --- a/coregrind/m_seqmatch.c +++ b/coregrind/m_seqmatch.c @@ -65,11 +65,10 @@ Bool VG_(generic_match) ( Bool havePatt, haveInput; const HChar *currPatt, *currInput; tailcall: - vg_assert(nPatt >= 0 && nPatt < 1000000); /* arbitrary */ - vg_assert(inputCompleter - || (nInput >= 0 && nInput < 1000000)); /* arbitrary */ - vg_assert(ixPatt >= 0 && ixPatt <= nPatt); - vg_assert(ixInput >= 0 && (inputCompleter || ixInput <= nInput)); + vg_assert(nPatt < 1000000); /* arbitrary */ + vg_assert(inputCompleter || (nInput < 1000000)); /* arbitrary */ + vg_assert(ixPatt <= nPatt); + vg_assert(inputCompleter || ixInput <= nInput); havePatt = ixPatt < nPatt; haveInput = inputCompleter ? diff --git a/coregrind/m_threadstate.c b/coregrind/m_threadstate.c index 6cb6941e4d..85ae03569d 100644 --- a/coregrind/m_threadstate.c +++ b/coregrind/m_threadstate.c @@ -97,7 +97,7 @@ const HChar* VG_(name_of_VgSchedReturnCode) ( VgSchedReturnCode retcode ) ThreadState *VG_(get_ThreadState)(ThreadId tid) { - vg_assert(tid >= 0 && tid < VG_N_THREADS); + vg_assert(tid < VG_N_THREADS); vg_assert(VG_(threads)[tid].tid == tid); return &VG_(threads)[tid]; } diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c index 8ae06d2a67..0dd36082d2 100644 --- a/coregrind/m_translate.c +++ b/coregrind/m_translate.c @@ -1831,7 +1831,7 @@ Bool VG_(translate) ( ThreadId tid, tres = LibVEX_Translate ( &vta ); vg_assert(tres.status == VexTransOK); - vg_assert(tres.n_sc_extents >= 0 && tres.n_sc_extents <= 3); + vg_assert(tres.n_sc_extents <= 3); vg_assert(tmpbuf_used <= N_TMPBUF); vg_assert(tmpbuf_used > 0); diff --git a/coregrind/m_transtab.c b/coregrind/m_transtab.c index ff5b35b53a..789a169dcd 100644 --- a/coregrind/m_transtab.c +++ b/coregrind/m_transtab.c @@ -1850,7 +1850,7 @@ void VG_(add_to_transtab)( const VexGuestExtents* vge, // Point an htt entry to the tt slot HTTno htti = HASH_TT(entry); - vg_assert(htti >= 0 && htti < N_HTTES_PER_SECTOR); + vg_assert(htti < N_HTTES_PER_SECTOR); while (True) { if (sectors[y].htt[htti] == HTT_EMPTY || sectors[y].htt[htti] == HTT_DELETED) @@ -1925,7 +1925,7 @@ Bool VG_(search_transtab) ( /*OUT*/Addr* res_hcode, all sectors and avoids multiple expensive % operations. */ n_full_lookups++; kstart = HASH_TT(guest_addr); - vg_assert(kstart >= 0 && kstart < N_HTTES_PER_SECTOR); + vg_assert(kstart < N_HTTES_PER_SECTOR); /* Search in all the sectors,using sector_search_order[] as a heuristic guide as to what order to visit the sectors. */ diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c index 45e6388b65..a31aacf5c7 100644 --- a/helgrind/hg_main.c +++ b/helgrind/hg_main.c @@ -3625,9 +3625,9 @@ static void univ_laog_do_GC ( void ) { links = NULL; while (VG_(nextIterFM)( laog, NULL, (UWord*)&links )) { tl_assert(links); - tl_assert(links->inns >= 0 && links->inns < univ_laog_cardinality); + tl_assert(links->inns < univ_laog_cardinality); univ_laog_seen[links->inns] = True; - tl_assert(links->outs >= 0 && links->outs < univ_laog_cardinality); + tl_assert(links->outs < univ_laog_cardinality); univ_laog_seen[links->outs] = True; links = NULL; } diff --git a/helgrind/hg_wordset.c b/helgrind/hg_wordset.c index 34978ffc5f..3b780262a6 100644 --- a/helgrind/hg_wordset.c +++ b/helgrind/hg_wordset.c @@ -420,7 +420,6 @@ UWord HG_(cardinalityWS) ( WordSetU* wsu, WordSet ws ) WordVec* wv; tl_assert(wsu); wv = do_ix2vec( wsu, ws ); - tl_assert(wv->size >= 0); return wv->size; } @@ -447,7 +446,6 @@ void HG_(getPayloadWS) ( /*OUT*/UWord** words, /*OUT*/UWord* nWords, if (HG_DEBUG) VG_(printf)("getPayloadWS %s %d\n", wsu->cc, (Int)ws); tl_assert(wsu); wv = do_ix2vec( wsu, ws ); - tl_assert(wv->size >= 0); *nWords = wv->size; *words = wv->words; } diff --git a/helgrind/libhb_core.c b/helgrind/libhb_core.c index 2acf3fbd83..101624028f 100644 --- a/helgrind/libhb_core.c +++ b/helgrind/libhb_core.c @@ -1511,7 +1511,7 @@ static __attribute__((noinline)) void cacheline_wback ( UWord wix ) if (0) VG_(printf)("scache wback line %d\n", (Int)wix); - tl_assert(wix >= 0 && wix < N_WAY_NENT); + tl_assert(wix < N_WAY_NENT); tag = cache_shmem.tags0[wix]; cl = &cache_shmem.lyns0[wix]; @@ -1650,7 +1650,7 @@ static __attribute__((noinline)) void cacheline_fetch ( UWord wix ) if (0) VG_(printf)("scache fetch line %d\n", (Int)wix); - tl_assert(wix >= 0 && wix < N_WAY_NENT); + tl_assert(wix < N_WAY_NENT); tag = cache_shmem.tags0[wix]; cl = &cache_shmem.lyns0[wix]; @@ -5338,7 +5338,7 @@ static void record_race_info ( Thr* acc_thr, tl_assert(acc_thr); tl_assert(acc_thr->hgthread); tl_assert(acc_thr->hgthread->hbthr == acc_thr); - tl_assert(HG_(clo_history_level) >= 0 && HG_(clo_history_level) <= 2); + tl_assert(HG_(clo_history_level) <= 2); if (HG_(clo_history_level) == 1) { Bool found; @@ -5941,6 +5941,7 @@ static void zsm_swrite64 ( Addr a, SVal svNew ) { CacheLine* cl; UWord cloff, tno; + SizeT i; //UWord toff; stats__cline_swrite64s++; if (UNLIKELY(!aligned64(a))) goto slowcase; diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 2221f8d3d8..e6e9ef80aa 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -3711,7 +3711,7 @@ static inline UInt convert_nia_to_ecu ( Addr nia ) stats__nia_cache_queries++; i = nia % N_NIA_TO_ECU_CACHE; - tl_assert(i >= 0 && i < N_NIA_TO_ECU_CACHE); + tl_assert(i < N_NIA_TO_ECU_CACHE); if (LIKELY( nia_to_ecu_cache[i].nia0 == nia )) return nia_to_ecu_cache[i].ecu0; -- 2.43.5