From 206e26383677409c823e9bef5cfac954347dbe8a Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 22 Aug 2011 15:25:10 +0000 Subject: [PATCH] Move cpu files from cgen/cpu to top level cpu directory. --- ChangeLog | 24 + cpu/fr30.cpu | 1844 ------- cpu/fr30.opc | 235 - cpu/ip2k.cpu | 1464 ------ cpu/ip2k.opc | 616 --- cpu/mep-avc.cpu | 1406 ------ cpu/mep-avc2.cpu | 1970 -------- cpu/mep-c5.cpu | 260 - cpu/mep-core.cpu | 3065 ------------ cpu/mep-default.cpu | 10 - cpu/mep-ext-cop.cpu | 8 - cpu/mep-fmax.cpu | 323 -- cpu/mep-h1.cpu | 28 - cpu/mep-ivc2.cpu | 9761 ------------------------------------- cpu/mep-rhcop.cpu | 321 -- cpu/mep-sample-ucidsp.cpu | 103 - cpu/mep.cpu | 1 - cpu/mep.opc | 1653 ------- cpu/openrisc.cpu | 775 --- cpu/openrisc.opc | 147 - cpu/xstormy16.cpu | 1948 -------- cpu/xstormy16.opc | 150 - 22 files changed, 24 insertions(+), 26088 deletions(-) delete mode 100644 cpu/fr30.cpu delete mode 100644 cpu/fr30.opc delete mode 100644 cpu/ip2k.cpu delete mode 100644 cpu/ip2k.opc delete mode 100644 cpu/mep-avc.cpu delete mode 100644 cpu/mep-avc2.cpu delete mode 100644 cpu/mep-c5.cpu delete mode 100644 cpu/mep-core.cpu delete mode 100644 cpu/mep-default.cpu delete mode 100644 cpu/mep-ext-cop.cpu delete mode 100644 cpu/mep-fmax.cpu delete mode 100644 cpu/mep-h1.cpu delete mode 100644 cpu/mep-ivc2.cpu delete mode 100644 cpu/mep-rhcop.cpu delete mode 100644 cpu/mep-sample-ucidsp.cpu delete mode 100644 cpu/mep.cpu delete mode 100644 cpu/mep.opc delete mode 100644 cpu/openrisc.cpu delete mode 100644 cpu/openrisc.opc delete mode 100644 cpu/xstormy16.cpu delete mode 100644 cpu/xstormy16.opc diff --git a/ChangeLog b/ChangeLog index 6221354..9555898 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,27 @@ +2011-08-22 Nick Clifton + + * cpu/fr30.cpu: Delete. Move to top level cpu directory. + * cpu/fr30.opc: Likewise. + * cpu/ip2k.cpu: Likewise. + * cpu/ip2k.opc: Likewise. + * cpu/mep-avc.cpu: Likewise. + * cpu/mep-avc2.cpu: Likewise. + * cpu/mep-c5.cpu: Likewise. + * cpu/mep-core.cpu: Likewise. + * cpu/mep-default.cpu: Likewise. + * cpu/mep-ext-cop.cpu: Likewise. + * cpu/mep-fmax.cpu: Likewise. + * cpu/mep-h1.cpu: Likewise. + * cpu/mep-ivc2.cpu: Likewise. + * cpu/mep-rhcop.cpu: Likewise. + * cpu/mep-sample-ucidsp.cpu: Likewise. + * cpu/mep.cpu: Likewise. + * cpu/mep.opc: Likewise. + * cpu/openrisc.cpu: Likewise. + * cpu/openrisc.opc: Likewise. + * cpu/xstormy16.cpu: Likewise. + * cpu/xstormy16.opc: Likewise. + 2010-10-28 Nick Clifton * cpu/xstormy16.cpu (alignfix-mem-far): New macro. Like diff --git a/cpu/fr30.cpu b/cpu/fr30.cpu deleted file mode 100644 index b3627a1..0000000 --- a/cpu/fr30.cpu +++ /dev/null @@ -1,1844 +0,0 @@ -; Fujitsu FR30 CPU description. -*- Scheme -*- -; Copyright (C) 2000, 2009 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -; define-arch must appear first - -(define-arch - (name fr30) ; name of cpu family - (comment "Fujitsu FR30") - (default-alignment forced) - (insn-lsb0? #f) - (machs fr30) - (isas fr30) -) - -(define-isa - (name fr30) - (base-insn-bitsize 16) - (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. - (liw-insns 1) ; The fr30 fetches 1 insn at a time. - (parallel-insns 1) ; The fr30 executes 1 insn at a time. -) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name fr30bf) - (comment "Fujitsu FR30 base family") - (endian big) - (word-bitsize 32) -) - -(define-mach - (name fr30) - (comment "Generic FR30 cpu") - (cpu fr30bf) -) - -; Model descriptions. -; -(define-model - (name fr30-1) (comment "fr30-1") (attrs) - (mach fr30) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; bit mask of h-gr registers loaded from memory by previous insn - (load-regs UINT) - ; bit mask of h-gr registers loaded from memory by current insn - (load-regs-pending UINT) - ) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1) (Rj INT -1)) ; inputs - ((Ri INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cti "Branch Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-load "Memory Load Unit" () - 1 1 ; issue done - () ; state - ((Rj INT -1) - ;(ld-mem AI) - ) ; inputs - ((Ri INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-store "Memory Store Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1) (Rj INT -1)) ; inputs - () ; ((st-mem AI)) ; outputs - () ; profile action (default) - ) - (unit u-ldm "LDM Memory Load Unit" () - 1 1 ; issue done - () ; state - ((reglist INT)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-stm "STM Memory Store Unit" () - 1 1 ; issue done - () ; state - ((reglist INT)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; The instruction fetch/execute cycle. -; -; This is how to fetch and decode an instruction. -; Leave it out for now - -; (define-extract (const SI 0)) - -; This is how to execute a decoded instruction. -; Leave it out for now - -; (define-execute (const SI 0)) - -; Instruction fields. -; -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 - -(dnf f-op1 "1st 4 bits of opcode" () 0 4) -(dnf f-op2 "2nd 4 bits of opcode" () 4 4) -(dnf f-op3 "3rd 4 bits of opcode" () 8 4) -(dnf f-op4 "4th 4 bits of opcode" () 12 4) -(dnf f-op5 "5th bit of opcode" () 4 1) -(dnf f-cc "condition code" () 4 4) -(dnf f-ccc "coprocessor calc code" () 16 8) -(dnf f-Rj "register Rj" () 8 4) -(dnf f-Ri "register Ri" () 12 4) -(dnf f-Rs1 "register Rs" () 8 4) -(dnf f-Rs2 "register Rs" () 12 4) -(dnf f-Rjc "register Rj" () 24 4) -(dnf f-Ric "register Ri" () 28 4) -(dnf f-CRj "coprocessor register" () 24 4) -(dnf f-CRi "coprocessor register" () 28 4) -(dnf f-u4 "4 bit 0 extended" () 8 4) -(dnf f-u4c "4 bit 0 extended" () 12 4) -(df f-i4 "4 bit sign extended" () 8 4 INT #f #f) -(df f-m4 "4 bit minus extended" () 8 4 UINT - ((value pc) (and WI value (const #xf))) - ; ??? On a 64 bit host this doesn't get completely sign extended - ; if the value is recorded in a long, as it is during extraction. - ; Various fixes exist, pick one. - ((value pc) (or WI value (sll WI (const -1) (const 4)))) -) -(dnf f-u8 "8 bit unsigned" () 8 8) -(dnf f-i8 "8 bit unsigned" () 4 8) - -(dnf f-i20-4 "upper 4 bits of i20" () 8 4) -(dnf f-i20-16 "lower 16 bits of i20" () 16 16) -(dnmf f-i20 "20 bit unsigned" () UINT - (f-i20-4 f-i20-16) - (sequence () ; insert - (set (ifield f-i20-4) (srl (ifield f-i20) (const 16))) - (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff))) - ) - (sequence () ; extract - (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16)) - (ifield f-i20-16))) - ) -) - -(dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32) - -(df f-udisp6 "6 bit unsigned offset" () 8 4 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-disp8 "8 bit signed offset" () 4 8 INT #f #f) -(df f-disp9 "9 bit signed offset" () 4 8 INT - ((value pc) (sra WI value (const 1))) - ((value pc) (sll WI value (const 1))) -) -(df f-disp10 "10 bit signed offset" () 4 8 INT - ((value pc) (sra WI value (const 2))) - ((value pc) (sll WI value (const 2))) -) -(df f-s10 "10 bit signed offset" () 8 8 INT - ((value pc) (sra WI value (const 2))) - ((value pc) (sll WI value (const 2))) -) -(df f-u10 "10 bit unsigned offset" () 8 8 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT - ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) - ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) -) -(dnf f-dir8 "8 bit direct address" () 8 8) -(df f-dir9 "9 bit direct address" () 8 8 UINT - ((value pc) (srl UWI value (const 1))) - ((value pc) (sll UWI value (const 1))) -) -(df f-dir10 "10 bit direct address" () 8 8 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT - ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) - ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) -) - -(dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8) -(dnf f-reglist_low_st "8 bit register mask for stm" () 8 8) -(dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8) -(dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8) - -; Enums. - -; insn-op1: bits 0-3 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op2: bits 4-7 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op3: bits 8-11 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op4: bits 12-15 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4 - ("0") -) - -; insn-op5: bit 4 (5th bit origin 0) -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5 - ("0" "1") -) - -; insn-cc: condition codes -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc - ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi") -) - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(define-keyword - (name gr-names) - (enum-prefix H-GR-) - (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) - (ac 13) (fp 14) (sp 15)) -) - -(define-hardware - (name h-gr) - (comment "general registers") - (attrs PROFILE CACHE-ADDR) - (type register WI (16)) - (indices extern-keyword gr-names) -) - -(define-keyword - (name cr-names) - (enum-prefix H-CR-) - (values (cr0 0) (cr1 1) (cr2 2) (cr3 3) - (cr4 4) (cr5 5) (cr6 6) (cr7 7) - (cr8 8) (cr9 9) (cr10 10) (cr11 11) - (cr12 12) (cr13 13) (cr14 14) (cr15 15)) -) - -(define-hardware - (name h-cr) - (comment "coprocessor registers") - (attrs) - (type register WI (16)) - (indices extern-keyword cr-names) -) - -(define-keyword - (name dr-names) - (enum-prefix H-DR-) - (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5)) -) - -(define-hardware - (name h-dr) - (comment "dedicated registers") - (type register WI (6)) - (indices extern-keyword dr-names) - (get (index) (c-call WI "@cpu@_h_dr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval)) -) - -(define-hardware - (name h-ps) - (comment "processor status") - (type register UWI) - (indices keyword "" ((ps 0))) - (get () (c-call UWI "@cpu@_h_ps_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval)) -) - -(dnh h-r13 "General Register 13 explicitly required" - () - (register WI) - (keyword "" ((r13 0))) - () () -) - -(dnh h-r14 "General Register 14 explicitly required" - () - (register WI) - (keyword "" ((r14 0))) - () () -) - -(dnh h-r15 "General Register 15 explicitly required" - () - (register WI) - (keyword "" ((r15 0))) - () () -) - -; These bits are actually part of the PS register but are accessed more -; often than the entire register, so define them directly. We can assemble -; the PS register from its components when necessary. - -(dsh h-nbit "negative bit" () (register BI)) -(dsh h-zbit "zero bit" () (register BI)) -(dsh h-vbit "overflow bit" () (register BI)) -(dsh h-cbit "carry bit" () (register BI)) -(dsh h-ibit "interrupt enable bit" () (register BI)) -(define-hardware - (name h-sbit) - (comment "stack bit") - (type register BI) - (get () (c-call BI "@cpu@_h_sbit_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval)) -) -(dsh h-tbit "trace trap bit" () (register BI)) -(dsh h-d0bit "division 0 bit" () (register BI)) -(dsh h-d1bit "division 1 bit" () (register BI)) - -; These represent sub-registers within the program status register - -(define-hardware - (name h-ccr) - (comment "condition code bits") - (type register UQI) - (get () (c-call UQI "@cpu@_h_ccr_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval)) -) -(define-hardware - (name h-scr) - (comment "system condition bits") - (type register UQI) - (get () (c-call UQI "@cpu@_h_scr_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval)) -) -(define-hardware - (name h-ilm) - (comment "interrupt level mask") - (type register UQI) - (get () (c-call UQI "@cpu@_h_ilm_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval)) -) - -; Instruction Operands. -; These entries provide a layer between the assembler and the raw hardware -; description, and are used to refer to hardware elements in the semantic -; code. Usually there's a bit of over-specification, but in more complicated -; instruction sets there isn't. - -; FR30 specific operand attributes: - -(define-attr - (for operand) - (type boolean) - (name HASH-PREFIX) - (comment "immediates have an optional '#' prefix") -) - -; ??? Convention says this should be o-sr, but then the insn definitions -; should refer to o-sr which is clumsy. The "o-" could be implicit, but -; then it should be implicit for all the symbols here, but then there would -; be confusion between (f-)simm8 and (h-)simm8. -; So for now the rule is exactly as it appears here. - -(dnop Ri "destination register" () h-gr f-Ri) -(dnop Rj "source register" () h-gr f-Rj) -(dnop Ric "target register coproc insn" () h-gr f-Ric) -(dnop Rjc "source register coproc insn" () h-gr f-Rjc) -(dnop CRi "coprocessor register" () h-cr f-CRi) -(dnop CRj "coprocessor register" () h-cr f-CRj) -(dnop Rs1 "dedicated register" () h-dr f-Rs1) -(dnop Rs2 "dedicated register" () h-dr f-Rs2) -(dnop R13 "General Register 13" () h-r13 f-nil) -(dnop R14 "General Register 14" () h-r14 f-nil) -(dnop R15 "General Register 15" () h-r15 f-nil) -(dnop ps "Program Status register" () h-ps f-nil) -(dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4) -(dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c) -(dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8) -(dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8) -(dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6) -(dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8) -(dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9) -(dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10) - -(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) -(dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10) -(dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32) - -(define-operand - (name m4) - (comment "4 bit negative immediate") - (attrs HASH-PREFIX) - (type h-sint) - (index f-m4) - (handlers (print "m4")) -) - -(define-operand - (name i20) - (comment "20 bit immediate") - (attrs HASH-PREFIX) - (type h-uint) - (index f-i20) -) - -(dnop dir8 "8 bit direct address" () h-uint f-dir8) -(dnop dir9 "9 bit direct address" () h-uint f-dir9) -(dnop dir10 "10 bit direct address" () h-uint f-dir10) - -(dnop label9 "9 bit pc relative address" () h-iaddr f-rel9) -(dnop label12 "12 bit pc relative address" () h-iaddr f-rel12) - -(define-operand - (name reglist_low_ld) - (comment "8 bit low register mask for ldm") - (attrs) - (type h-uint) - (index f-reglist_low_ld) - (handlers (parse "low_register_list_ld") - (print "low_register_list_ld")) -) - -(define-operand - (name reglist_hi_ld) - (comment "8 bit high register mask for ldm") - (attrs) - (type h-uint) - (index f-reglist_hi_ld) - (handlers (parse "hi_register_list_ld") - (print "hi_register_list_ld")) -) - -(define-operand - (name reglist_low_st) - (comment "8 bit low register mask for stm") - (attrs) - (type h-uint) - (index f-reglist_low_st) - (handlers (parse "low_register_list_st") - (print "low_register_list_st")) -) - -(define-operand - (name reglist_hi_st) - (comment "8 bit high register mask for stm") - (attrs) - (type h-uint) - (index f-reglist_hi_st) - (handlers (parse "hi_register_list_st") - (print "hi_register_list_st")) -) - -(dnop cc "condition codes" () h-uint f-cc) -(dnop ccc "coprocessor calc" (HASH-PREFIX) h-uint f-ccc) - -(dnop nbit "negative bit" (SEM-ONLY) h-nbit f-nil) -(dnop vbit "overflow bit" (SEM-ONLY) h-vbit f-nil) -(dnop zbit "zero bit" (SEM-ONLY) h-zbit f-nil) -(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil) -(dnop ibit "interrupt bit" (SEM-ONLY) h-ibit f-nil) -(dnop sbit "stack bit" (SEM-ONLY) h-sbit f-nil) -(dnop tbit "trace trap bit" (SEM-ONLY) h-tbit f-nil) -(dnop d0bit "division 0 bit" (SEM-ONLY) h-d0bit f-nil) -(dnop d1bit "division 1 bit" (SEM-ONLY) h-d1bit f-nil) - -(dnop ccr "condition code bits" (SEM-ONLY) h-ccr f-nil) -(dnop scr "system condition bits" (SEM-ONLY) h-scr f-nil) -(dnop ilm "interrupt level mask" (SEM-ONLY) h-ilm f-nil) - -; Instruction definitions. -; -; Notes: -; - dni is short for "define-normal-instruction" - -; FR30 specific insn attributes: - -(define-attr - (for insn) - (type boolean) - (name NOT-IN-DELAY-SLOT) - (comment "insn can't go in delay slot") -) - -; Sets zbit and nbit based on the value of x -; -(define-pmacro (set-z-and-n x) - (sequence () - (set zbit (eq x (const 0))) - (set nbit (lt x (const 0)))) -) - -; Binary integer instruction which sets status bits -; -(define-pmacro (binary-int-op name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence () - (set vbit ((.sym op -oflag) arg2 arg1 (const 0))) - (set cbit ((.sym op -cflag) arg2 arg1 (const 0))) - (set arg2 (op arg2 arg1)) - (set-z-and-n arg2)) - () - ) -) - -; Binary integer instruction which does *not* set status bits -; -(define-pmacro (binary-int-op-n name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (op arg2 arg1)) - () - ) -) - -; Binary integer instruction with carry which sets status bits -; -(define-pmacro (binary-int-op-c name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI tmp)) - (set tmp ((.sym op c) arg2 arg1 cbit)) - (set vbit ((.sym op -oflag) arg2 arg1 cbit)) - (set cbit ((.sym op -cflag) arg2 arg1 cbit)) - (set arg2 tmp) - (set-z-and-n arg2)) - () - ) -) - -(binary-int-op add add "reg/reg" OP1_A OP2_6 add Rj Ri) -(binary-int-op addi add "immed/reg" OP1_A OP2_4 add u4 Ri) -(binary-int-op add2 add2 "immed/reg" OP1_A OP2_5 add m4 Ri) -(binary-int-op-c addc addc "reg/reg" OP1_A OP2_7 add Rj Ri) -(binary-int-op-n addn addn "reg/reg" OP1_A OP2_2 add Rj Ri) -(binary-int-op-n addni addn "immed/reg" OP1_A OP2_0 add u4 Ri) -(binary-int-op-n addn2 addn2 "immed/reg" OP1_A OP2_1 add m4 Ri) - -(binary-int-op sub sub "reg/reg" OP1_A OP2_C sub Rj Ri) -(binary-int-op-c subc subc "reg/reg" OP1_A OP2_D sub Rj Ri) -(binary-int-op-n subn subn "reg/reg" OP1_A OP2_E sub Rj Ri) - -; Integer compare instruction -; -(define-pmacro (int-cmp name insn comment opc1 opc2 arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI tmp1)) - (set vbit (sub-oflag arg2 arg1 (const 0))) - (set cbit (sub-cflag arg2 arg1 (const 0))) - (set tmp1 (sub arg2 arg1)) - (set-z-and-n tmp1) - ) - () - ) -) - -(int-cmp cmp cmp "reg/reg" OP1_A OP2_A Rj Ri) -(int-cmp cmpi cmp "immed/reg" OP1_A OP2_8 u4 Ri) -(int-cmp cmp2 cmp2 "immed/reg" OP1_A OP2_9 m4 Ri) - -; Binary logical instruction -; -(define-pmacro (binary-logical-op name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence () - (set arg2 (op arg2 arg1)) - (set-z-and-n arg2)) - () - ) -) - -(binary-logical-op and and "reg/reg" OP1_8 OP2_2 and Rj Ri) -(binary-logical-op or or "reg/reg" OP1_9 OP2_2 or Rj Ri) -(binary-logical-op eor eor "reg/reg" OP1_9 OP2_A xor Rj Ri) - -(define-pmacro (les-units model) ; les: load-exec-store - (model (unit u-exec) (unit u-load) (unit u-store)) -) - -; Binary logical instruction to memory -; -(define-pmacro (binary-logical-op-m name insn comment opc1 opc2 mode op arg1 arg2) - (dni name - (.str insn " " comment) - (NOT-IN-DELAY-SLOT) - (.str insn " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((mode tmp)) - (set mode tmp (op mode (mem mode arg2) arg1)) - (set-z-and-n tmp) - (set mode (mem mode arg2) tmp)) - ((les-units fr30-1)) - ) -) - -(binary-logical-op-m andm and "reg/mem" OP1_8 OP2_4 WI and Rj Ri) -(binary-logical-op-m andh andh "reg/mem" OP1_8 OP2_5 HI and Rj Ri) -(binary-logical-op-m andb andb "reg/mem" OP1_8 OP2_6 QI and Rj Ri) -(binary-logical-op-m orm or "reg/mem" OP1_9 OP2_4 WI or Rj Ri) -(binary-logical-op-m orh orh "reg/mem" OP1_9 OP2_5 HI or Rj Ri) -(binary-logical-op-m orb orb "reg/mem" OP1_9 OP2_6 QI or Rj Ri) -(binary-logical-op-m eorm eor "reg/mem" OP1_9 OP2_C WI xor Rj Ri) -(binary-logical-op-m eorh eorh "reg/mem" OP1_9 OP2_D HI xor Rj Ri) -(binary-logical-op-m eorb eorb "reg/mem" OP1_9 OP2_E QI xor Rj Ri) - -; Binary logical instruction to low half of byte in memory -; -(dni bandl - "bandl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "bandl $u4,@$Ri" - (+ OP1_8 OP2_0 u4 Ri) - (set QI (mem QI Ri) - (and QI - (or QI u4 (const #xf0)) - (mem QI Ri))) - ((les-units fr30-1)) -) - -(dni borl - "borl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "borl $u4,@$Ri" - (+ OP1_9 OP2_0 u4 Ri) - (set QI (mem QI Ri) (or QI u4 (mem QI Ri))) - ((les-units fr30-1)) -) - -(dni beorl - "beorl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "beorl $u4,@$Ri" - (+ OP1_9 OP2_8 u4 Ri) - (set QI (mem QI Ri) (xor QI u4 (mem QI Ri))) - ((les-units fr30-1)) -) - -; Binary logical instruction to high half of byte in memory -; -(dni bandh - "bandh #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "bandh $u4,@$Ri" - (+ OP1_8 OP2_1 u4 Ri) - (set QI (mem QI Ri) - (and QI - (or QI (sll QI u4 (const 4)) (const #x0f)) - (mem QI Ri))) - ((les-units fr30-1)) -) - -(define-pmacro (binary-or-op-mh name insn opc1 opc2 op arg1 arg2) - (dni name - (.str name " #" arg1 ",@" args) - (NOT-IN-DELAY-SLOT) - (.str name " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (set QI (mem QI arg2) - (insn QI - (sll QI arg1 (const 4)) - (mem QI arg2))) - ((les-units fr30-1)) - ) -) - -(binary-or-op-mh borh or OP1_9 OP2_1 or u4 Ri) -(binary-or-op-mh beorh xor OP1_9 OP2_9 xor u4 Ri) - -(dni btstl - "btstl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "btstl $u4,@$Ri" - (+ OP1_8 OP2_8 u4 Ri) - (sequence ((QI tmp)) - (set tmp (and QI u4 (mem QI Ri))) - (set zbit (eq tmp (const 0))) - (set nbit (const 0))) - ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) -) - -(dni btsth - "btsth #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "btsth $u4,@$Ri" - (+ OP1_8 OP2_9 u4 Ri) - (sequence ((QI tmp)) - (set tmp (and QI (sll QI u4 (const 4)) (mem QI Ri))) - (set zbit (eq tmp (const 0))) - (set nbit (lt tmp (const 0)))) - ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) -) - -(dni mul - "mul Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mul $Rj,$Ri" - (+ OP1_A OP2_F Rj Ri) - (sequence ((DI tmp)) - (set tmp (mul DI (ext DI Rj) (ext DI Ri))) - (set (reg h-dr 5) (trunc WI tmp)) - (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (eq tmp (const DI 0))) - (set vbit (orif - (gt tmp (const DI #x7fffffff)) - (lt tmp (neg (const DI #x80000000)))))) - ((fr30-1 (unit u-exec (cycles 5)))) -) - -(dni mulu - "mulu Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mulu $Rj,$Ri" - (+ OP1_A OP2_B Rj Ri) - (sequence ((DI tmp)) - (set tmp (mul DI (zext DI Rj) (zext DI Ri))) - (set (reg h-dr 5) (trunc WI tmp)) - (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) - (set nbit (lt (reg h-dr 4) (const 0))) - (set zbit (eq (reg h-dr 5) (const 0))) - (set vbit (ne (reg h-dr 4) (const 0)))) - ((fr30-1 (unit u-exec (cycles 5)))) -) - -(dni mulh - "mulh Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mulh $Rj,$Ri" - (+ OP1_B OP2_F Rj Ri) - (sequence () - (set (reg h-dr 5) (mul (trunc HI Rj) (trunc HI Ri))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (ge (reg h-dr 5) (const 0)))) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -(dni muluh - "muluh Rj,Ri" - (NOT-IN-DELAY-SLOT) - "muluh $Rj,$Ri" - (+ OP1_B OP2_B Rj Ri) - (sequence () - (set (reg h-dr 5) (mul (and Rj (const #xffff)) - (and Ri (const #xffff)))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (ge (reg h-dr 5) (const 0)))) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -(dni div0s - "div0s Ri" - () - "div0s $Ri" - (+ OP1_9 OP2_7 OP3_4 Ri) - (sequence () - (set d0bit (lt (reg h-dr 5) (const 0))) - (set d1bit (xor d0bit (lt Ri (const 0)))) - (if (ne d0bit (const 0)) - (set (reg h-dr 4) (const #xffffffff)) - (set (reg h-dr 4) (const 0)))) - () -) - -(dni div0u - "div0u Ri" - () - "div0u $Ri" - (+ OP1_9 OP2_7 OP3_5 Ri) - (sequence () - (set d0bit (const 0)) - (set d1bit (const 0)) - (set (reg h-dr 4) (const 0))) - () -) - -(dni div1 - "div1 Ri" - () - "div1 $Ri" - (+ OP1_9 OP2_7 OP3_6 Ri) - (sequence ((WI tmp)) - (set (reg h-dr 4) (sll (reg h-dr 4) (const 1))) - (if (lt (reg h-dr 5) (const 0)) - (set (reg h-dr 4) (add (reg h-dr 4) (const 1)))) - (set (reg h-dr 5) (sll (reg h-dr 5) (const 1))) - (if (eq d1bit (const 1)) - (sequence () - (set tmp (add (reg h-dr 4) Ri)) - (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) - (sequence () - (set tmp (sub (reg h-dr 4) Ri)) - (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) - (if (not (xor (xor d0bit d1bit) cbit)) - (sequence () - (set (reg h-dr 4) tmp) - (set (reg h-dr 5) (or (reg h-dr 5) (const 1))))) - (set zbit (eq (reg h-dr 4) (const 0)))) - () -) - -(dni div2 - "div2 Ri" - () - "div2 $Ri" - (+ OP1_9 OP2_7 OP3_7 Ri) - (sequence ((WI tmp)) - (if (eq d1bit (const 1)) - (sequence () - (set tmp (add (reg h-dr 4) Ri)) - (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) - (sequence () - (set tmp (sub (reg h-dr 4) Ri)) - (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) - (if (eq tmp (const 0)) - (sequence () - (set zbit (const 1)) - (set (reg h-dr 4) (const 0))) - (set zbit (const 0)))) - () -) - -(dni div3 - "div3" - () - "div3" - (+ OP1_9 OP2_F OP3_6 OP4_0) - (if (eq zbit (const 1)) - (set (reg h-dr 5) (add (reg h-dr 5) (const 1)))) - () -) - -(dni div4s - "div4s" - () - "div4s" - (+ OP1_9 OP2_F OP3_7 OP4_0) - (if (eq d1bit (const 1)) - (set (reg h-dr 5) (neg (reg h-dr 5)))) - () -) - -(define-pmacro (leftshift-op name insn opc1 opc2 arg1 arg2 shift-expr) - (dni name - (.str insn " " arg1 "," arg2) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI shift)) - (set shift shift-expr) - (if (ne shift (const 0)) - (sequence () - (set cbit (ne (and arg2 - (sll (const 1) - (sub (const 32) shift))) - (const 0))) - (set arg2 (sll arg2 shift))) - (set cbit (const 0))) - (set nbit (lt arg2 (const 0))) - (set zbit (eq arg2 (const 0)))) - () - ) -) -(leftshift-op lsl lsl OP1_B OP2_6 Rj Ri (and Rj (const #x1f))) -(leftshift-op lsli lsl OP1_B OP2_4 u4 Ri u4) -(leftshift-op lsl2 lsl2 OP1_B OP2_5 u4 Ri (add u4 (const #x10))) - -(define-pmacro (rightshift-op name insn opc1 opc2 op arg1 arg2 shift-expr) - (dni name - (.str insn " " arg1 "," arg2) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI shift)) - (set shift shift-expr) - (if (ne shift (const 0)) - (sequence () - (set cbit (ne (and arg2 - (sll (const 1) - (sub shift (const 1)))) - (const 0))) - (set arg2 (op arg2 shift))) - (set cbit (const 0))) - (set nbit (lt arg2 (const 0))) - (set zbit (eq arg2 (const 0)))) - () - ) -) -(rightshift-op lsr lsr OP1_B OP2_2 srl Rj Ri (and Rj (const #x1f))) -(rightshift-op lsri lsr OP1_B OP2_0 srl u4 Ri u4) -(rightshift-op lsr2 lsr2 OP1_B OP2_1 srl u4 Ri (add u4 (const #x10))) -(rightshift-op asr asr OP1_B OP2_A sra Rj Ri (and Rj (const #x1f))) -(rightshift-op asri asr OP1_B OP2_8 sra u4 Ri u4) -(rightshift-op asr2 asr2 OP1_B OP2_9 sra u4 Ri (add u4 (const #x10))) - -(dni ldi8 - "load 8 bit unsigned immediate" - () - "ldi:8 $i8,$Ri" - (+ OP1_C i8 Ri) - (set Ri i8) - () -) - -; Typing ldi:8 in in emacs is a pain. -(dnmi ldi8m "ldi:8 without the colon" - (NO-DIS) - "ldi8 $i8,$Ri" - (emit ldi8 i8 Ri) -) - -(dni ldi20 - "load 20 bit unsigned immediate" - (NOT-IN-DELAY-SLOT) - "ldi:20 $i20,$Ri" - (+ OP1_9 OP2_B Ri i20) - (set Ri i20) - ((fr30-1 (unit u-exec (cycles 2)))) -) - -; Typing ldi:20 in in emacs is a pain. -(dnmi ldi20m "ldi:20 without the colon" - (NO-DIS) - "ldi20 $i20,$Ri" - (emit ldi20 i20 Ri) -) - -(dni ldi32 - "load 32 bit immediate" - (NOT-IN-DELAY-SLOT) - "ldi:32 $i32,$Ri" - (+ OP1_9 OP2_F OP3_8 Ri i32) - (set Ri i32) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -; Typing ldi:32 in in emacs is a pain. -(dnmi ldi32m "ldi:32 without the colon" - (NO-DIS) - "ldi32 $i32,$Ri" - (emit ldi32 i32 Ri) -) - -(define-pmacro (basic-ld name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str name " @" arg1 "," arg2) - () - (.str name " @$" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (mem mode arg1)) - ((fr30-1 (unit u-load))) - ) -) - -(basic-ld ld ld OP1_0 OP2_4 WI Rj Ri) -(basic-ld lduh lduh OP1_0 OP2_5 UHI Rj Ri) -(basic-ld ldub ldub OP1_0 OP2_6 UQI Rj Ri) - -(define-pmacro (r13base-ld name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str insn " @(R13," arg1 ")," arg2) - () - (.str insn " @($R13,$" arg1 "),$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (mem mode (add arg1 (reg h-gr 13)))) - ((fr30-1 (unit u-load))) - ) -) - -(r13base-ld ldr13 ld OP1_0 OP2_0 WI Rj Ri) -(r13base-ld ldr13uh lduh OP1_0 OP2_1 UHI Rj Ri) -(r13base-ld ldr13ub ldub OP1_0 OP2_2 UQI Rj Ri) - -(define-pmacro (r14base-ld name insn opc1 mode arg1 arg2) - (dni name - (.str insn " @(R14," arg1 ")," arg2) - () - (.str insn " @($R14,$" arg1 "),$" arg2) - (+ opc1 arg1 arg2) - (set arg2 (mem mode (add arg1 (reg h-gr 14)))) - ((fr30-1 (unit u-load))) - ) -) - -(r14base-ld ldr14 ld OP1_2 WI disp10 Ri) -(r14base-ld ldr14uh lduh OP1_4 UHI disp9 Ri) -(r14base-ld ldr14ub ldub OP1_6 UQI disp8 Ri) - -(dni ldr15 - "ld @(R15,udisp6),Ri mem/reg" - () - "ld @($R15,$udisp6),$Ri" - (+ OP1_0 OP2_3 udisp6 Ri) - (set Ri (mem WI (add udisp6 (reg h-gr 15)))) - ((fr30-1 (unit u-load))) -) - -(dni ldr15gr - "ld @R15+,Ri" - () - "ld @$R15+,$Ri" - (+ OP1_0 OP2_7 OP3_0 Ri) - (sequence () - (set Ri (mem WI (reg h-gr 15))) - (if (ne (ifield f-Ri) (const 15)) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - ((fr30-1 (unit u-load))) -) - -; This insn loads a value from where r15 points into the target register and -; then increments r15. If the target register is also r15, then the post -; increment is not performed. -; -(dni ldr15dr - "ld @R15+,Rs2" - () - "ld @$R15+,$Rs2" - (+ OP1_0 OP2_7 OP3_8 Rs2) -; This seems more straight forward, but doesn't work due to a problem in -; cgen. We're trying to not increment r15 if it is the target register. -; (sequence () -; (set Rs2 (mem WI (reg h-gr 15))) -; (if (not (or (and (eq (ifield f-Rs2) (const 2)) -; (eq sbit (const 0))) -; (and (eq (ifield f-Rs2) (const 3)) -; (eq sbit (const 1))))) -; (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) -; ) -; ) - (sequence ((WI tmp)) - (set tmp (mem WI (reg h-gr 15))) ; save in case target is r15 - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) - (set Rs2 tmp)) - ((fr30-1 (unit u-load))) -) - -(dni ldr15ps - "ld @R15+,ps mem/reg" - (NOT-IN-DELAY-SLOT) - "ld @$R15+,$ps" - (+ OP1_0 OP2_7 OP3_9 OP4_0) - (sequence () - (set ps (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) - ((fr30-1 (unit u-load))) -) - -(define-pmacro (basic-st name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str name " " arg1 ",@" arg2) - () - (.str name " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (set (mem mode arg2) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(basic-st st st OP1_1 OP2_4 WI Ri Rj) -(basic-st sth sth OP1_1 OP2_5 HI Ri Rj) -(basic-st stb stb OP1_1 OP2_6 QI Ri Rj) - -(define-pmacro (r13base-st name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str insn " " arg1 ",@(R13," arg2 ")") - () - (.str insn " $" arg1 ",@($R13,$" arg2 ")") - (+ opc1 opc2 arg1 arg2) - (set (mem mode (add arg2 (reg h-gr 13))) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(r13base-st str13 st OP1_1 OP2_0 WI Ri Rj) -(r13base-st str13h sth OP1_1 OP2_1 HI Ri Rj) -(r13base-st str13b stb OP1_1 OP2_2 QI Ri Rj) - -(define-pmacro (r14base-st name insn opc1 mode arg1 arg2) - (dni name - (.str insn " " arg1 ",@(R14," arg2 ")") - () - (.str insn " $" arg1 ",@($R14,$" arg2 ")") - (+ opc1 arg1 arg2) - (set (mem mode (add arg2 (reg h-gr 14))) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(r14base-st str14 st OP1_3 WI Ri disp10) -(r14base-st str14h sth OP1_5 HI Ri disp9) -(r14base-st str14b stb OP1_7 QI Ri disp8) - -(dni str15 - "st Ri,@(R15,udisp6) reg/mem" - () - "st $Ri,@($R15,$udisp6)" - (+ OP1_1 OP2_3 udisp6 Ri) - (set (mem WI (add (reg h-gr 15) udisp6)) Ri) - ((fr30-1 (unit u-store))) -) - -; These store insns predecrement r15 and then store the contents of the source -; register where r15 then points. If the source register is also r15, then the -; original value of r15 is stored. -; -(dni str15gr - "st Ri,@-R15 reg/mem" - () - "st $Ri,@-$R15" - (+ OP1_1 OP2_7 OP3_0 Ri) - (sequence ((WI tmp)) - (set tmp Ri) ; save in case it's r15 - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) tmp)) - ((fr30-1 (unit u-store))) -) - -(dni str15dr - "st Rs,@-R15 reg/mem" - () - "st $Rs2,@-$R15" - (+ OP1_1 OP2_7 OP3_8 Rs2) - (sequence ((WI tmp)) - (set tmp Rs2) ; save in case it's r15 - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) tmp)) - ((fr30-1 (unit u-store))) -) - -(dni str15ps - "st ps,@-R15 reg/mem" - () - "st $ps,@-$R15" - (+ OP1_1 OP2_7 OP3_9 OP4_0) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) ps)) - ((fr30-1 (unit u-store))) -) - -(define-pmacro (mov2gr name opc1 opc2 arg1 arg2) - (dni name - (.str "mov " arg1 "," arg2) - () - (.str "mov $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 arg1) - () - ) -) - -(mov2gr mov OP1_8 OP2_B Rj Ri) -(mov2gr movdr OP1_B OP2_7 Rs1 Ri) - -(dni movps - "mov ps,Ri reg/reg" - () - "mov $ps,$Ri" - (+ OP1_1 OP2_7 OP3_1 Ri) - (set Ri ps) - () -) - -(dni mov2dr - "mov Ri,Rs reg/reg" - () - "mov $Ri,$Rs1" - (+ OP1_B OP2_3 Rs1 Ri) - (set Rs1 Ri) - () -) - -(dni mov2ps - "mov Ri,ps reg/reg" - () - "mov $Ri,$ps" - (+ OP1_0 OP2_7 OP3_1 Ri) - (set ps Ri) - () -) - -(dni jmp - "jmp with no delay slot" - (NOT-IN-DELAY-SLOT) - "jmp @$Ri" - (+ OP1_9 OP2_7 OP3_0 Ri) - (set pc Ri) - ((fr30-1 (unit u-cti))) -) - -(dni jmpd "jmp with delay slot" - (NOT-IN-DELAY-SLOT) - "jmp:d @$Ri" - (+ OP1_9 OP2_F OP3_0 Ri) - (delay (const 1) - (set pc Ri)) - ((fr30-1 (unit u-cti))) -) - -; These versions which use registers must appear before the other -; versions which use relative addresses due to a problem in cgen -; - DB. -(dni callr - "call @Ri" - (NOT-IN-DELAY-SLOT) - "call @$Ri" - (+ OP1_9 OP2_7 OP3_1 Ri) - (sequence () - (set (reg h-dr 1) (add pc (const 2))) - (set pc Ri)) - ((fr30-1 (unit u-cti))) -) -(dni callrd - "call:d @Ri" - (NOT-IN-DELAY-SLOT) - "call:d @$Ri" - (+ OP1_9 OP2_F OP3_1 Ri) - (delay (const 1) - (sequence () - (set (reg h-dr 1) (add pc (const 4))) - (set pc Ri))) - ((fr30-1 (unit u-cti))) -) -; end of reordered insns - -(dni call - "call relative to pc" - (NOT-IN-DELAY-SLOT) - "call $label12" - (+ OP1_D OP5_0 label12) - (sequence () - (set (reg h-dr 1) (add pc (const 2))) - (set pc label12)) - ((fr30-1 (unit u-cti))) -) -(dni calld - "call relative to pc" - (NOT-IN-DELAY-SLOT) - "call:d $label12" - (+ OP1_D OP5_1 label12) - (delay (const 1) - (sequence () - (set (reg h-dr 1) (add pc (const 4))) - (set pc label12))) - ((fr30-1 (unit u-cti))) -) - -(dni ret - "return from subroutine" - (NOT-IN-DELAY-SLOT) - "ret" - (+ OP1_9 OP2_7 OP3_2 OP4_0) - (set pc (reg h-dr 1)) - ((fr30-1 (unit u-cti))) -) - -(dni ret:d - "return from subroutine with delay slot" - (NOT-IN-DELAY-SLOT) - "ret:d" - (+ OP1_9 OP2_F OP3_2 OP4_0) - (delay (const 1) - (set pc (reg h-dr 1))) - ((fr30-1 (unit u-cti))) -) - -(dni int - "interrupt" - (NOT-IN-DELAY-SLOT) - "int $u8" - (+ OP1_1 OP2_F u8) - (sequence () - ; This is defered to fr30_int because for the breakpoint case - ; we want to change as little of the machine state as possible. - ; Push PS onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) ps) - ; Push the return address onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) - ; Set status bits - ;(set ibit (const 0)) - ;(set sbit (const 0)) - - ; We still should indicate what is modified by this insn. - (clobber (reg h-dr 2)) - (clobber ibit) - (clobber sbit) - ; ??? (clobber memory)? - - ; fr30_int handles operating vs user mode - (set WI pc (c-call WI "fr30_int" pc u8)) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 6)))) -) - -(dni inte - "interrupt for emulator" - (NOT-IN-DELAY-SLOT) - "inte" - (+ OP1_9 OP2_F OP3_3 OP4_0) - (sequence () - ; This is defered to fr30_inte because for the breakpoint case - ; we want to change as little of the machine state as possible. - ; Push PS onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) ps) - ; Push the return address onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) - ; Set status bits - ;(set ibit (const 0)) - ;(set ilm (const 4)) - - ; We still should indicate what is modified by this insn. - (clobber (reg h-dr 2)) - (clobber ibit) - (clobber ilm) - ; ??? (clobber memory)? - - ; fr30_int handles operating vs user mode - (set WI pc (c-call WI "fr30_inte" pc)) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 6)))) -) - -(dni reti - "return from interrupt" - (NOT-IN-DELAY-SLOT) - "reti" - (+ OP1_9 OP2_7 OP3_3 OP4_0) - (if (eq sbit (const 0)) - (sequence () - ; Pop the return address from the system stack - (set UWI pc (mem UWI (reg h-dr 2))) - (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) - ; Pop PS from the system stack - (set UWI ps (mem UWI (reg h-dr 2))) - (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) - ) - (sequence () - ; Pop the return address from the user stack - (set UWI pc (mem UWI (reg h-dr 3))) - (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) - ; Pop PS from the user stack - (set UWI ps (mem UWI (reg h-dr 3))) - (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) - ) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 4)))) -) - -; Conditional branches with and without delay slots -; -(define-pmacro (cond-branch cc condition) - (begin - (dni (.sym b cc d) - (.str (.sym b cc :d) " label9") - (NOT-IN-DELAY-SLOT) - (.str (.sym b cc :d) " $label9") - (+ OP1_F (.sym CC_ cc) label9) - (delay (const 1) - (if condition (set pc label9))) - ((fr30-1 (unit u-cti))) - ) - (dni (.sym b cc) - (.str (.sym b cc) " label9") - (NOT-IN-DELAY-SLOT) - (.str (.sym b cc) " $label9") - (+ OP1_E (.sym CC_ cc) label9) - (if condition (set pc label9)) - ((fr30-1 (unit u-cti))) - ) - ) -) - -(cond-branch ra (const BI 1)) -(cond-branch no (const BI 0)) -(cond-branch eq zbit) -(cond-branch ne (not zbit)) -(cond-branch c cbit) -(cond-branch nc (not cbit)) -(cond-branch n nbit) -(cond-branch p (not nbit)) -(cond-branch v vbit) -(cond-branch nv (not vbit)) -(cond-branch lt (xor vbit nbit)) -(cond-branch ge (not (xor vbit nbit))) -(cond-branch le (or (xor vbit nbit) zbit)) -(cond-branch gt (not (or (xor vbit nbit) zbit))) -(cond-branch ls (or cbit zbit)) -(cond-branch hi (not (or cbit zbit))) - -(define-pmacro (dir2r13 name insn opc1 opc2 mode arg1) - (dni name - (.str insn " @" arg1 ",R13") - () - (.str insn " @$" arg1 ",$R13") - (+ opc1 opc2 arg1) - (set (reg h-gr 13) (mem mode arg1)) - ((fr30-1 (unit u-load))) - ) -) - -(define-pmacro (dir2r13-postinc name insn opc1 opc2 mode arg1 incr) - (dni name - (.str insn " @" arg1 ",@R13+") - (NOT-IN-DELAY-SLOT) - (.str insn " @$" arg1 ",@$R13+") - (+ opc1 opc2 arg1) - (sequence () - (set (mem mode (reg h-gr 13)) (mem mode arg1)) - (set (reg h-gr 13) (add (reg h-gr 13) incr))) - ((fr30-1 (unit u-load) (unit u-store))) - ) -) - -(define-pmacro (r132dir name insn opc1 opc2 mode arg1) - (dni name - (.str insn " R13,@" arg1) - () - (.str insn " $R13,@$" arg1) - (+ opc1 opc2 arg1) - (set (mem mode arg1) (reg h-gr 13)) - ((fr30-1 (unit u-store))) - ) -) - -(define-pmacro (r13-postinc2dir name insn opc1 opc2 mode arg1 incr) - (dni name - (.str insn " @R13+,@" arg1) - (NOT-IN-DELAY-SLOT) - (.str insn " @$R13+,@$" arg1) - (+ opc1 opc2 arg1) - (sequence () - (set (mem mode arg1) (mem mode (reg h-gr 13))) - (set (reg h-gr 13) (add (reg h-gr 13) incr))) - ((fr30-1 (unit u-load) (unit u-store))) - ) -) - -; These versions which move from reg to mem must appear before the other -; versions which use immediate addresses due to a problem in cgen -; - DB. -(r132dir dmovr13 dmov OP1_1 OP2_8 WI dir10) -(r132dir dmovr13h dmovh OP1_1 OP2_9 HI dir9) -(r132dir dmovr13b dmovb OP1_1 OP2_A QI dir8) - -(r13-postinc2dir dmovr13pi dmov OP1_1 OP2_C WI dir10 (const 4)) -(r13-postinc2dir dmovr13pih dmovh OP1_1 OP2_D HI dir9 (const 2)) -(r13-postinc2dir dmovr13pib dmovb OP1_1 OP2_E QI dir8 (const 1)) - -(dni dmovr15pi - "dmov @R15+,@dir10" - (NOT-IN-DELAY-SLOT) - "dmov @$R15+,@$dir10" - (+ OP1_1 OP2_B dir10) - (sequence () - (set (mem WI dir10) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) - ((fr30-1 (unit u-load) (unit u-store))) -) -; End of reordered insns. - -(dir2r13 dmov2r13 dmov OP1_0 OP2_8 WI dir10) -(dir2r13 dmov2r13h dmovh OP1_0 OP2_9 HI dir9) -(dir2r13 dmov2r13b dmovb OP1_0 OP2_A QI dir8) - -(dir2r13-postinc dmov2r13pi dmov OP1_0 OP2_C WI dir10 (const 4)) -(dir2r13-postinc dmov2r13pih dmovh OP1_0 OP2_D HI dir9 (const 2)) -(dir2r13-postinc dmov2r13pib dmovb OP1_0 OP2_E QI dir8 (const 1)) - -(dni dmov2r15pd - "dmov @dir10,@-R15" - (NOT-IN-DELAY-SLOT) - "dmov @$dir10,@-$R15" - (+ OP1_0 OP2_B dir10) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (mem WI dir10))) - ((fr30-1 (unit u-load) (unit u-store))) -) - -; Leave these insns as stubs for now, except for the increment of $Ri -; -(dni ldres - "ldres @Ri+,#u4" - () - "ldres @$Ri+,$u4" - (+ OP1_B OP2_C u4 Ri) - (set Ri (add Ri (const 4))) - () -) - -(dni stres - "stres #u4,@Ri+" - () - "stres $u4,@$Ri+" - (+ OP1_B OP2_D u4 Ri) - (set Ri (add Ri (const 4))) - () -) - -; Leave the coprocessor insns as stubs for now. -; -(define-pmacro (cop-stub name insn opc1 opc2 opc3 arg1 arg2) - (dni name - (.str insn " u4c,ccc,CRj," arg1 "," arg2) - (NOT-IN-DELAY-SLOT) - (.str insn " $u4c,$ccc,$" arg1 ",$" arg2) - (+ opc1 opc2 opc3 u4c ccc arg1 arg2) - (nop) ; STUB - () - ) -) - -(cop-stub copop copop OP1_9 OP2_F OP3_C CRj CRi) -(cop-stub copld copld OP1_9 OP2_F OP3_D Rjc CRi) -(cop-stub copst copst OP1_9 OP2_F OP3_E CRj Ric) -(cop-stub copsv copsv OP1_9 OP2_F OP3_F CRj Ric) - -(dni nop - "nop" - () - "nop" - (+ OP1_9 OP2_F OP3_A OP4_0) - (nop) - () -) - -(dni andccr - "andccr #u8" - () - "andccr $u8" - (+ OP1_8 OP2_3 u8) - (set ccr (and ccr u8)) - () -) - -(dni orccr - "orccr #u8" - () - "orccr $u8" - (+ OP1_9 OP2_3 u8) - (set ccr (or ccr u8)) - () -) - -(dni stilm - "stilm #u8" - () - "stilm $u8" - (+ OP1_8 OP2_7 u8) - (set ilm (and u8 (const #x1f))) - () -) - -(dni addsp - "addsp #s10" - () - "addsp $s10" - (+ OP1_A OP2_3 s10) - (set (reg h-gr 15) (add (reg h-gr 15) s10)) - () -) - -(define-pmacro (ext-op name opc1 opc2 opc3 op mode mask) - (dni name - (.str name " Ri") - () - (.str name " $Ri") - (+ opc1 opc2 opc3 Ri) - (set Ri (op WI (and mode Ri mask))) - () - ) -) - -(ext-op extsb OP1_9 OP2_7 OP3_8 ext QI (const #xff)) -(ext-op extub OP1_9 OP2_7 OP3_9 zext UQI (const #xff)) -(ext-op extsh OP1_9 OP2_7 OP3_A ext HI (const #xffff)) -(ext-op extuh OP1_9 OP2_7 OP3_B zext UHI (const #xffff)) - -(dni ldm0 - "ldm0 (reglist_low_ld)" - (NOT-IN-DELAY-SLOT) - "ldm0 ($reglist_low_ld)" - (+ OP1_8 OP2_C reglist_low_ld) - (sequence () - (if (and reglist_low_ld (const #x1)) - (sequence () - (set (reg h-gr 0) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x2)) - (sequence () - (set (reg h-gr 1) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x4)) - (sequence () - (set (reg h-gr 2) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x8)) - (sequence () - (set (reg h-gr 3) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x10)) - (sequence () - (set (reg h-gr 4) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x20)) - (sequence () - (set (reg h-gr 5) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x40)) - (sequence () - (set (reg h-gr 6) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x80)) - (sequence () - (set (reg h-gr 7) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - ) - ((fr30-1 (unit u-ldm))) -) - -(dni ldm1 - "ldm1 (reglist_hi_ld)" - (NOT-IN-DELAY-SLOT) - "ldm1 ($reglist_hi_ld)" - (+ OP1_8 OP2_D reglist_hi_ld) - (sequence () - (if (and reglist_hi_ld (const #x1)) - (sequence () - (set (reg h-gr 8) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x2)) - (sequence () - (set (reg h-gr 9) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x4)) - (sequence () - (set (reg h-gr 10) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x8)) - (sequence () - (set (reg h-gr 11) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x10)) - (sequence () - (set (reg h-gr 12) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x20)) - (sequence () - (set (reg h-gr 13) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x40)) - (sequence () - (set (reg h-gr 14) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x80)) - (set (reg h-gr 15) (mem WI (reg h-gr 15)))) - ) - ((fr30-1 (unit u-ldm))) -) - -(dni stm0 - "stm0 (reglist_low_st)" - (NOT-IN-DELAY-SLOT) - "stm0 ($reglist_low_st)" - (+ OP1_8 OP2_E reglist_low_st) - (sequence () - (if (and reglist_low_st (const #x1)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 7)))) - (if (and reglist_low_st (const #x2)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 6)))) - (if (and reglist_low_st (const #x4)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 5)))) - (if (and reglist_low_st (const #x8)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 4)))) - (if (and reglist_low_st (const #x10)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 3)))) - (if (and reglist_low_st (const #x20)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 2)))) - (if (and reglist_low_st (const #x40)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 1)))) - (if (and reglist_low_st (const #x80)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 0)))) - ) - ((fr30-1 (unit u-stm))) -) - -(dni stm1 - "stm1 (reglist_hi_st)" - (NOT-IN-DELAY-SLOT) - "stm1 ($reglist_hi_st)" - (+ OP1_8 OP2_F reglist_hi_st) - (sequence () - (if (and reglist_hi_st (const #x1)) - (sequence ((WI save-r15)) - (set save-r15 (reg h-gr 15)) - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) save-r15))) - (if (and reglist_hi_st (const #x2)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 14)))) - (if (and reglist_hi_st (const #x4)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 13)))) - (if (and reglist_hi_st (const #x8)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 12)))) - (if (and reglist_hi_st (const #x10)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 11)))) - (if (and reglist_hi_st (const #x20)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 10)))) - (if (and reglist_hi_st (const #x40)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 9)))) - (if (and reglist_hi_st (const #x80)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 8)))) - ) - ((fr30-1 (unit u-stm))) -) - -(dni enter - "enter #u10" - (NOT-IN-DELAY-SLOT) - "enter $u10" - (+ OP1_0 OP2_F u10) - (sequence ((WI tmp)) - (set tmp (sub (reg h-gr 15) (const 4))) - (set (mem WI tmp) (reg h-gr 14)) - (set (reg h-gr 14) tmp) - (set (reg h-gr 15) (sub (reg h-gr 15) u10))) - ((fr30-1 (unit u-exec (cycles 2)))) -) - -(dni leave - "leave" - () - "leave" - (+ OP1_9 OP2_F OP3_9 OP4_0) - (sequence () - (set (reg h-gr 15) (add (reg h-gr 14) (const 4))) - (set (reg h-gr 14) (mem WI (sub (reg h-gr 15) (const 4))))) - () -) - -(dni xchb - "xchb @Rj,Ri" - (NOT-IN-DELAY-SLOT) - "xchb @$Rj,$Ri" - (+ OP1_8 OP2_A Rj Ri) - (sequence ((WI tmp)) - (set tmp Ri) - (set Ri (mem UQI Rj)) - (set (mem UQI Rj) tmp)) - ((fr30-1 (unit u-load) (unit u-store))) -) diff --git a/cpu/fr30.opc b/cpu/fr30.opc deleted file mode 100644 index 4f7a6b4..0000000 --- a/cpu/fr30.opc +++ /dev/null @@ -1,235 +0,0 @@ -/* FR30 opcode support. -*- C -*- - Copyright (C) 2000, 2001, 2005 Red Hat, Inc. - This file is part of CGEN. */ - -/* This file is an addendum to fr30.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - -opc.h additions use: "-- opc.h" - -opc.c additions use: "-- opc.c" - -asm.c additions use: "-- asm.c" - -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* ??? This can be improved upon. */ -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 16 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) - -/* -- */ - -/* -- asm.c */ -/* Handle register lists for LDMx and STMx. */ - -static int -parse_register_number (const char **strp) -{ - int regno; - - if (**strp < '0' || **strp > '9') - return -1; /* Error. */ - regno = **strp - '0'; - ++*strp; - - if (**strp >= '0' && **strp <= '9') - { - regno = regno * 10 + (**strp - '0'); - ++*strp; - } - - return regno; -} - -static const char * -parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep, - int high_low, /* 0 == high, 1 == low. */ - int load_store) /* 0 == load, 1 == store. */ -{ - *valuep = 0; - while (**strp && **strp != ')') - { - int regno; - - if (**strp != 'R' && **strp != 'r') - break; - ++*strp; - - regno = parse_register_number (strp); - if (regno == -1) - return _("Register number is not valid"); - if (regno > 7 && !high_low) - return _("Register must be between r0 and r7"); - if (regno < 8 && high_low) - return _("Register must be between r8 and r15"); - - if (high_low) - regno -= 8; - - if (load_store) /* Mask is reversed for store. */ - *valuep |= 0x80 >> regno; - else - *valuep |= 1 << regno; - - if (**strp == ',') - { - if (*(*strp + 1) == ')') - break; - ++*strp; - } - } - - if (!*strp || **strp != ')') - return _("Register list is not valid"); - - return NULL; -} - -static const char * -parse_low_register_list_ld (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 0 /* Low. */, 0 /* Load. */); -} - -static const char * -parse_hi_register_list_ld (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 1 /* High. */, 0 /* Load. */); -} - -static const char * -parse_low_register_list_st (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 0 /* Low. */, 1 /* Store. */); -} - -static const char * -parse_hi_register_list_st (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 1 /* High. */, 1 /* Store. */); -} - -/* -- */ - -/* -- dis.c */ -static void -print_register_list (void * dis_info, - long value, - long offset, - int load_store) /* 0 == load, 1 == store. */ -{ - disassemble_info *info = dis_info; - int mask; - int reg_index = 0; - char * comma = ""; - - if (load_store) - mask = 0x80; - else - mask = 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "r%li", reg_index + offset); - comma = ","; - } - - for (reg_index = 1; reg_index <= 7; ++reg_index) - { - if (load_store) - mask >>= 1; - else - mask <<= 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset); - comma = ","; - } - } -} - -static void -print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 8, 0 /* Load. */); -} - -static void -print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 0, 0 /* Load. */); -} - -static void -print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 8, 1 /* Store. */); -} - -static void -print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 0, 1 /* Store. */); -} - -static void -print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "%ld", value); -} -/* -- */ diff --git a/cpu/ip2k.cpu b/cpu/ip2k.cpu deleted file mode 100644 index 8d5641e..0000000 --- a/cpu/ip2k.cpu +++ /dev/null @@ -1,1464 +0,0 @@ -; Ubicom IP2K CPU description. -*- Scheme -*- -; Copyright (C) 2000, 2001 Red Hat, Inc. -; Copyright (C) 2002, 2009 Free Software Foundation, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -; define-arch must appear first - -(define-arch - (name ip2k) ; name of cpu family - (comment "Ubicom IP2000 family") - (default-alignment aligned) - (insn-lsb0? #t) - (machs ip2022 ip2022ext) - (isas ip2k) -) - -; Attributes. - -(define-attr - (for insn) - (type boolean) - (name EXT-SKIP-INSN) - (comment "instruction is a PAGE, LOADL, LOADH or BREAKX instruction") -) - -(define-attr - (for insn) - (type boolean) - (name SKIPA) - (comment "instruction is a SKIP instruction") -) - -; Instruction set parameters. - -(define-isa - (name ip2k) - (comment "Ubicom IP2000 ISA") - - (default-insn-word-bitsize 16) - (default-insn-bitsize 16) - (base-insn-bitsize 16) -) - -; Cpu family definitions. - - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name ip2kbf) - (comment "Ubicom IP2000 Family") - (endian big) - (word-bitsize 16) -) - -(define-mach - (name ip2022) - (comment "Ubicom IP2022") - (cpu ip2kbf) -) - -(define-mach - (name ip2022ext) - (comment "Ubicom IP2022 extended") - (cpu ip2kbf) -) - - -; Model descriptions. - -(define-model - (name ip2k) (comment "VPE 2xxx") (attrs) - (mach ip2022ext) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - - -; FIXME: It might simplify things to separate the execute process from the -; one that updates the PC. - -; Instruction fields. -; -; Attributes: -; XXX: what VPE attrs -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 -; RELOC: there is a relocation associated with this field (experiment) - - -(dnf f-imm8 "imm8" () 7 8) -(dnf f-reg "reg" (ABS-ADDR) 8 9) -(dnf f-addr16cjp "addr16cjp" (ABS-ADDR) 12 13) -(dnf f-dir "dir" () 9 1) -(dnf f-bitno "bit number" () 11 3) -(dnf f-op3 "op3" () 15 3) -(dnf f-op4 "op4" () 15 4) -(dnf f-op4mid "op4mid" () 11 4) -(dnf f-op6 "op6" () 15 6) -(dnf f-op8 "op8" () 15 8) -(dnf f-op6-10low "op6-10low" () 9 10) -(dnf f-op6-7low "op6-7low" () 9 7) -(dnf f-reti3 "reti3" () 2 3) -(dnf f-skipb "sb/snb" (ABS-ADDR) 12 1) -(dnf f-page3 "page3" () 2 3) -;(define-ifield (name f-page3) (comment "page3") (attrs) (start 2) (length 3) -; (encode (value pc) (srl WI value 13)) -; (decode (value pc) (sll WI value 13)) -;) -; To fix the page/call asymmetry -;(define-ifield (name f-page3) (comment "page3") (attrs) (start 2) (length 3) -; (encode (value pc) (srl WI value 13)) -; (decode (value pc) (sll WI value 13)) -;) - - - -; Enums. - -; insn-op6: bits 15-10 -(define-normal-insn-enum insn-op6 "op6 enums" () OP6_ f-op6 - (OTHER1 OTHER2 SUB DEC OR AND XOR ADD - TEST NOT INC DECSZ RR RL SWAP INCSZ - CSE POP SUBC DECSNZ MULU MULS INCSNZ ADDC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ) -) - -; insn-dir: bit 9 -(define-normal-insn-enum insn-dir "dir enums" () DIR_ f-dir - ; This bit specifies the polarity of many two-operand instructions: - ; TO_W writes result to W regiser (eg. ADDC W,$fr) - ; NOTTO_W writes result in general register (eg. ADDC $fr,W) - (TO_W NOTTO_W) -) - - -; insn-op4: bits 15-12 -(define-normal-insn-enum insn-op4 "op4 enums" () OP4_ f-op4 - (- - - - - - - LITERAL - CLRB SETB SNB SB - - - - - ) -) - -; insn-op4mid: bits 11-8 -; used for f-op4=LITERAL -(define-normal-insn-enum insn-op4mid "op4mid enums" () OP4MID_ f-op4mid - (LOADH_L LOADL_L MULU_L MULS_L PUSH_L - CSNE_L CSE_L - RETW_L CMP_L SUB_L ADD_L MOV_L OR_L AND_L XOR_L) -) - -; insn-op3: bits 15-13 -(define-normal-insn-enum insn-op3 "op3 enums" () OP3_ f-op3 - (- - - - - - CALL JMP) -) - - - -; Hardware pieces. - -; Bank-relative general purpose registers - -; (define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) - -(define-keyword - (name register-names) - (enum-prefix H-REGISTERS-) - (values - ; These are the "Special Purpose Registers" that are not reserved - ("ADDRSEL" #x2) ("ADDRX" #x3) - ("IPH" #x4) ("IPL" #x5) ("SPH" #x6) ("SPL" #x7) - ("PCH" #x8) ("PCL" #x9) ("WREG" #xA) ("STATUS" #xB) - ("DPH" #xC) ("DPL" #xD) ("SPDREG" #xE) ("MULH" #xF) - ("ADDRH" #x10) ("ADDRL" #x11) ("DATAH" #x12) ("DATAL" #x13) - ("INTVECH" #x14) ("INTVECL" #x15) ("INTSPD" #x16) ("INTF" #x17) - ("INTE" #x18) ("INTED" #x19) ("FCFG" #x1A) ("TCTRL" #x1B) - ("XCFG" #x1C) ("EMCFG" #x1D) ("IPCH" #x1E) ("IPCL" #x1F) - ("RAIN" #x20) ("RAOUT" #x21) ("RADIR" #x22) ("LFSRH" #x23) - ("RBIN" #x24) ("RBOUT" #x25) ("RBDIR" #x26) ("LFSRL" #x27) - ("RCIN" #x28) ("RCOUT" #x29) ("RCDIR" #x2A) ("LFSRA" #x2B) - ("RDIN" #x2C) ("RDOUT" #x2D) ("RDDIR" #x2E) - ("REIN" #x30) ("REOUT" #x31) ("REDIR" #x32) - ("RFIN" #x34) ("RFOUT" #x35) ("RFDIR" #x36) - ("RGOUT" #x39) ("RGDIR" #x3A) - ("RTTMR" #x40) ("RTCFG" #x41) ("T0TMR" #x42) ("T0CFG" #x43) - ("T1CNTH" #x44) ("T1CNTL" #x45) ("T1CAP1H" #x46) ("T1CAP1L" #x47) - ("T1CAP2H" #x48) ("T1CMP2H" #x48) ("T1CAP2L" #x49) ("T1CMP2L" #x49) ; note aliases - ("T1CMP1H" #x4A) ("T1CMP1L" #x4B) - ("T1CFG1H" #x4C) ("T1CFG1L" #x4D) ("T1CFG2H" #x4E) ("T1CFG2L" #x4F) - ("ADCH" #x50) ("ADCL" #x51) ("ADCCFG" #x52) ("ADCTMR" #x53) - ("T2CNTH" #x54) ("T2CNTL" #x55) ("T2CAP1H" #x56) ("T2CAP1L" #x57) - ("T2CAP2H" #x58) ("T2CMP2H" #x58) ("T2CAP2L" #x59) ("T2CMP2L" #x59) ; note aliases - ("T2CMP1H" #x5A) ("T2CMP1L" #x5B) - ("T2CFG1H" #x5C) ("T2CFG1L" #x5D) ("T2CFG2H" #x5E) ("T2CFG2L" #x5F) - ("S1TMRH" #x60) ("S1TMRL" #x61) ("S1TBUFH" #x62) ("S1TBUFL" #x63) - ("S1TCFG" #x64) ("S1RCNT" #x65) ("S1RBUFH" #x66) ("S1RBUFL" #x67) - ("S1RCFG" #x68) ("S1RSYNC" #x69) ("S1INTF" #x6A) ("S1INTE" #x6B) - ("S1MODE" #x6C) ("S1SMASK" #x6D) ("PSPCFG" #x6E) ("CMPCFG" #x6F) - ("S2TMRH" #x70) ("S2TMRL" #x71) ("S2TBUFH" #x72) ("S2TBUFL" #x73) - ("S2TCFG" #x74) ("S2RCNT" #x75) ("S2RBUFH" #x76) ("S2RBUFL" #x77) - ("S2RCFG" #x78) ("S2RSYNC" #x79) ("S2INTF" #x7A) ("S2INTE" #x7B) - ("S2MODE" #x7C) ("S2SMASK" #x7D) ("CALLH" #x7E) ("CALLL" #x7F)) - ) - -(define-hardware - (name h-spr) - (comment "special-purpose registers") - (type register QI (128)) - (get (index) (c-call QI "get_spr" index )) - (set (index newval) (c-call VOID "set_spr" index newval )) -) - - -;;(define-hardware -;; (name h-gpr-global) -;; (comment "gpr registers - global") -;; (type register QI (128)) -;;) - -; The general register - -(define-hardware - (name h-registers) - (comment "all addressable registers") - (attrs VIRTUAL) - (type register QI (512)) - (get (index) (c-call QI "get_h_registers" index )) - (set (index newval) (c-call VOID "set_h_registers" index newval )) -) - -; The hardware stack. -; Use {push,pop}_pc_stack c-calls to operate on this hardware element. - -(define-hardware - (name h-stack) - (comment "hardware stack") - (type register UHI (16)) -) - -(dsh h-pabits "page bits" () (register QI)) -(dsh h-zbit "zero bit" () (register BI)) -(dsh h-cbit "carry bit" () (register BI)) -(dsh h-dcbit "digit-carry bit" () (register BI)) -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - - -; Operands - -(define-operand (name addr16cjp) (comment "13-bit address") (attrs) - (type h-uint) (index f-addr16cjp) (handlers (parse "addr16_cjp") (print "dollarhex_cj"))) ; overload lit8 printer -(define-operand (name fr) (comment "register") (attrs) - (type h-registers) (index f-reg) (handlers (parse "fr") (print "fr"))) -(define-operand (name lit8) (comment "8-bit signed literal") (attrs) - (type h-sint) (index f-imm8) (handlers (parse "lit8") (print "dollarhex8"))) -(define-operand (name bitno) (comment "bit number") (attrs) - (type h-uint) (index f-bitno) (handlers (parse "bit3")(print "decimal"))) -(define-operand (name addr16p) (comment "page number") (attrs) - (type h-uint) (index f-page3) (handlers (parse "addr16_cjp") (print "dollarhex_p"))) -(define-operand (name addr16h) (comment "high 8 bits of address") (attrs) - (type h-uint) (index f-imm8) (handlers (parse "addr16") (print "dollarhex_addr16h"))) -(define-operand (name addr16l) (comment "low 8 bits of address") (attrs) - (type h-uint) (index f-imm8) (handlers (parse "addr16") (print "dollarhex_addr16l"))) -(define-operand (name reti3) (comment "reti flags") (attrs) - (type h-uint) (index f-reti3) (handlers (print "dollarhex"))) -(dnop pabits "page bits" () h-pabits f-nil) -(dnop zbit "zero bit" () h-zbit f-nil) -(dnop cbit "carry bit" () h-cbit f-nil) -(dnop dcbit "digit carry bit" () h-dcbit f-nil) -;;(dnop bank "bank register" () h-bank-no f-nil) - -(define-pmacro w (reg h-spr #x0A)) -(define-pmacro mulh (reg h-spr #x0F)) -(define-pmacro dph (reg h-spr #x0C)) -(define-pmacro dpl (reg h-spr #x0D)) -(define-pmacro sph (reg h-spr #x06)) -(define-pmacro spl (reg h-spr #x07)) -(define-pmacro iph (reg h-spr #x04)) -(define-pmacro ipl (reg h-spr #x05)) -(define-pmacro addrh (reg h-spr #x10)) -(define-pmacro addrl (reg h-spr #x11)) - - - -; Pseudo-RTL for DC flag calculations -; "DC" = "digit carry", ie carry between nibbles -(define-pmacro (add-dcflag a b c) - (add-cflag (sll QI a 4) (sll QI b 4) c) -) - -(define-pmacro (sub-dcflag a b c) - (sub-cflag (sll QI a 4) (sll QI b 4) c) -) - -; Check to see if an fr is one of IPL, SPL, DPL, ADDRL, PCL. -(define-pmacro (LregCheck isLreg fr9bit) - (sequence() - (set isLreg #x0) ;; Assume it's not an Lreg - (if (or (or (eq fr9bit #x5) (eq fr9bit #x7)) - (or (eq fr9bit #x9) - (or (eq fr9bit #xd) (eq fr9bit #x11)))) - (set isLreg #x1) - ) - ) -) - - -; Instructions, in order of the "Instruction Set Map" table on -; pp 19-20 of IP2022 spec V1.09 - -(dni jmp "Jump" - () - "jmp $addr16cjp" - (+ OP3_JMP addr16cjp) - (set pc (or (sll pabits 13) addr16cjp)) - () -) - -; note that in call, we push pc instead of pc + 1 because the ip2k increments -; the pc prior to execution of the instruction -(dni call "Call" - () - "call $addr16cjp" - (+ OP3_CALL addr16cjp) - (sequence () - (c-call "push_pc_stack" pc) - (set pc (or (sll pabits 13) addr16cjp))) - () -) - -(dni sb "Skip if bit set" - () - "sb $fr,$bitno" - (+ OP4_SB bitno fr) - (if (and fr (sll 1 bitno)) - (skip 1)) - () -) - -(dni snb "Skip if bit clear" - () - "snb $fr,$bitno" - (+ OP4_SNB bitno fr) - (if (not (and fr (sll 1 bitno))) - (skip 1)) - () -) - -(dni setb "Set bit" - () - "setb $fr,$bitno" - (+ OP4_SETB bitno fr) - (set fr (or fr (sll 1 bitno))) - () -) - -(dni clrb "Clear bit" - () - "clrb $fr,$bitno" - (+ OP4_CLRB bitno fr) - (set fr (and fr (inv (sll 1 bitno)))) - () -) - -(dni xorw_l "XOR W,literal" - () - "xor W,#$lit8" - (+ OP4_LITERAL OP4MID_XOR_L lit8) - (sequence () - (set w (xor w lit8)) - (set zbit (zflag w))) - () -) - -(dni andw_l "AND W,literal" - () - "and W,#$lit8" - (+ OP4_LITERAL OP4MID_AND_L lit8) - (sequence () - (set w (and w lit8)) - (set zbit (zflag w))) - () -) - -(dni orw_l "OR W,literal" - () - "or W,#$lit8" - (+ OP4_LITERAL OP4MID_OR_L lit8) - (sequence () - (set w (or w lit8)) - (set zbit (zflag w))) - () -) - -(dni addw_l "ADD W,literal" - () - "add W,#$lit8" - (+ OP4_LITERAL OP4MID_ADD_L lit8) - (sequence () - (set cbit (add-cflag w lit8 0)) - (set dcbit (add-dcflag w lit8 0)) - (set w (add w lit8)) - (set zbit (zflag w))) - () -) - -(dni subw_l "SUB W,literal" - () - "sub W,#$lit8" - (+ OP4_LITERAL OP4MID_SUB_L lit8) - (sequence () - (set cbit (not (sub-cflag lit8 w 0))) - (set dcbit (not (sub-dcflag lit8 w 0))) - (set zbit (zflag (sub w lit8))) - (set w (sub lit8 w))) - () -) - -(dni cmpw_l "CMP W,literal" - () - "cmp W,#$lit8" - (+ OP4_LITERAL OP4MID_CMP_L lit8) - (sequence () - (set cbit (not (sub-cflag lit8 w 0))) - (set dcbit (not (sub-dcflag lit8 w 0))) - (set zbit (zflag (sub w lit8)))) - () -) - -(dni retw_l "RETW literal" - () - "retw #$lit8" - (+ OP4_LITERAL OP4MID_RETW_L lit8) - (sequence ((USI new_pc)) - (set w lit8) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pabits (srl new_pc 13)) - (set pc new_pc)) - () -) - -(dni csew_l "CSE W,literal" - () - "cse W,#$lit8" - (+ OP4_LITERAL OP4MID_CSE_L lit8) - (if (eq w lit8) - (skip 1)) - () -) - -(dni csnew_l "CSNE W,literal" - () - "csne W,#$lit8" - (+ OP4_LITERAL OP4MID_CSNE_L lit8) - (if (not (eq w lit8)) - (skip 1)) - () -) - -(dni push_l "Push #lit8" - () - "push #$lit8" - (+ OP4_LITERAL OP4MID_PUSH_L lit8) - (sequence () - (c-call "push" lit8) - (c-call VOID "adjuststackptr" (const -1)) - - ) - () -) - -(dni mulsw_l "Multiply W,literal (signed)" - () - "muls W,#$lit8" - (+ OP4_LITERAL OP4MID_MULS_L lit8) - (sequence ((SI tmp)) - (set tmp (mul (ext SI w) (ext SI (and UQI #xff lit8)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni muluw_l "Multiply W,literal (unsigned)" - () - "mulu W,#$lit8" - (+ OP4_LITERAL OP4MID_MULU_L lit8) - (sequence ((USI tmp)) - (set tmp (and #xFFFF (mul (zext USI w) (zext USI lit8)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni loadl_l "LoadL literal" - (EXT-SKIP-INSN) - "loadl #$lit8" - (+ OP4_LITERAL OP4MID_LOADL_L lit8) - (set dpl (and lit8 #x00FF)) - () -) - -(dni loadh_l "LoadH literal" - (EXT-SKIP-INSN) - "loadh #$lit8" - (+ OP4_LITERAL OP4MID_LOADH_L lit8) - (set dph (and lit8 #x00FF)) - () -) - -(dni loadl_a "LoadL addr16l" - (EXT-SKIP-INSN) - "loadl $addr16l" - (+ OP4_LITERAL OP4MID_LOADL_L addr16l) - (set dpl (and addr16l #x00FF)) - () -) - -(dni loadh_a "LoadH addr16h" - (EXT-SKIP-INSN) - "loadh $addr16h" - (+ OP4_LITERAL OP4MID_LOADH_L addr16h) - (set dph (and addr16l #x0FF00)) - () -) - -;; THIS NO LONGER EXISTS -> Now LOADL -;;(dni bank_l "Bank literal" -;; () -;; "bank #$lit8" -;; (+ OP4_LITERAL OP4MID_BANK_L lit8) -;; (set bank lit8) -;; () -;;) - -(dni addcfr_w "Add w/carry fr,W" - () - "addc $fr,W" - (+ OP6_ADDC DIR_NOTTO_W fr) - (sequence ((QI result) (BI newcbit) (QI isLreg) (HI 16bval)) - (set newcbit (add-cflag w fr cbit)) - (set dcbit (add-dcflag w fr cbit)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (LregCheck isLreg (ifield f-reg)) - (if (eq isLreg #x1) - (sequence() - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - (set 16bval (addc HI 16bval w cbit)) - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - (set result (addc w fr cbit)) ;; else part - ) - - (set zbit (zflag result)) - (set cbit newcbit) - (set fr result)) - () -) - -(dni addcw_fr "Add w/carry W,fr" - () - "addc W,$fr" - (+ OP6_ADDC DIR_TO_W fr) - (sequence ((QI result) (BI newcbit)) - (set newcbit (add-cflag w fr cbit)) - (set dcbit (add-dcflag w fr cbit)) - (set result (addc w fr cbit)) - (set zbit (zflag result)) - (set cbit newcbit) - (set w result)) - () -) - - -(dni incsnz_fr "Skip if fr++ not zero" - () - "incsnz $fr" - (+ OP6_INCSNZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; Do 16 bit arithmetic. - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - (set fr (add fr 1)) ; Do 8 bit arithmetic. - ) - (if (not (zflag fr)) - (skip 1))) - () -) - -(dni incsnzw_fr "Skip if W=fr+1 not zero" - () - "incsnz W,$fr" - (+ OP6_INCSNZ DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (if (not (zflag w)) - (skip 1))) - () -) - -(dni mulsw_fr "Multiply W,fr (signed)" - () - "muls W,$fr" - (+ OP6_MULS DIR_TO_W fr) - (sequence ((SI tmp)) - (set tmp (mul (ext SI w) (ext SI fr))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni muluw_fr "Multiply W,fr (unsigned)" - () - "mulu W,$fr" - (+ OP6_MULU DIR_TO_W fr) - (sequence ((USI tmp)) - (set tmp (and #xFFFF (mul (zext USI w) (zext USI fr)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni decsnz_fr "Skip if fr-- not zero" - () - "decsnz $fr" - (+ OP6_DECSNZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (if (not (zflag fr)) - (skip 1))) - () -) - -(dni decsnzw_fr "Skip if W=fr-1 not zero" - () - "decsnz W,$fr" - (+ OP6_DECSNZ DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (if (not (zflag w)) - (skip 1))) - () -) - -(dni subcw_fr "Subract w/carry W,fr" - () - "subc W,$fr" - (+ OP6_SUBC DIR_TO_W fr) - (sequence ((QI result) (BI newcbit)) - (set newcbit (not (sub-cflag fr w (not cbit)))) - (set dcbit (not (sub-dcflag fr w (not cbit)))) - (set result (subc fr w (not cbit))) - (set zbit (zflag result)) - (set cbit newcbit) - (set w result)) - () -) - -(dni subcfr_w "Subtract w/carry fr,W" - () - "subc $fr,W" - (+ OP6_SUBC DIR_NOTTO_W fr) - (sequence ((QI result) (BI newcbit) (QI isLreg) (HI 16bval)) - (set newcbit (not (sub-cflag fr w (not cbit)))) - (set dcbit (not (sub-dcflag fr w (not cbit)))) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (subc HI 16bval w (not cbit))) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set result (subc fr w (not cbit))) - ) - - - (set zbit (zflag result)) - (set cbit newcbit) - (set fr result)) - () -) - - -(dni pop_fr "Pop fr" - () - "pop $fr" - (+ OP6_POP (f-dir 1) fr) - (sequence() - (set fr (c-call QI "pop")) - (c-call VOID "adjuststackptr" (const 1)) - ) - () -) - -(dni push_fr "Push fr" - () - "push $fr" - (+ OP6_POP (f-dir 0) fr) - (sequence() - (c-call "push" fr) - (c-call VOID "adjuststackptr" (const -1)) - ) - () -) - -(dni csew_fr "Skip if equal W,fr" - () - "cse W,$fr" - (+ OP6_CSE (f-dir 1) fr) - (if (eq w fr) - (skip 1)) - () -) - -(dni csnew_fr "Skip if not-equal W,fr" - () - "csne W,$fr" - (+ OP6_CSE (f-dir 0) fr) - (if (not (eq w fr)) - (skip 1)) - () -) - -;;(dni csaw_fr "Skip if W above fr" -;; ((MACH ip2022ext)) -;; "csa W,$fr" -;; (+ OP6_CSAB (f-dir 1) fr) -;; (if (gt w fr) -;; (skip 1)) -;; () -;;) - -;;(dni csbw_fr "Skip if W below fr" -;; ((MACH ip2022ext)) -;; "csb W,$fr" -;; (+ OP6_CSAB (f-dir 0) fr) -;; (if (lt w fr) -;; (skip 1)) -;; () -;;) - -(dni incsz_fr "Skip if fr++ zero" - () - "incsz $fr" - (+ OP6_INCSZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (add fr 1)) - ) - (if (zflag fr) - (skip 1))) - () -) - -(dni incszw_fr "Skip if W=fr+1 zero" - () - "incsz W,$fr" - (+ OP6_INCSZ DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (if (zflag w) - (skip 1))) - () -) - -(dni swap_fr "Swap fr nibbles" - () - "swap $fr" - (+ OP6_SWAP DIR_NOTTO_W fr) - (set fr (or (and (sll fr 4) #xf0) - (and (srl fr 4) #x0f))) - () -) - -(dni swapw_fr "Swap fr nibbles into W" - () - "swap W,$fr" - (+ OP6_SWAP DIR_TO_W fr) - (set w (or (and (sll fr 4) #xf0) - (and (srl fr 4) #x0f))) - () -) - -(dni rl_fr "Rotate fr left with carry" - () - "rl $fr" - (+ OP6_RL DIR_NOTTO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x80)) - (set newfr (or (sll fr 1) (if QI cbit 1 0))) - (set cbit (if QI newc 1 0)) - (set fr newfr)) - () -) - -(dni rlw_fr "Rotate fr left with carry into W" - () - "rl W,$fr" - (+ OP6_RL DIR_TO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x80)) - (set newfr (or (sll fr 1) (if QI cbit 1 0))) - (set cbit (if QI newc 1 0)) - (set w newfr)) - () -) - -(dni rr_fr "Rotate fr right with carry" - () - "rr $fr" - (+ OP6_RR DIR_NOTTO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x01)) - (set newfr (or (srl fr 1) (if QI cbit #x80 #x00))) - (set cbit (if QI newc 1 0)) - (set fr newfr)) - () -) - -(dni rrw_fr "Rotate fr right with carry into W" - () - "rr W,$fr" - (+ OP6_RR DIR_TO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x01)) - (set newfr (or (srl fr 1) (if QI cbit #x80 #x00))) - (set cbit (if QI newc 1 0)) - (set w newfr)) - () -) - -(dni decsz_fr "Skip if fr-- zero" - () - "decsz $fr" - (+ OP6_DECSZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (if (zflag fr) - (skip 1))) - () -) - -(dni decszw_fr "Skip if W=fr-1 zero" - () - "decsz W,$fr" - (+ OP6_DECSZ DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (if (zflag w) - (skip 1))) - () -) - -(dni inc_fr "Increment fr" - () - "inc $fr" - (+ OP6_INC DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (add fr 1)) - ) - (set zbit (zflag fr))) - () -) - -(dni incw_fr "Increment fr into w" - () - "inc W,$fr" - (+ OP6_INC DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (set zbit (zflag w))) - () -) - -(dni not_fr "Invert fr" - () - "not $fr" - (+ OP6_NOT DIR_NOTTO_W fr) - (sequence () - (set fr (inv fr)) - (set zbit (zflag fr))) - () -) - -(dni notw_fr "Invert fr into w" - () - "not W,$fr" - (+ OP6_NOT DIR_TO_W fr) - (sequence () - (set w (inv fr)) - (set zbit (zflag w))) - () -) - -(dni test_fr "Test fr" - () - "test $fr" - (+ OP6_TEST DIR_NOTTO_W fr) - (sequence () - (set zbit (zflag fr))) - () -) - -(dni movw_l "MOV W,literal" - () - "mov W,#$lit8" - (+ OP4_LITERAL OP4MID_MOV_L lit8) - (set w lit8) - () -) - -(dni movfr_w "Move/test w into fr" - () - "mov $fr,W" - (+ OP6_OTHER1 DIR_NOTTO_W fr) - (set fr w) - () -) - -(dni movw_fr "Move/test fr into w" - () - "mov W,$fr" - (+ OP6_TEST DIR_TO_W fr) - (sequence () - (set w fr) - (set zbit (zflag w))) - () -) - - -(dni addfr_w "Add fr,W" - () - "add $fr,W" - (+ OP6_ADD DIR_NOTTO_W fr) - (sequence ((QI result) (QI isLreg) (HI 16bval)) - (set cbit (add-cflag w fr 0)) - (set dcbit (add-dcflag w fr 0)) - (LregCheck isLreg (ifield f-reg)) - - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - (set 16bval (add HI (and w #xFF) 16bval)) - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - (set result (addc w fr 0)) ;; else part - ) - (set zbit (zflag result)) - (set fr result)) - () -) - -(dni addw_fr "Add W,fr" - () - "add W,$fr" - (+ OP6_ADD DIR_TO_W fr) - (sequence ((QI result)) - (set cbit (add-cflag w fr 0)) - (set dcbit (add-dcflag w fr 0)) - (set result (addc w fr 0)) - (set zbit (zflag result)) - (set w result)) - () -) - -(dni xorfr_w "XOR fr,W" - () - "xor $fr,W" - (+ OP6_XOR DIR_NOTTO_W fr) - (sequence () - (set fr (xor w fr)) - (set zbit (zflag fr))) - () -) - -(dni xorw_fr "XOR W,fr" - () - "xor W,$fr" - (+ OP6_XOR DIR_TO_W fr) - (sequence () - (set w (xor fr w)) - (set zbit (zflag w))) - () -) - -(dni andfr_w "AND fr,W" - () - "and $fr,W" - (+ OP6_AND DIR_NOTTO_W fr) - (sequence () - (set fr (and w fr)) - (set zbit (zflag fr))) - () -) - -(dni andw_fr "AND W,fr" - () - "and W,$fr" - (+ OP6_AND DIR_TO_W fr) - (sequence () - (set w (and fr w)) - (set zbit (zflag w))) - () -) - -(dni orfr_w "OR fr,W" - () - "or $fr,W" - (+ OP6_OR DIR_NOTTO_W fr) - (sequence () - (set fr (or w fr)) - (set zbit (zflag fr))) - () -) - -(dni orw_fr "OR W,fr" - () - "or W,$fr" - (+ OP6_OR DIR_TO_W fr) - (sequence () - (set w (or fr w)) - (set zbit (zflag w))) - () -) - -(dni dec_fr "Decrement fr" - () - "dec $fr" - (+ OP6_DEC DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (set zbit (zflag fr))) - () -) - -(dni decw_fr "Decrement fr into w" - () - "dec W,$fr" - (+ OP6_DEC DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (set zbit (zflag w))) - () -) - -(dni subfr_w "Sub fr,W" - () - "sub $fr,W" - (+ OP6_SUB DIR_NOTTO_W fr) - (sequence ((QI result) (QI isLreg) (HI 16bval)) - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval (and w #xFF))) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set result (subc fr w 0)) - ) - (set zbit (zflag result)) - (set fr result)) - () -) - -(dni subw_fr "Sub W,fr" - () - "sub W,$fr" - (+ OP6_SUB DIR_TO_W fr) - (sequence ((QI result)) - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (set result (subc fr w 0)) - (set zbit (zflag result)) - (set w result)) - () -) - -(dni clr_fr "Clear fr" - () - "clr $fr" - (+ OP6_OTHER2 (f-dir 1) fr) - (sequence () - (set fr 0) - (set zbit (zflag fr))) - () -) - -(dni cmpw_fr "CMP W,fr" - () - "cmp W,$fr" - (+ OP6_OTHER2 (f-dir 0) fr) - (sequence () - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (set zbit (zflag (sub w fr)))) - () -) - -(dni speed "Set speed" - () - "speed #$lit8" - (+ (f-op8 1) lit8) - (set (reg h-registers #x0E) lit8) - () -) - -(dni ireadi "Insn memory read with increment" - () - "ireadi" - (+ OP6_OTHER1 (f-op6-10low #x1D)) - (c-call "do_insn_read") - () -) - -(dni iwritei "Insn memory write with increment" - () - "iwritei" - (+ OP6_OTHER1 (f-op6-10low #x1C)) - (c-call "do_insn_write") - () -) - -(dni fread "Flash read" - () - "fread" - (+ OP6_OTHER1 (f-op6-10low #x1B)) - (c-call "do_flash_read") - () -) - -(dni fwrite "Flash write" - () - "fwrite" - (+ OP6_OTHER1 (f-op6-10low #x1A)) - (c-call "do_flash_write") - () -) - -(dni iread "Insn memory read" - () - "iread" - (+ OP6_OTHER1 (f-op6-10low #x19)) - (c-call "do_insn_read") - () -) - -(dni iwrite "Insn memory write" - () - "iwrite" - (+ OP6_OTHER1 (f-op6-10low #x18)) - (c-call "do_insn_write") - () -) - -(dni page "Set insn page" - (EXT-SKIP-INSN) - ;"page $page3" - "page $addr16p" - ;(+ OP6_OTHER1 (f-op6-7low #x2) page3) - ;(set pabits (srl page3 13)) - (+ OP6_OTHER1 (f-op6-7low #x2) addr16p) - (set pabits addr16p) - () -) - -(dni system "System call" - () - "system" - (+ OP6_OTHER1 (f-op6-10low #xff)) - (c-call "do_system") - () -) - -(dni reti "Return from interrupt" - () - "reti #$reti3" - (+ OP6_OTHER1 (f-op6-7low #x1) reti3) - (c-call "do_reti" reti3) - () -) - -(dni ret "Return" - () - "ret" - (+ OP6_OTHER1 (f-op6-10low #x07)) - (sequence ((USI new_pc)) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pabits (srl new_pc 13)) - (set pc new_pc)) - () -) - -(dni int "Software interrupt" - () - "int" - (+ OP6_OTHER1 (f-op6-10low #x6)) - (nop) - () -) - -(dni breakx "Breakpoint with extended skip" - (EXT-SKIP-INSN) - "breakx" - (+ OP6_OTHER1 (f-op6-10low #x5)) - (c-call "do_break" pc) - () -) - -(dni cwdt "Clear watchdog timer" - () - "cwdt" - (+ OP6_OTHER1 (f-op6-10low #x4)) - (c-call "do_clear_wdt") - () -) - -(dni ferase "Flash erase" - () - "ferase" - (+ OP6_OTHER1 (f-op6-10low #x3)) - (c-call "do_flash_erase") - () -) - -(dni retnp "Return, no page" - () - "retnp" - (+ OP6_OTHER1 (f-op6-10low #x2)) - (sequence ((USI new_pc)) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pc new_pc)) - () -) - -(dni break "Breakpoint" - () - "break" - (+ OP6_OTHER1 (f-op6-10low #x1)) - (c-call "do_break" pc) - () -) - -(dni nop "No operation" - () - "nop" - (+ OP6_OTHER1 (f-op6-10low #x0)) - (nop) - () -) - - -; Macro instructions -(dnmi sc "Skip on carry" - () - "sc" - (emit sb (bitno 0) (fr #xB)) ; sb status.0 -) - -(dnmi snc "Skip on no carry" - () - "snc" - (emit snb (bitno 0) (fr #xB)) ; snb status.0 -) - -(dnmi sz "Skip on zero" - () - "sz" - (emit sb (bitno 2) (fr #xB)) ; sb status.2 -) - -(dnmi snz "Skip on no zero" - () - "snz" - (emit snb (bitno 2) (fr #xB)) ; snb status.2 -) - -(dnmi skip "Skip always" - (SKIPA) - "skip" - (emit snb (bitno 0) (fr 9)) ; snb pcl.0 | (pcl&1)<<12 -) - -(dnmi skipb "Skip always" - (SKIPA) - "skip" - (emit sb (bitno 0) (fr 9)) ; sb pcl.0 | (pcl&1)<<12 -) - diff --git a/cpu/ip2k.opc b/cpu/ip2k.opc deleted file mode 100644 index c2d505a..0000000 --- a/cpu/ip2k.opc +++ /dev/null @@ -1,616 +0,0 @@ -/* IP2K opcode support. -*- C -*- - Copyright (C) 2000 Red Hat, Inc. - Copyright (C) 2002, 2005 Free Software Foundation, Inc. - This file is part of CGEN. */ - -/* - Each section is delimited with start and end markers. - - -opc.h additions use: "-- opc.h" - -opc.c additions use: "-- opc.c" - -asm.c additions use: "-- asm.c" - -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Check applicability of instructions against machines. */ -#define CGEN_VALIDATE_INSN_SUPPORTED - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf, value) \ - (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) - -#define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn) - -extern unsigned int ip2k_asm_hash (const char *); -extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); - -/* -- opc.c */ - -#include "safe-ctype.h" - -/* A better hash function for instruction mnemonics. */ -unsigned int -ip2k_asm_hash (const char* insn) -{ - unsigned int hash; - const char* m = insn; - - for (hash = 0; *m && ! ISSPACE (*m); m++) - hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); - - /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ - - return hash % CGEN_ASM_HASH_SIZE; -} - - -/* Special check to ensure that instruction exists for given machine. */ - -int -ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - - /* No mach attribute? Assume it's supported for all machs. */ - if (machs == 0) - return 1; - - return (machs & cd->machs) != 0; -} - - -/* -- asm.c */ - -static const char * -parse_fr (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - const char *old_strp; - char *afteroffset; - enum cgen_parse_operand_result result_type; - bfd_vma value; - extern CGEN_KEYWORD ip2k_cgen_opval_register_names; - bfd_vma tempvalue; - - old_strp = *strp; - afteroffset = NULL; - - /* Check here to see if you're about to try parsing a w as the first arg - and return an error if you are. */ - if ((strncmp (*strp, "w", 1) == 0) || (strncmp (*strp, "W", 1) == 0)) - { - (*strp)++; - - if ((strncmp (*strp, ",", 1) == 0) || ISSPACE (**strp)) - { - /* We've been passed a w. Return with an error message so that - cgen will try the next parsing option. */ - errmsg = _("W keyword invalid in FR operand slot."); - return errmsg; - } - *strp = old_strp; - } - - /* Attempt parse as register keyword. */ - errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, - (long *) valuep); - if (*strp != NULL - && errmsg == NULL) - return errmsg; - - /* Attempt to parse for "(IP)". */ - afteroffset = strstr (*strp, "(IP)"); - - if (afteroffset == NULL) - /* Make sure it's not in lower case. */ - afteroffset = strstr (*strp, "(ip)"); - - if (afteroffset != NULL) - { - if (afteroffset != *strp) - { - /* Invalid offset present. */ - errmsg = _("offset(IP) is not a valid form"); - return errmsg; - } - else - { - *strp += 4; - *valuep = 0; - errmsg = NULL; - return errmsg; - } - } - - /* Attempt to parse for DP. ex: mov w, offset(DP) - mov offset(DP),w */ - - /* Try parsing it as an address and see what comes back. */ - afteroffset = strstr (*strp, "(DP)"); - - if (afteroffset == NULL) - /* Maybe it's in lower case. */ - afteroffset = strstr (*strp, "(dp)"); - - if (afteroffset != NULL) - { - if (afteroffset == *strp) - { - /* No offset present. Use 0 by default. */ - tempvalue = 0; - errmsg = NULL; - } - else - errmsg = cgen_parse_address (cd, strp, opindex, - BFD_RELOC_IP2K_FR_OFFSET, - & result_type, & tempvalue); - - if (errmsg == NULL) - { - if (tempvalue <= 127) - { - /* Value is ok. Fix up the first 2 bits and return. */ - *valuep = 0x0100 | tempvalue; - *strp += 4; /* Skip over the (DP) in *strp. */ - return errmsg; - } - else - { - /* Found something there in front of (DP) but it's out - of range. */ - errmsg = _("(DP) offset out of range."); - return errmsg; - } - } - } - - - /* Attempt to parse for SP. ex: mov w, offset(SP) - mov offset(SP), w. */ - afteroffset = strstr (*strp, "(SP)"); - - if (afteroffset == NULL) - /* Maybe it's in lower case. */ - afteroffset = strstr (*strp, "(sp)"); - - if (afteroffset != NULL) - { - if (afteroffset == *strp) - { - /* No offset present. Use 0 by default. */ - tempvalue = 0; - errmsg = NULL; - } - else - errmsg = cgen_parse_address (cd, strp, opindex, - BFD_RELOC_IP2K_FR_OFFSET, - & result_type, & tempvalue); - - if (errmsg == NULL) - { - if (tempvalue <= 127) - { - /* Value is ok. Fix up the first 2 bits and return. */ - *valuep = 0x0180 | tempvalue; - *strp += 4; /* Skip over the (SP) in *strp. */ - return errmsg; - } - else - { - /* Found something there in front of (SP) but it's out - of range. */ - errmsg = _("(SP) offset out of range."); - return errmsg; - } - } - } - - /* Attempt to parse as an address. */ - *strp = old_strp; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9, - & result_type, & value); - if (errmsg == NULL) - { - *valuep = value; - - /* If a parenthesis is found, warn about invalid form. */ - if (**strp == '(') - errmsg = _("illegal use of parentheses"); - - /* If a numeric value is specified, ensure that it is between - 1 and 255. */ - else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - if (value < 0x1 || value > 0xff) - errmsg = _("operand out of range (not between 1 and 255)"); - } - } - return errmsg; -} - -static const char * -parse_addr16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16H) - code = BFD_RELOC_IP2K_HI8DATA; - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16L) - code = BFD_RELOC_IP2K_LO8DATA; - else - { - /* Something is very wrong. opindex has to be one of the above. */ - errmsg = _("parse_addr16: invalid opindex."); - return errmsg; - } - - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - /* We either have a relocation or a number now. */ - if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* We got a number back. */ - if (code == BFD_RELOC_IP2K_HI8DATA) - value >>= 8; - else - /* code = BFD_RELOC_IP2K_LOW8DATA. */ - value &= 0x00FF; - } - *valuep = value; - } - - return errmsg; -} - -static const char * -parse_addr16_cjp (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) - code = BFD_RELOC_IP2K_ADDR16CJP; - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) - code = BFD_RELOC_IP2K_PAGE3; - - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - if ((value & 0x1) == 0) /* If the address is even .... */ - { - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) - *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) - *valuep = (value >> 14) & 0x7; - } - else - errmsg = _("Byte address required. - must be even."); - } - else if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) - { - /* This will happen for things like (s2-s1) where s2 and s1 - are labels. */ - *valuep = value; - } - else - errmsg = _("cgen_parse_address returned a symbol. Literal required."); - } - return errmsg; -} - -static const char * -parse_lit8 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - /* Parse %OP relocating operators. */ - if (strncmp (*strp, "%bank", 5) == 0) - { - *strp += 5; - code = BFD_RELOC_IP2K_BANK; - } - else if (strncmp (*strp, "%lo8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_LO8DATA; - } - else if (strncmp (*strp, "%hi8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_HI8DATA; - } - else if (strncmp (*strp, "%ex8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_EX8DATA; - } - else if (strncmp (*strp, "%lo8insn", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_LO8INSN; - } - else if (strncmp (*strp, "%hi8insn", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_HI8INSN; - } - - /* Parse %op operand. */ - if (code != BFD_RELOC_NONE) - { - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if ((errmsg == NULL) && - (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED)) - errmsg = _("percent-operator operand is not a symbol"); - - *valuep = value; - } - /* Parse as a number. */ - else - { - errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); - - /* Truncate to eight bits to accept both signed and unsigned input. */ - if (errmsg == NULL) - *valuep &= 0xFF; - } - - return errmsg; -} - -static const char * -parse_bit3 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - char mode = 0; - long count = 0; - unsigned long value; - - if (strncmp (*strp, "%bit", 4) == 0) - { - *strp += 4; - mode = 1; - } - else if (strncmp (*strp, "%msbbit", 7) == 0) - { - *strp += 7; - mode = 1; - } - else if (strncmp (*strp, "%lsbbit", 7) == 0) - { - *strp += 7; - mode = 2; - } - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - if (errmsg) - return errmsg; - - if (mode) - { - value = * valuep; - if (value == 0) - { - errmsg = _("Attempt to find bit index of 0"); - return errmsg; - } - - if (mode == 1) - { - count = 31; - while ((value & 0x80000000) == 0) - { - count--; - value <<= 1; - } - } - else if (mode == 2) - { - count = 0; - while ((value & 0x00000001) == 0) - { - count++; - value >>= 1; - } - } - - *valuep = count; - } - - return errmsg; -} - -/* -- dis.c */ - -static void -print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - extern CGEN_KEYWORD ip2k_cgen_opval_register_names; - long offsettest; - long offsetvalue; - - if (value == 0) /* This is (IP). */ - { - (*info->fprintf_func) (info->stream, "%s", "(IP)"); - return; - } - - offsettest = value >> 7; - offsetvalue = value & 0x7F; - - /* Check to see if first two bits are 10 -> (DP). */ - if (offsettest == 2) - { - if (offsetvalue == 0) - (*info->fprintf_func) (info->stream, "%s","(DP)"); - else - (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue, "(DP)"); - return; - } - - /* Check to see if first two bits are 11 -> (SP). */ - if (offsettest == 3) - { - if (offsetvalue == 0) - (*info->fprintf_func) (info->stream, "%s", "(SP)"); - else - (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue,"(SP)"); - return; - } - - /* Attempt to print as a register keyword. */ - ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value); - - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - /* Print as an address literal. */ - (*info->fprintf_func) (info->stream, "$%02lx", value); -} - -static void -print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%lx", value); -} - -static void -print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%02lx", value); -} - -static void -print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - /* This is a loadh instruction. Shift the value to the left - by 8 bits so that disassembled code will reassemble properly. */ - value = ((value << 8) & 0xFF00); - - (*info->fprintf_func) (info->stream, "$%04lx", value); -} - -static void -print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%04lx", value); -} - -static void -print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - value = ((value << 14) & 0x1C000); - ;value = (value & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05lx", value); -} - -static void -print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - value = ((value << 1) & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05lx", value); -} - -static void -print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "%ld", value); -} - - - -/* -- */ - diff --git a/cpu/mep-avc.cpu b/cpu/mep-avc.cpu deleted file mode 100644 index cb19dc6..0000000 --- a/cpu/mep-avc.cpu +++ /dev/null @@ -1,1406 +0,0 @@ -; Toshiba MeP AVC Coprocessor description. -*- Scheme -*- -; Copyright (C) 2005 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. -; -; This file was customized based upon the output of a2cgen 0.42 - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires 16 and 32 bit insns. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro avc-core-isa () (ISA ext_core1)) -(define-pmacro avc-16-isa () (ISA ext_cop1_16)) -(define-pmacro avc-32-isa () (ISA ext_cop1_32)) -(define-pmacro all-avc-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32)) -; end-isas - -(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-core-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-16-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-32-isa) xsyntax xformat xsemantics xtiming)) - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-avc) - (comment "32-bit coprocessor registers for avc coprocessor") - (attrs VIRTUAL all-avc-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-avc) - (comment "Coprocessor control registers for avc coprocessor") - (attrs VIRTUAL all-avc-isas) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - ($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0) - ($cbcr 1) - (.unsplice (.map -ccr-reg-pair (.iota 6))) - ) - ) -) -(dnop avccopCCR5 "Audio Copro Accumulator" (all-avc-isas) h-ccr 5) -(dnop avccopCCR4 "Audio Copro Accumulator" (all-avc-isas) h-ccr 4) -(dnop avccopCCR3 "Audio Copro Accumulator" (all-avc-isas) h-ccr 3) -(dnop avccopCCR2 "Audio Copro Accumulator" (all-avc-isas) h-ccr 2) -(dnop avccopCCR1 "Audio Copro Branch Condition Register" (all-avc-isas) h-ccr 1) -(dnop avccopCCR0 "Audio Copro Shift-Amount Register" (all-avc-isas) h-ccr 0) - -; instruction field and operand definitions -(dnf f-avc-v3sub4u0 "sub opecode field" (avc-32-isa) 0 4) -(dnf f-avc-v1sub4u0 "sub opecode field" (avc-16-isa) 0 4) -(dnf f-avc-v3Rn "register field" (avc-32-isa) 4 4) -(dnop avcv3Rn "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rn) -(dnf f-avc-v3CCRn "register field" (avc-32-isa) 4 4) -(define-full-operand avcv3CCRn "the operand definition" (avc-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc-v3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ()) -(df f-avc-v3Imm16s4x24e32-hi "split immediate field hi" (avc-32-isa) 4 8 INT #f #f) -(df f-avc-v3Imm16s4x24e32-lo "split immediate field lo" (avc-32-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc-v3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc-32-isa) - (mode INT) - (subfields f-avc-v3Imm16s4x24e32-hi f-avc-v3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc-v3Imm16s4x24e32) 8)) - (set (ifield f-avc-v3Imm16s4x24e32-lo) (and (ifield f-avc-v3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc-v3Imm16s4x24e32) - (or (sll (ifield f-avc-v3Imm16s4x24e32-hi) 8) (ifield f-avc-v3Imm16s4x24e32-lo)))) - ) -(dnop avcv3Imm16s4x24e32 "the operand definition" (avc-32-isa) h-sint f-avc-v3Imm16s4x24e32) -(dnf f-avc-v3CRn "register field" (avc-32-isa) 4 4) -(define-full-operand avcv3CRn "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRn ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1CRq "register field" (avc-16-isa) 4 4) -(define-full-operand avcv1CRq "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u4 "sub opecode field" (avc-16-isa) 4 4) -(dnf f-avc-c3Rn "register field" (avc-core-isa) 4 4) -(dnop avcc3Rn "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rn) -(dnf f-avc-c3CCRn "register field" (avc-core-isa) 4 4) -(define-full-operand avcc3CCRn "the operand definition" (avc-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc-c3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ()) -(df f-avc-c3Imm16s4x24e32-hi "split immediate field hi" (avc-core-isa) 4 8 INT #f #f) -(df f-avc-c3Imm16s4x24e32-lo "split immediate field lo" (avc-core-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc-c3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc-core-isa) - (mode INT) - (subfields f-avc-c3Imm16s4x24e32-hi f-avc-c3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc-c3Imm16s4x24e32) 8)) - (set (ifield f-avc-c3Imm16s4x24e32-lo) (and (ifield f-avc-c3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc-c3Imm16s4x24e32) - (or (sll (ifield f-avc-c3Imm16s4x24e32-hi) 8) (ifield f-avc-c3Imm16s4x24e32-lo)))) - ) -(dnop avcc3Imm16s4x24e32 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm16s4x24e32) -(dnf f-avc-c3CRn "register field" (avc-core-isa) 4 4) -(define-full-operand avcc3CRn "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRn ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u4 "sub opecode field" (avc-core-isa) 4 4) -(dnf f-avc-v3Rm "register field" (avc-32-isa) 8 4) -(dnop avcv3Rm "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rm) -(df f-avc-v1Imm5u8 "immediate field" (avc-16-isa) 8 5 UINT #f #f) -(dnop avcv1Imm5u8 "the operand definition" (avc-16-isa) h-uint f-avc-v1Imm5u8) -(df f-avc-v1Imm6s8 "immediate field" (avc-16-isa) 8 6 INT #f #f) -(dnop avcv1Imm6s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm6s8) -(df f-avc-v1Imm8s8 "immediate field" (avc-16-isa) 8 8 INT #f #f) -(dnop avcv1Imm8s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm8s8) -(dnf f-avc-v1CRp "register field" (avc-16-isa) 8 4) -(define-full-operand avcv1CRp "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRp ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u8 "sub opecode field" (avc-16-isa) 8 4) -(dnf f-avc-c3Rm "register field" (avc-core-isa) 8 4) -(dnop avcc3Rm "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rm) -(dnf f-avc-c3sub4u8 "sub opecode field" (avc-core-isa) 8 4) -(dnf f-avc-v3sub4u12 "sub opecode field" (avc-32-isa) 12 4) -(dnf f-avc-v1CRo "register field" (avc-16-isa) 12 4) -(define-full-operand avcv1CRo "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRo ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u12 "sub opecode field" (avc-16-isa) 12 4) -(dnf f-avc-v1sub3u13 "sub opecode field" (avc-16-isa) 13 3) -(dnf f-avc-v1sub2u14 "sub opecode field" (avc-16-isa) 14 2) -(dnf f-avc-v3sub4u16 "sub opecode field" (avc-32-isa) 16 4) -(dnf f-avc-c3sub4u16 "sub opecode field" (avc-core-isa) 16 4) -(dnf f-avc-v3CRq "register field" (avc-32-isa) 20 4) -(define-full-operand avcv3CRq "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v3sub4u20 "sub opecode field" (avc-32-isa) 20 4) -(dnf f-avc-c3CRq "register field" (avc-core-isa) 20 4) -(define-full-operand avcc3CRq "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u20 "sub opecode field" (avc-core-isa) 20 4) -(dnf f-avc-v3sub4u24 "sub opecode field" (avc-32-isa) 24 4) -(df f-avc-c3Imm5u24 "immediate field" (avc-core-isa) 24 5 UINT #f #f) -(dnop avcc3Imm5u24 "the operand definition" (avc-core-isa) h-uint f-avc-c3Imm5u24) -(df f-avc-c3Imm6s24 "immediate field" (avc-core-isa) 24 6 INT #f #f) -(dnop avcc3Imm6s24 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm6s24) -(dnf f-avc-c3CRp "register field" (avc-core-isa) 24 4) -(define-full-operand avcc3CRp "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRp ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u24 "sub opecode field" (avc-core-isa) 24 4) -(dnf f-avc-v3sub4u28 "sub opecode field" (avc-32-isa) 28 4) -(dnf f-avc-c3CRo "register field" (avc-core-isa) 28 4) -(define-full-operand avcc3CRo "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRo ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u28 "sub opecode field" (avc-core-isa) 28 4) -(dnf f-avc-c3sub3u29 "sub opecode field" (avc-core-isa) 29 3) -(dnf f-avc-c3sub2u30 "sub opecode field" (avc-core-isa) 30 2) - -; instruction definitions -(dncpi cnop_avc_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop")) - "cnop" -(+ MAJ_15 (f-sub4 7) (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(c-call "check_option_cp" pc) - ()) -(dncpi cmov1_avc_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1")) - "cmov $avcc3CRn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3CRn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRn avcc3Rm) -) - ()) -(dncpi cmov2_avc_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2")) - "cmov $avcc3Rm,$avcc3CRn" -(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CRn (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3Rm avcc3CRn) -) - ()) -(dncpi cmovi_avc_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi")) - "cmovi $avcc3CRq,$avcc3Imm16s4x24e32" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm16s4x24e32 (f-avc-c3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI avcc3Imm16s4x24e32)) -) - ()) -(dncpi cmovc1_avc_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1")) - "cmovc $avcc3CCRn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3CCRn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CCRn avcc3Rm) -) - ()) -(dncpi cmovc2_avc_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2")) - "cmovc $avcc3Rm,$avcc3CCRn" -(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CCRn (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3Rm avcc3CCRn) -) - ()) -(dncpi cmov_avc_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov")) - "cmov $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq avcc3CRp) -) - ()) -(dncpi cadd3_avc_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3")) - "cadd3 $avcc3CRo,$avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRo avcc3CRq avcc3CRp (f-avc-c3sub4u16 #x3) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRo (add avcc3CRq avcc3CRp)) -) - ()) -(dncpi caddi_avc_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi")) - "caddi $avcc3CRq,$avcc3Imm6s24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm6s24 (f-avc-c3sub2u30 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (add avcc3CRq (ext SI avcc3Imm6s24))) -) - ()) -(dncpi csub_avc_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub")) - "csub $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sub avcc3CRq avcc3CRp)) -) - ()) -(dncpi cneg_avc_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg")) - "cneg $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (neg avcc3CRp)) -) - ()) -(dncpi cextb_avc_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb")) - "cextb $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI (and QI (srl avcc3CRq 0) #xff))) -) - ()) -(dncpi cexth_avc_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth")) - "cexth $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI (and HI (srl avcc3CRq 0) #xffff))) -) - ()) -(dncpi cextub_avc_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub")) - "cextub $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x8) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (zext SI (and QI (srl avcc3CRq 0) #xff))) -) - ()) -(dncpi cextuh_avc_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh")) - "cextuh $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (zext SI (and HI (srl avcc3CRq 0) #xffff))) -) - ()) -(dncpi cscltz_avc_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz")) - "cscltz $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dncpi cldz_avc_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz")) - "cldz $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (and avcc3CRp #x80000000) (set avcc3CRq 0) -(if (and avcc3CRp #x40000000) (set avcc3CRq 1) -(if (and avcc3CRp #x20000000) (set avcc3CRq 2) -(if (and avcc3CRp #x10000000) (set avcc3CRq 3) -(if (and avcc3CRp #x8000000) (set avcc3CRq 4) -(if (and avcc3CRp #x4000000) (set avcc3CRq 5) -(if (and avcc3CRp #x2000000) (set avcc3CRq 6) -(if (and avcc3CRp #x1000000) (set avcc3CRq 7) -(if (and avcc3CRp #x800000) (set avcc3CRq 8) -(if (and avcc3CRp #x400000) (set avcc3CRq 9) -(if (and avcc3CRp #x200000) (set avcc3CRq 10) -(if (and avcc3CRp #x100000) (set avcc3CRq 11) -(if (and avcc3CRp #x80000) (set avcc3CRq 12) -(if (and avcc3CRp #x40000) (set avcc3CRq 13) -(if (and avcc3CRp #x20000) (set avcc3CRq 14) -(if (and avcc3CRp #x10000) (set avcc3CRq 15) -(if (and avcc3CRp #x8000) (set avcc3CRq 16) -(if (and avcc3CRp #x4000) (set avcc3CRq 17) -(if (and avcc3CRp #x2000) (set avcc3CRq 18) -(if (and avcc3CRp #x1000) (set avcc3CRq 19) -(if (and avcc3CRp #x800) (set avcc3CRq 20) -(if (and avcc3CRp #x400) (set avcc3CRq 21) -(if (and avcc3CRp #x200) (set avcc3CRq 22) -(if (and avcc3CRp #x100) (set avcc3CRq 23) -(if (and avcc3CRp #x80) (set avcc3CRq 24) -(if (and avcc3CRp #x40) (set avcc3CRq 25) -(if (and avcc3CRp #x20) (set avcc3CRq 26) -(if (and avcc3CRp #x10) (set avcc3CRq 27) -(if (and avcc3CRp #x8) (set avcc3CRq 28) -(if (and avcc3CRp #x4) (set avcc3CRq 29) -(if (and avcc3CRp #x2) (set avcc3CRq 30) -(if (and avcc3CRp #x1) (set avcc3CRq 31) -(set avcc3CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dncpi cabs_avc_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs")) - "cabs $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (abs (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1)))) -) - ()) -(dncpi cad1s_avc_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s")) - "cad1s $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (add avcc3CRq avcc3CRp) 1))) -(set avcc3CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dncpi csb1s_avc_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s")) - "csb1s $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1))) -(set avcc3CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dncpi cmin_avc_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin")) - "cmin $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cmax_avc_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax")) - "cmax $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cminu_avc_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu")) - "cminu $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cmaxu_avc_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu")) - "cmaxu $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xb) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cclipi_avc_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi")) - "cclipi $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x4) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0) -(sequence() (set tmp0 (sll 1 (sub avcc3Imm5u24 1))) -(set tmp1 (sub (subword SI tmp0 1) 1)) -(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp1 1))) (set avcc3CRq (subword SI tmp1 1)) -(if (lt (ext SI avcc3CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcc3CRq (neg (subword SI tmp0 1))) -(set avcc3CRq avcc3CRq) -) -) -) -) -) - ()) -(dncpi cclipiu_avc_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu")) - "cclipiu $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x5) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0) -(sequence() (set tmp0 (sub (sll 1 avcc3Imm5u24) 1)) -(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp0 1))) (set avcc3CRq (subword SI tmp0 1)) -(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avcc3CRq 0) -(set avcc3CRq avcc3CRq) -) -) -) -) -) - ()) -(dncpi cor_avc_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor")) - "cor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (or avcc3CRq avcc3CRp)) -) - ()) -(dncpi cand_avc_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand")) - "cand $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (and avcc3CRq avcc3CRp)) -) - ()) -(dncpi cxor_avc_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor")) - "cxor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (xor avcc3CRq avcc3CRp)) -) - ()) -(dncpi cnor_avc_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor")) - "cnor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (inv (or avcc3CRq avcc3CRp))) -) - ()) -(dncpi csra_avc_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra")) - "csra $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sra avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csrl_avc_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl")) - "csrl $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (srl avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csll_avc_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll")) - "csll $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sll avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csrai_avc_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai")) - "csrai $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x2) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sra avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi csrli_avc_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli")) - "csrli $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x3) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (srl avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi cslli_avc_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli")) - "cslli $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x6) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sll avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi cfsft_avc_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft")) - "cfsft $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avcc3CRq)) 32) (zext DI avcc3CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta0_avc_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0")) - "cfsfta0 $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta1_avc_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1")) - "cfsfta1 $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cmula0_avc_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0")) - "cmula0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat0)) (c-call "check_option_cp" pc) -(set concat0 (mul (ext DI avcc3CRq) (ext DI avcc3CRp))) -(set avccopCCR2 (subword SI concat0 0)) -(set avccopCCR3 (subword SI concat0 1)) -) - ()) -(dncpi cmulua0_avc_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0")) - "cmulua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat1)) (c-call "check_option_cp" pc) -(set concat1 (mul (zext DI avcc3CRq) (zext DI avcc3CRp))) -(set avccopCCR2 (subword SI concat1 0)) -(set avccopCCR3 (subword SI concat1 1)) -) - ()) -(dncpi cnmula0_avc_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0")) - "cnmula0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat2)) (c-call "check_option_cp" pc) -(set concat2 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat2 0)) -(set avccopCCR3 (subword SI concat2 1)) -) - ()) -(dncpi cmada0_avc_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0")) - "cmada0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat3)) (c-call "check_option_cp" pc) -(set concat3 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat3 0)) -(set avccopCCR3 (subword SI concat3 1)) -) - ()) -(dncpi cmadua0_avc_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0")) - "cmadua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat4)) (c-call "check_option_cp" pc) -(set concat4 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat4 0)) -(set avccopCCR3 (subword SI concat4 1)) -) - ()) -(dncpi cmsba0_avc_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0")) - "cmsba0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat5)) (c-call "check_option_cp" pc) -(set concat5 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat5 0)) -(set avccopCCR3 (subword SI concat5 1)) -) - ()) -(dncpi cmsbua0_avc_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0")) - "cmsbua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat6)) (c-call "check_option_cp" pc) -(set concat6 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat6 0)) -(set avccopCCR3 (subword SI concat6 1)) -) - ()) -(dncpi cmula1_avc_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1")) - "cmula1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat7)) (c-call "check_option_cp" pc) -(set concat7 (mul (ext DI avcc3CRq) (ext DI avcc3CRp))) -(set avccopCCR4 (subword SI concat7 0)) -(set avccopCCR5 (subword SI concat7 1)) -) - ()) -(dncpi cmulua1_avc_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1")) - "cmulua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat8)) (c-call "check_option_cp" pc) -(set concat8 (mul (zext DI avcc3CRq) (zext DI avcc3CRp))) -(set avccopCCR4 (subword SI concat8 0)) -(set avccopCCR5 (subword SI concat8 1)) -) - ()) -(dncpi cnmula1_avc_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1")) - "cnmula1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat9)) (c-call "check_option_cp" pc) -(set concat9 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat9 0)) -(set avccopCCR5 (subword SI concat9 1)) -) - ()) -(dncpi cmada1_avc_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1")) - "cmada1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat10)) (c-call "check_option_cp" pc) -(set concat10 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat10 0)) -(set avccopCCR5 (subword SI concat10 1)) -) - ()) -(dncpi cmadua1_avc_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1")) - "cmadua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat11)) (c-call "check_option_cp" pc) -(set concat11 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat11 0)) -(set avccopCCR5 (subword SI concat11 1)) -) - ()) -(dncpi cmsba1_avc_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1")) - "cmsba1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat12)) (c-call "check_option_cp" pc) -(set concat12 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat12 0)) -(set avccopCCR5 (subword SI concat12 1)) -) - ()) -(dncpi cmsbua1_avc_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1")) - "cmsbua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat13)) (c-call "check_option_cp" pc) -(set concat13 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat13 0)) -(set avccopCCR5 (subword SI concat13 1)) -) - ()) -(dncpi xmula0_avc_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0")) - "xmula0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat14)) (c-call "check_option_cp" pc) -(set concat14 (mul (ext DI avcc3Rn) (ext DI avcc3Rm))) -(set avccopCCR2 (subword SI concat14 0)) -(set avccopCCR3 (subword SI concat14 1)) -) - ()) -(dncpi xmulua0_avc_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0")) - "xmulua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat15)) (c-call "check_option_cp" pc) -(set concat15 (mul (zext DI avcc3Rn) (zext DI avcc3Rm))) -(set avccopCCR2 (subword SI concat15 0)) -(set avccopCCR3 (subword SI concat15 1)) -) - ()) -(dncpi xnmula0_avc_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0")) - "xnmula0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat16)) (c-call "check_option_cp" pc) -(set concat16 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat16 0)) -(set avccopCCR3 (subword SI concat16 1)) -) - ()) -(dncpi xmada0_avc_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0")) - "xmada0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat17)) (c-call "check_option_cp" pc) -(set concat17 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat17 0)) -(set avccopCCR3 (subword SI concat17 1)) -) - ()) -(dncpi xmadua0_avc_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0")) - "xmadua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat18)) (c-call "check_option_cp" pc) -(set concat18 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat18 0)) -(set avccopCCR3 (subword SI concat18 1)) -) - ()) -(dncpi xmsba0_avc_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0")) - "xmsba0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat19)) (c-call "check_option_cp" pc) -(set concat19 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat19 0)) -(set avccopCCR3 (subword SI concat19 1)) -) - ()) -(dncpi xmsbua0_avc_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat20)) (c-call "check_option_cp" pc) -(set concat20 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat20 0)) -(set avccopCCR3 (subword SI concat20 1)) -) - ()) -(dncpi xmula1_avc_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1")) - "xmula1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat21)) (c-call "check_option_cp" pc) -(set concat21 (mul (ext DI avcc3Rn) (ext DI avcc3Rm))) -(set avccopCCR4 (subword SI concat21 0)) -(set avccopCCR5 (subword SI concat21 1)) -) - ()) -(dncpi xmulua1_avc_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1")) - "xmulua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat22)) (c-call "check_option_cp" pc) -(set concat22 (mul (zext DI avcc3Rn) (zext DI avcc3Rm))) -(set avccopCCR4 (subword SI concat22 0)) -(set avccopCCR5 (subword SI concat22 1)) -) - ()) -(dncpi xnmula1_avc_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1")) - "xnmula1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat23)) (c-call "check_option_cp" pc) -(set concat23 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat23 0)) -(set avccopCCR5 (subword SI concat23 1)) -) - ()) -(dncpi xmada1_avc_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1")) - "xmada1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat24)) (c-call "check_option_cp" pc) -(set concat24 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat24 0)) -(set avccopCCR5 (subword SI concat24 1)) -) - ()) -(dncpi xmadua1_avc_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1")) - "xmadua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat25)) (c-call "check_option_cp" pc) -(set concat25 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat25 0)) -(set avccopCCR5 (subword SI concat25 1)) -) - ()) -(dncpi xmsba1_avc_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1")) - "xmsba1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat26)) (c-call "check_option_cp" pc) -(set concat26 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat26 0)) -(set avccopCCR5 (subword SI concat26 1)) -) - ()) -(dncpi xmsbua1_avc_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat27)) (c-call "check_option_cp" pc) -(set concat27 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat27 0)) -(set avccopCCR5 (subword SI concat27 1)) -) - ()) -(dn16i cnop_avc_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop")) - "cnop" -(+ (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u4 #x0) (f-avc-v1sub4u0 #x0)) -(c-call "check_option_cp" pc) - ()) -(dnmi cpnop16_avc_v1 "cpnop16" -(avc-16-isa NO-DIS) -"cpnop16" -(emit cnop_avc_v1) -) -(dn16i cmov_avc_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov")) - "cmov $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq avcv1CRp) -) - ()) -(dn16i cmovi_avc_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi")) - "cmovi $avcv1CRq,$avcv1Imm8s8" -(+ avcv1CRq avcv1Imm8s8 (f-avc-v1sub4u0 #x2)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI avcv1Imm8s8)) -) - ()) -(dn16i cadd3_avc_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3")) - "cadd3 $avcv1CRo,$avcv1CRq,$avcv1CRp" -(+ avcv1CRo avcv1CRq avcv1CRp (f-avc-v1sub4u0 #x3)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRo (add avcv1CRq avcv1CRp)) -) - ()) -(dn16i caddi_avc_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi")) - "caddi $avcv1CRq,$avcv1Imm6s8" -(+ avcv1CRq avcv1Imm6s8 (f-avc-v1sub2u14 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (add avcv1CRq (ext SI avcv1Imm6s8))) -) - ()) -(dn16i csub_avc_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub")) - "csub $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sub avcv1CRq avcv1CRp)) -) - ()) -(dn16i cneg_avc_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg")) - "cneg $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (neg avcv1CRp)) -) - ()) -(dn16i cextb_avc_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb")) - "cextb $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI (and QI (srl avcv1CRq 0) #xff))) -) - ()) -(dn16i cexth_avc_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth")) - "cexth $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x2) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI (and HI (srl avcv1CRq 0) #xffff))) -) - ()) -(dn16i cextub_avc_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub")) - "cextub $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x8) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (zext SI (and QI (srl avcv1CRq 0) #xff))) -) - ()) -(dn16i cextuh_avc_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh")) - "cextuh $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (zext SI (and HI (srl avcv1CRq 0) #xffff))) -) - ()) -(dn16i cscltz_avc_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz")) - "cscltz $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dn16i cldz_avc_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz")) - "cldz $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (and avcv1CRp #x80000000) (set avcv1CRq 0) -(if (and avcv1CRp #x40000000) (set avcv1CRq 1) -(if (and avcv1CRp #x20000000) (set avcv1CRq 2) -(if (and avcv1CRp #x10000000) (set avcv1CRq 3) -(if (and avcv1CRp #x8000000) (set avcv1CRq 4) -(if (and avcv1CRp #x4000000) (set avcv1CRq 5) -(if (and avcv1CRp #x2000000) (set avcv1CRq 6) -(if (and avcv1CRp #x1000000) (set avcv1CRq 7) -(if (and avcv1CRp #x800000) (set avcv1CRq 8) -(if (and avcv1CRp #x400000) (set avcv1CRq 9) -(if (and avcv1CRp #x200000) (set avcv1CRq 10) -(if (and avcv1CRp #x100000) (set avcv1CRq 11) -(if (and avcv1CRp #x80000) (set avcv1CRq 12) -(if (and avcv1CRp #x40000) (set avcv1CRq 13) -(if (and avcv1CRp #x20000) (set avcv1CRq 14) -(if (and avcv1CRp #x10000) (set avcv1CRq 15) -(if (and avcv1CRp #x8000) (set avcv1CRq 16) -(if (and avcv1CRp #x4000) (set avcv1CRq 17) -(if (and avcv1CRp #x2000) (set avcv1CRq 18) -(if (and avcv1CRp #x1000) (set avcv1CRq 19) -(if (and avcv1CRp #x800) (set avcv1CRq 20) -(if (and avcv1CRp #x400) (set avcv1CRq 21) -(if (and avcv1CRp #x200) (set avcv1CRq 22) -(if (and avcv1CRp #x100) (set avcv1CRq 23) -(if (and avcv1CRp #x80) (set avcv1CRq 24) -(if (and avcv1CRp #x40) (set avcv1CRq 25) -(if (and avcv1CRp #x20) (set avcv1CRq 26) -(if (and avcv1CRp #x10) (set avcv1CRq 27) -(if (and avcv1CRp #x8) (set avcv1CRq 28) -(if (and avcv1CRp #x4) (set avcv1CRq 29) -(if (and avcv1CRp #x2) (set avcv1CRq 30) -(if (and avcv1CRp #x1) (set avcv1CRq 31) -(set avcv1CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dn16i cabs_avc_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs")) - "cabs $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (abs (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1)))) -) - ()) -(dn16i cad1s_avc_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s")) - "cad1s $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (add avcv1CRq avcv1CRp) 1))) -(set avcv1CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dn16i csb1s_avc_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s")) - "csb1s $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1))) -(set avcv1CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dn16i cmin_avc_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin")) - "cmin $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cmax_avc_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax")) - "cmax $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cminu_avc_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu")) - "cminu $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cmaxu_avc_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu")) - "cmaxu $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xb) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cclipi_avc_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi")) - "cclipi $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x4) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0) -(sequence() (set tmp0 (sll 1 (sub avcv1Imm5u8 1))) -(set tmp1 (sub (subword SI tmp0 1) 1)) -(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp1 1))) (set avcv1CRq (subword SI tmp1 1)) -(if (lt (ext SI avcv1CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcv1CRq (neg (subword SI tmp0 1))) -(set avcv1CRq avcv1CRq) -) -) -) -) -) - ()) -(dn16i cclipiu_avc_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu")) - "cclipiu $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x5) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0) -(sequence() (set tmp0 (sub (sll 1 avcv1Imm5u8) 1)) -(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp0 1))) (set avcv1CRq (subword SI tmp0 1)) -(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avcv1CRq 0) -(set avcv1CRq avcv1CRq) -) -) -) -) -) - ()) -(dn16i cor_avc_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor")) - "cor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (or avcv1CRq avcv1CRp)) -) - ()) -(dn16i cand_avc_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand")) - "cand $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (and avcv1CRq avcv1CRp)) -) - ()) -(dn16i cxor_avc_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor")) - "cxor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (xor avcv1CRq avcv1CRp)) -) - ()) -(dn16i cnor_avc_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor")) - "cnor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (inv (or avcv1CRq avcv1CRp))) -) - ()) -(dn16i csra_avc_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra")) - "csra $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sra avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csrl_avc_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl")) - "csrl $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (srl avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csll_avc_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll")) - "csll $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sll avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csrai_avc_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai")) - "csrai $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x2) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sra avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i csrli_avc_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli")) - "csrli $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x3) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (srl avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i cslli_avc_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli")) - "cslli $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x6) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sll avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i cfsft_avc_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft")) - "cfsft $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avcv1CRq)) 32) (zext DI avcv1CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta0_avc_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0")) - "cfsfta0 $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta1_avc_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1")) - "cfsfta1 $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cmula0_avc_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0")) - "cmula0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat28)) (c-call "check_option_cp" pc) -(set concat28 (mul (ext DI avcv1CRq) (ext DI avcv1CRp))) -(set avccopCCR2 (subword SI concat28 0)) -(set avccopCCR3 (subword SI concat28 1)) -) - ()) -(dn16i cmulua0_avc_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0")) - "cmulua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat29)) (c-call "check_option_cp" pc) -(set concat29 (mul (zext DI avcv1CRq) (zext DI avcv1CRp))) -(set avccopCCR2 (subword SI concat29 0)) -(set avccopCCR3 (subword SI concat29 1)) -) - ()) -(dn16i cnmula0_avc_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0")) - "cnmula0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat30)) (c-call "check_option_cp" pc) -(set concat30 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat30 0)) -(set avccopCCR3 (subword SI concat30 1)) -) - ()) -(dn16i cmada0_avc_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0")) - "cmada0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat31)) (c-call "check_option_cp" pc) -(set concat31 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat31 0)) -(set avccopCCR3 (subword SI concat31 1)) -) - ()) -(dn16i cmadua0_avc_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0")) - "cmadua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat32)) (c-call "check_option_cp" pc) -(set concat32 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat32 0)) -(set avccopCCR3 (subword SI concat32 1)) -) - ()) -(dn16i cmsba0_avc_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0")) - "cmsba0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat33)) (c-call "check_option_cp" pc) -(set concat33 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat33 0)) -(set avccopCCR3 (subword SI concat33 1)) -) - ()) -(dn16i cmsbua0_avc_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0")) - "cmsbua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat34)) (c-call "check_option_cp" pc) -(set concat34 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat34 0)) -(set avccopCCR3 (subword SI concat34 1)) -) - ()) -(dn16i cmula1_avc_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1")) - "cmula1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat35)) (c-call "check_option_cp" pc) -(set concat35 (mul (ext DI avcv1CRq) (ext DI avcv1CRp))) -(set avccopCCR4 (subword SI concat35 0)) -(set avccopCCR5 (subword SI concat35 1)) -) - ()) -(dn16i cmulua1_avc_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1")) - "cmulua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat36)) (c-call "check_option_cp" pc) -(set concat36 (mul (zext DI avcv1CRq) (zext DI avcv1CRp))) -(set avccopCCR4 (subword SI concat36 0)) -(set avccopCCR5 (subword SI concat36 1)) -) - ()) -(dn16i cnmula1_avc_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1")) - "cnmula1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat37)) (c-call "check_option_cp" pc) -(set concat37 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat37 0)) -(set avccopCCR5 (subword SI concat37 1)) -) - ()) -(dn16i cmada1_avc_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1")) - "cmada1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat38)) (c-call "check_option_cp" pc) -(set concat38 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat38 0)) -(set avccopCCR5 (subword SI concat38 1)) -) - ()) -(dn16i cmadua1_avc_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1")) - "cmadua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat39)) (c-call "check_option_cp" pc) -(set concat39 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat39 0)) -(set avccopCCR5 (subword SI concat39 1)) -) - ()) -(dn16i cmsba1_avc_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1")) - "cmsba1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat40)) (c-call "check_option_cp" pc) -(set concat40 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat40 0)) -(set avccopCCR5 (subword SI concat40 1)) -) - ()) -(dn16i cmsbua1_avc_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1")) - "cmsbua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat41)) (c-call "check_option_cp" pc) -(set concat41 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat41 0)) -(set avccopCCR5 (subword SI concat41 1)) -) - ()) -(dn32i cmov1_avc_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1")) - "cmov $avcv3CRn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CRn avcv3Rm) -) - ()) -(dn32i cmov2_avc_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2")) - "cmov $avcv3Rm,$avcv3CRn" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CRn (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3Rm avcv3CRn) -) - ()) -(dn32i cmovi_avc_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi")) - "cmovi $avcv3CRq,$avcv3Imm16s4x24e32" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRq avcv3Imm16s4x24e32 (f-avc-v3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CRq (ext SI avcv3Imm16s4x24e32)) -) - ()) -(dn32i cmovc1_avc_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1")) - "cmovc $avcv3CCRn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CCRn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CCRn avcv3Rm) -) - ()) -(dn32i cmovc2_avc_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2")) - "cmovc $avcv3Rm,$avcv3CCRn" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CCRn (f-avc-v3sub4u28 #x3) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3Rm avcv3CCRn) -) - ()) -(dn32i xmula0_avc_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0")) - "xmula0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat42)) (c-call "check_option_cp" pc) -(set concat42 (mul (ext DI avcv3Rn) (ext DI avcv3Rm))) -(set avccopCCR2 (subword SI concat42 0)) -(set avccopCCR3 (subword SI concat42 1)) -) - ()) -(dn32i xmulua0_avc_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0")) - "xmulua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat43)) (c-call "check_option_cp" pc) -(set concat43 (mul (zext DI avcv3Rn) (zext DI avcv3Rm))) -(set avccopCCR2 (subword SI concat43 0)) -(set avccopCCR3 (subword SI concat43 1)) -) - ()) -(dn32i xnmula0_avc_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0")) - "xnmula0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat44)) (c-call "check_option_cp" pc) -(set concat44 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat44 0)) -(set avccopCCR3 (subword SI concat44 1)) -) - ()) -(dn32i xmada0_avc_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0")) - "xmada0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x4) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat45)) (c-call "check_option_cp" pc) -(set concat45 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat45 0)) -(set avccopCCR3 (subword SI concat45 1)) -) - ()) -(dn32i xmadua0_avc_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0")) - "xmadua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x5) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat46)) (c-call "check_option_cp" pc) -(set concat46 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat46 0)) -(set avccopCCR3 (subword SI concat46 1)) -) - ()) -(dn32i xmsba0_avc_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0")) - "xmsba0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x6) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat47)) (c-call "check_option_cp" pc) -(set concat47 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat47 0)) -(set avccopCCR3 (subword SI concat47 1)) -) - ()) -(dn32i xmsbua0_avc_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x7) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat48)) (c-call "check_option_cp" pc) -(set concat48 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat48 0)) -(set avccopCCR3 (subword SI concat48 1)) -) - ()) -(dn32i xmula1_avc_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1")) - "xmula1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x8) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat49)) (c-call "check_option_cp" pc) -(set concat49 (mul (ext DI avcv3Rn) (ext DI avcv3Rm))) -(set avccopCCR4 (subword SI concat49 0)) -(set avccopCCR5 (subword SI concat49 1)) -) - ()) -(dn32i xmulua1_avc_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1")) - "xmulua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x9) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat50)) (c-call "check_option_cp" pc) -(set concat50 (mul (zext DI avcv3Rn) (zext DI avcv3Rm))) -(set avccopCCR4 (subword SI concat50 0)) -(set avccopCCR5 (subword SI concat50 1)) -) - ()) -(dn32i xnmula1_avc_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1")) - "xnmula1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xa) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat51)) (c-call "check_option_cp" pc) -(set concat51 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat51 0)) -(set avccopCCR5 (subword SI concat51 1)) -) - ()) -(dn32i xmada1_avc_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1")) - "xmada1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xc) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat52)) (c-call "check_option_cp" pc) -(set concat52 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat52 0)) -(set avccopCCR5 (subword SI concat52 1)) -) - ()) -(dn32i xmadua1_avc_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1")) - "xmadua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xd) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat53)) (c-call "check_option_cp" pc) -(set concat53 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat53 0)) -(set avccopCCR5 (subword SI concat53 1)) -) - ()) -(dn32i xmsba1_avc_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1")) - "xmsba1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xe) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat54)) (c-call "check_option_cp" pc) -(set concat54 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat54 0)) -(set avccopCCR5 (subword SI concat54 1)) -) - ()) -(dn32i xmsbua1_avc_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xf) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat55)) (c-call "check_option_cp" pc) -(set concat55 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat55 0)) -(set avccopCCR5 (subword SI concat55 1)) -) - ()) diff --git a/cpu/mep-avc2.cpu b/cpu/mep-avc2.cpu deleted file mode 100644 index 60287e3..0000000 --- a/cpu/mep-avc2.cpu +++ /dev/null @@ -1,1970 +0,0 @@ -; Toshiba MeP AVC2 Coprocessor description. -*- Scheme -*- -; Copyright (C) 2005 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. -; -; This file was customized based upon the output of a2cgen 0.42 - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires 16 and 32 bit insns. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro avc2-core-isa () (ISA ext_core1)) -(define-pmacro avc2-16-isa () (ISA ext_cop1_16)) -(define-pmacro avc2-32-isa () (ISA ext_cop1_32)) -(define-pmacro all-avc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32)) -; end-isas - -(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-core-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-16-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-32-isa) xsyntax xformat xsemantics xtiming)) - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-avc2) - (comment "32-bit coprocessor registers for avc2 coprocessor") - (attrs VIRTUAL all-avc2-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-avc2) - (comment "Coprocessor control registers for avc2 coprocessor") - (attrs VIRTUAL all-avc2-isas) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - ($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0) - ($cbcr 1) - (.unsplice (.map -ccr-reg-pair (.iota 6))) - ) - ) -) -(dnop avc2copCCR5 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 5) -(dnop avc2copCCR4 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 4) -(dnop avc2copCCR3 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 3) -(dnop avc2copCCR2 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 2) -(dnop avc2copCCR1 "Audio Copro Branch Condition Register" (all-avc2-isas) h-ccr 1) -(dnop avc2copCCR0 "Audio Copro Shift-Amount Register" (all-avc2-isas) h-ccr 0) - -; instruction field and operand definitions -(dnf f-avc2-v3sub4u0 "sub opecode field" (avc2-32-isa) 0 4) -(dnf f-avc2-v1sub4u0 "sub opecode field" (avc2-16-isa) 0 4) -(dnf f-avc2-v3Rn "register field" (avc2-32-isa) 4 4) -(dnop avc2v3Rn "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rn) -(dnf f-avc2-v3CCRn "register field" (avc2-32-isa) 4 4) -(define-full-operand avc2v3CCRn "the operand definition" (avc2-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-v3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ()) -(df f-avc2-v3Imm16s4x24e32-hi "split immediate field hi" (avc2-32-isa) 4 8 INT #f #f) -(df f-avc2-v3Imm16s4x24e32-lo "split immediate field lo" (avc2-32-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc2-v3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc2-32-isa) - (mode INT) - (subfields f-avc2-v3Imm16s4x24e32-hi f-avc2-v3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc2-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-v3Imm16s4x24e32) 8)) - (set (ifield f-avc2-v3Imm16s4x24e32-lo) (and (ifield f-avc2-v3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc2-v3Imm16s4x24e32) - (or (sll (ifield f-avc2-v3Imm16s4x24e32-hi) 8) (ifield f-avc2-v3Imm16s4x24e32-lo)))) - ) -(dnop avc2v3Imm16s4x24e32 "the operand definition" (avc2-32-isa) h-sint f-avc2-v3Imm16s4x24e32) -(dnf f-avc2-v3CRn "register field" (avc2-32-isa) 4 4) -(define-full-operand avc2v3CRn "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRn ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1CRq "register field" (avc2-16-isa) 4 4) -(define-full-operand avc2v1CRq "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u4 "sub opecode field" (avc2-16-isa) 4 4) -(dnf f-avc2-c3Rn "register field" (avc2-core-isa) 4 4) -(dnop avc2c3Rn "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rn) -(dnf f-avc2-c3CCRn "register field" (avc2-core-isa) 4 4) -(define-full-operand avc2c3CCRn "the operand definition" (avc2-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-c3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ()) -(df f-avc2-c3Imm16s4x24e32-hi "split immediate field hi" (avc2-core-isa) 4 8 INT #f #f) -(df f-avc2-c3Imm16s4x24e32-lo "split immediate field lo" (avc2-core-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc2-c3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc2-core-isa) - (mode INT) - (subfields f-avc2-c3Imm16s4x24e32-hi f-avc2-c3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc2-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-c3Imm16s4x24e32) 8)) - (set (ifield f-avc2-c3Imm16s4x24e32-lo) (and (ifield f-avc2-c3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc2-c3Imm16s4x24e32) - (or (sll (ifield f-avc2-c3Imm16s4x24e32-hi) 8) (ifield f-avc2-c3Imm16s4x24e32-lo)))) - ) -(dnop avc2c3Imm16s4x24e32 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm16s4x24e32) -(dnf f-avc2-c3CRn "register field" (avc2-core-isa) 4 4) -(define-full-operand avc2c3CRn "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRn ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u4 "sub opecode field" (avc2-core-isa) 4 4) -(dnf f-avc2-v3Rm "register field" (avc2-32-isa) 8 4) -(dnop avc2v3Rm "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rm) -(df f-avc2-v1Imm6u8 "immediate field" (avc2-16-isa) 8 6 UINT #f #f) -(dnop avc2v1Imm6u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm6u8) -(df f-avc2-v1Imm5u8 "immediate field" (avc2-16-isa) 8 5 UINT #f #f) -(dnop avc2v1Imm5u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm5u8) -(df f-avc2-v1Imm6s8 "immediate field" (avc2-16-isa) 8 6 INT #f #f) -(dnop avc2v1Imm6s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm6s8) -(df f-avc2-v1Imm8s8 "immediate field" (avc2-16-isa) 8 8 INT #f #f) -(dnop avc2v1Imm8s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm8s8) -(dnf f-avc2-v1CRp "register field" (avc2-16-isa) 8 4) -(define-full-operand avc2v1CRp "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRp ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u8 "sub opecode field" (avc2-16-isa) 8 4) -(dnf f-avc2-c3Rm "register field" (avc2-core-isa) 8 4) -(dnop avc2c3Rm "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rm) -(dnf f-avc2-c3sub4u8 "sub opecode field" (avc2-core-isa) 8 4) -(dnf f-avc2-v3sub4u12 "sub opecode field" (avc2-32-isa) 12 4) -(dnf f-avc2-v1CRo "register field" (avc2-16-isa) 12 4) -(define-full-operand avc2v1CRo "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRo ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u12 "sub opecode field" (avc2-16-isa) 12 4) -(dnf f-avc2-v1sub3u13 "sub opecode field" (avc2-16-isa) 13 3) -(dnf f-avc2-v1sub2u14 "sub opecode field" (avc2-16-isa) 14 2) -(dnf f-avc2-v3sub4u16 "sub opecode field" (avc2-32-isa) 16 4) -(dnf f-avc2-c3sub4u16 "sub opecode field" (avc2-core-isa) 16 4) -(dnf f-avc2-v3CRq "register field" (avc2-32-isa) 20 4) -(define-full-operand avc2v3CRq "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v3sub4u20 "sub opecode field" (avc2-32-isa) 20 4) -(dnf f-avc2-c3CRq "register field" (avc2-core-isa) 20 4) -(define-full-operand avc2c3CRq "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u20 "sub opecode field" (avc2-core-isa) 20 4) -(dnf f-avc2-v3sub4u24 "sub opecode field" (avc2-32-isa) 24 4) -(df f-avc2-c3Imm6u24 "immediate field" (avc2-core-isa) 24 6 UINT #f #f) -(dnop avc2c3Imm6u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm6u24) -(df f-avc2-c3Imm5u24 "immediate field" (avc2-core-isa) 24 5 UINT #f #f) -(dnop avc2c3Imm5u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm5u24) -(df f-avc2-c3Imm6s24 "immediate field" (avc2-core-isa) 24 6 INT #f #f) -(dnop avc2c3Imm6s24 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm6s24) -(dnf f-avc2-c3CRp "register field" (avc2-core-isa) 24 4) -(define-full-operand avc2c3CRp "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRp ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u24 "sub opecode field" (avc2-core-isa) 24 4) -(dnf f-avc2-v3sub4u28 "sub opecode field" (avc2-32-isa) 28 4) -(dnf f-avc2-c3CRo "register field" (avc2-core-isa) 28 4) -(define-full-operand avc2c3CRo "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRo ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u28 "sub opecode field" (avc2-core-isa) 28 4) -(dnf f-avc2-c3sub3u29 "sub opecode field" (avc2-core-isa) 29 3) -(dnf f-avc2-c3sub2u30 "sub opecode field" (avc2-core-isa) 30 2) - -; instruction definitions -(dncpi cnop_avc2_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop")) - "cnop" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(c-call "check_option_cp" pc) - ()) -(dncpi cmov1_avc2_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1")) - "cmov $avc2c3CRn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3CRn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRn avc2c3Rm) -) - ()) -(dncpi cmov2_avc2_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2")) - "cmov $avc2c3Rm,$avc2c3CRn" -(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CRn (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3Rm avc2c3CRn) -) - ()) -(dncpi cmovi_avc2_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi")) - "cmovi $avc2c3CRq,$avc2c3Imm16s4x24e32" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm16s4x24e32 (f-avc2-c3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI avc2c3Imm16s4x24e32)) -) - ()) -(dncpi cmovc1_avc2_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1")) - "cmovc $avc2c3CCRn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3CCRn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CCRn avc2c3Rm) -) - ()) -(dncpi cmovc2_avc2_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2")) - "cmovc $avc2c3Rm,$avc2c3CCRn" -(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CCRn (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3Rm avc2c3CCRn) -) - ()) -(dncpi cmov_avc2_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov")) - "cmov $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq avc2c3CRp) -) - ()) -(dncpi cadd3_avc2_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3")) - "cadd3 $avc2c3CRo,$avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRo avc2c3CRq avc2c3CRp (f-avc2-c3sub4u16 #x3) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRo (add avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi caddi_avc2_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi")) - "caddi $avc2c3CRq,$avc2c3Imm6s24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6s24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (add avc2c3CRq (ext SI avc2c3Imm6s24))) -) - ()) -(dncpi csub_avc2_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub")) - "csub $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sub avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cneg_avc2_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg")) - "cneg $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (neg avc2c3CRp)) -) - ()) -(dncpi cextb_avc2_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb")) - "cextb $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI (and QI (srl avc2c3CRq 0) #xff))) -) - ()) -(dncpi cexth_avc2_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth")) - "cexth $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI (and HI (srl avc2c3CRq 0) #xffff))) -) - ()) -(dncpi cextub_avc2_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub")) - "cextub $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x8) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (zext SI (and QI (srl avc2c3CRq 0) #xff))) -) - ()) -(dncpi cextuh_avc2_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh")) - "cextuh $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (zext SI (and HI (srl avc2c3CRq 0) #xffff))) -) - ()) -(dncpi cscltz_avc2_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz")) - "cscltz $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dncpi cldz_avc2_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz")) - "cldz $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (and avc2c3CRp #x80000000) (set avc2c3CRq 0) -(if (and avc2c3CRp #x40000000) (set avc2c3CRq 1) -(if (and avc2c3CRp #x20000000) (set avc2c3CRq 2) -(if (and avc2c3CRp #x10000000) (set avc2c3CRq 3) -(if (and avc2c3CRp #x8000000) (set avc2c3CRq 4) -(if (and avc2c3CRp #x4000000) (set avc2c3CRq 5) -(if (and avc2c3CRp #x2000000) (set avc2c3CRq 6) -(if (and avc2c3CRp #x1000000) (set avc2c3CRq 7) -(if (and avc2c3CRp #x800000) (set avc2c3CRq 8) -(if (and avc2c3CRp #x400000) (set avc2c3CRq 9) -(if (and avc2c3CRp #x200000) (set avc2c3CRq 10) -(if (and avc2c3CRp #x100000) (set avc2c3CRq 11) -(if (and avc2c3CRp #x80000) (set avc2c3CRq 12) -(if (and avc2c3CRp #x40000) (set avc2c3CRq 13) -(if (and avc2c3CRp #x20000) (set avc2c3CRq 14) -(if (and avc2c3CRp #x10000) (set avc2c3CRq 15) -(if (and avc2c3CRp #x8000) (set avc2c3CRq 16) -(if (and avc2c3CRp #x4000) (set avc2c3CRq 17) -(if (and avc2c3CRp #x2000) (set avc2c3CRq 18) -(if (and avc2c3CRp #x1000) (set avc2c3CRq 19) -(if (and avc2c3CRp #x800) (set avc2c3CRq 20) -(if (and avc2c3CRp #x400) (set avc2c3CRq 21) -(if (and avc2c3CRp #x200) (set avc2c3CRq 22) -(if (and avc2c3CRp #x100) (set avc2c3CRq 23) -(if (and avc2c3CRp #x80) (set avc2c3CRq 24) -(if (and avc2c3CRp #x40) (set avc2c3CRq 25) -(if (and avc2c3CRp #x20) (set avc2c3CRq 26) -(if (and avc2c3CRp #x10) (set avc2c3CRq 27) -(if (and avc2c3CRp #x8) (set avc2c3CRq 28) -(if (and avc2c3CRp #x4) (set avc2c3CRq 29) -(if (and avc2c3CRp #x2) (set avc2c3CRq 30) -(if (and avc2c3CRp #x1) (set avc2c3CRq 31) -(set avc2c3CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dncpi cabs_avc2_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs")) - "cabs $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (abs (ext SI (subword SI (sub avc2c3CRq avc2c3CRp) 1)))) -) - ()) -(dncpi cad1s_avc2_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s")) - "cad1s $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (add avc2c3CRq avc2c3CRp) 1)) -(set avc2c3CRq (sra tmp0 1)) -) - ()) -(dncpi csb1s_avc2_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s")) - "csb1s $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (sub avc2c3CRq avc2c3CRp) 1)) -(set avc2c3CRq (sra tmp0 1)) -) - ()) -(dncpi cmin_avc2_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin")) - "cmin $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cmax_avc2_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax")) - "cmax $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cminu_avc2_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu")) - "cminu $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cmaxu_avc2_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu")) - "cmaxu $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cclipi_avc2_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi")) - "cclipi $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x4) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0) -(sequence() (set tmp0 (sll 1 (sub avc2c3Imm5u24 1))) -(set tmp1 (sub tmp0 1)) -(if (gt (ext SI avc2c3CRq) (ext SI tmp1)) (set avc2c3CRq tmp1) -(if (lt (ext SI avc2c3CRq) (ext SI (neg tmp0))) (set avc2c3CRq (neg tmp0)) -(set avc2c3CRq avc2c3CRq) -) -) -) -) -) - ()) -(dncpi cclipiu_avc2_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu")) - "cclipiu $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x5) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)(SI tmp1)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0) -(sequence() (set tmp0 (sub (sll 1 avc2c3Imm5u24) 1)) -(if (gtu (ext SI avc2c3CRq) (zext SI tmp0)) (set avc2c3CRq tmp0) -(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2c3CRq 0) -(set avc2c3CRq avc2c3CRq) -) -) -) -) -) - ()) -(dncpi cor_avc2_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor")) - "cor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (or avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cand_avc2_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand")) - "cand $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (and avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cxor_avc2_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor")) - "cxor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (xor avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cnor_avc2_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor")) - "cnor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (inv (or avc2c3CRq avc2c3CRp))) -) - ()) -(dncpi csra_avc2_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra")) - "csra $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sra avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csrl_avc2_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl")) - "csrl $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (srl avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csll_avc2_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll")) - "csll $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sll avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csrai_avc2_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai")) - "csrai $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x2) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sra avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi csrli_avc2_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli")) - "csrli $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x3) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (srl avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi cslli_avc2_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli")) - "cslli $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x6) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sll avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi cfsft_avc2_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft")) - "cfsft $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI avc2c3CRq) 32) (zext DI avc2c3CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta0_avc2_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0")) - "cfsfta0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta1_avc2_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1")) - "cfsfta1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cmula0_avc2_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0")) - "cmula0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat0)) (c-call "check_option_cp" pc) -(set concat0 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat0 0)) -(set avc2copCCR3 (subword SI concat0 1)) -) - ()) -(dncpi cmulua0_avc2_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0")) - "cmulua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat1)) (c-call "check_option_cp" pc) -(set concat1 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat1 0)) -(set avc2copCCR3 (subword SI concat1 1)) -) - ()) -(dncpi cnmula0_avc2_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0")) - "cnmula0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat2)) (c-call "check_option_cp" pc) -(set concat2 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat2 0)) -(set avc2copCCR3 (subword SI concat2 1)) -) - ()) -(dncpi cmada0_avc2_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0")) - "cmada0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat3)) (c-call "check_option_cp" pc) -(set concat3 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat3 0)) -(set avc2copCCR3 (subword SI concat3 1)) -) - ()) -(dncpi cmadua0_avc2_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0")) - "cmadua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat4)) (c-call "check_option_cp" pc) -(set concat4 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat4 0)) -(set avc2copCCR3 (subword SI concat4 1)) -) - ()) -(dncpi cmsba0_avc2_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0")) - "cmsba0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat5)) (c-call "check_option_cp" pc) -(set concat5 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat5 0)) -(set avc2copCCR3 (subword SI concat5 1)) -) - ()) -(dncpi cmsbua0_avc2_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0")) - "cmsbua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat6)) (c-call "check_option_cp" pc) -(set concat6 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat6 0)) -(set avc2copCCR3 (subword SI concat6 1)) -) - ()) -(dncpi cmula1_avc2_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1")) - "cmula1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat7)) (c-call "check_option_cp" pc) -(set concat7 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat7 0)) -(set avc2copCCR5 (subword SI concat7 1)) -) - ()) -(dncpi cmulua1_avc2_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1")) - "cmulua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat8)) (c-call "check_option_cp" pc) -(set concat8 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat8 0)) -(set avc2copCCR5 (subword SI concat8 1)) -) - ()) -(dncpi cnmula1_avc2_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1")) - "cnmula1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat9)) (c-call "check_option_cp" pc) -(set concat9 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat9 0)) -(set avc2copCCR5 (subword SI concat9 1)) -) - ()) -(dncpi cmada1_avc2_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1")) - "cmada1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat10)) (c-call "check_option_cp" pc) -(set concat10 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat10 0)) -(set avc2copCCR5 (subword SI concat10 1)) -) - ()) -(dncpi cmadua1_avc2_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1")) - "cmadua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat11)) (c-call "check_option_cp" pc) -(set concat11 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat11 0)) -(set avc2copCCR5 (subword SI concat11 1)) -) - ()) -(dncpi cmsba1_avc2_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1")) - "cmsba1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat12)) (c-call "check_option_cp" pc) -(set concat12 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat12 0)) -(set avc2copCCR5 (subword SI concat12 1)) -) - ()) -(dncpi cmsbua1_avc2_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1")) - "cmsbua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat13)) (c-call "check_option_cp" pc) -(set concat13 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat13 0)) -(set avc2copCCR5 (subword SI concat13 1)) -) - ()) -(dncpi xmula0_avc2_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0")) - "xmula0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat14)) (c-call "check_option_cp" pc) -(set concat14 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))) -(set avc2copCCR2 (subword SI concat14 0)) -(set avc2copCCR3 (subword SI concat14 1)) -) - ()) -(dncpi xmulua0_avc2_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0")) - "xmulua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat15)) (c-call "check_option_cp" pc) -(set concat15 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))) -(set avc2copCCR2 (subword SI concat15 0)) -(set avc2copCCR3 (subword SI concat15 1)) -) - ()) -(dncpi xnmula0_avc2_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0")) - "xnmula0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat16)) (c-call "check_option_cp" pc) -(set concat16 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat16 0)) -(set avc2copCCR3 (subword SI concat16 1)) -) - ()) -(dncpi xmada0_avc2_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0")) - "xmada0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat17)) (c-call "check_option_cp" pc) -(set concat17 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat17 0)) -(set avc2copCCR3 (subword SI concat17 1)) -) - ()) -(dncpi xmadua0_avc2_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0")) - "xmadua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat18)) (c-call "check_option_cp" pc) -(set concat18 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat18 0)) -(set avc2copCCR3 (subword SI concat18 1)) -) - ()) -(dncpi xmsba0_avc2_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0")) - "xmsba0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat19)) (c-call "check_option_cp" pc) -(set concat19 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat19 0)) -(set avc2copCCR3 (subword SI concat19 1)) -) - ()) -(dncpi xmsbua0_avc2_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat20)) (c-call "check_option_cp" pc) -(set concat20 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat20 0)) -(set avc2copCCR3 (subword SI concat20 1)) -) - ()) -(dncpi xmula1_avc2_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1")) - "xmula1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat21)) (c-call "check_option_cp" pc) -(set concat21 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))) -(set avc2copCCR4 (subword SI concat21 0)) -(set avc2copCCR5 (subword SI concat21 1)) -) - ()) -(dncpi xmulua1_avc2_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1")) - "xmulua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat22)) (c-call "check_option_cp" pc) -(set concat22 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))) -(set avc2copCCR4 (subword SI concat22 0)) -(set avc2copCCR5 (subword SI concat22 1)) -) - ()) -(dncpi xnmula1_avc2_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1")) - "xnmula1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat23)) (c-call "check_option_cp" pc) -(set concat23 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat23 0)) -(set avc2copCCR5 (subword SI concat23 1)) -) - ()) -(dncpi xmada1_avc2_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1")) - "xmada1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat24)) (c-call "check_option_cp" pc) -(set concat24 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat24 0)) -(set avc2copCCR5 (subword SI concat24 1)) -) - ()) -(dncpi xmadua1_avc2_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1")) - "xmadua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat25)) (c-call "check_option_cp" pc) -(set concat25 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat25 0)) -(set avc2copCCR5 (subword SI concat25 1)) -) - ()) -(dncpi xmsba1_avc2_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1")) - "xmsba1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat26)) (c-call "check_option_cp" pc) -(set concat26 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat26 0)) -(set avc2copCCR5 (subword SI concat26 1)) -) - ()) -(dncpi xmsbua1_avc2_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat27)) (c-call "check_option_cp" pc) -(set concat27 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat27 0)) -(set avc2copCCR5 (subword SI concat27 1)) -) - ()) -(dncpi cclipa0_avc2_c3 "cclipa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa0")) - "cclipa0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) -) -) -(set avc2c3CRq (subword SI tmp_rslt 1)) -) - ()) -(dncpi cclipa1_avc2_c3 "cclipa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa1")) - "cclipa1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) -) -) -(set avc2c3CRq (subword SI tmp_rslt 1)) -) - ()) -(dncpi cmvsla0i_avc2_c3 "cmvsla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla0i")) - "cmvsla0i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x2) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat28)) (c-call "check_option_cp" pc) -(set concat28 (sll (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat28 0)) -(set avc2copCCR3 (subword SI concat28 1)) -) - ()) -(dncpi cmvsra0i_avc2_c3 "cmvsra0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra0i")) - "cmvsra0i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat29)) (c-call "check_option_cp" pc) -(set concat29 (sra (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat29 0)) -(set avc2copCCR3 (subword SI concat29 1)) -) - ()) -(dncpi cmvsla1i_avc2_c3 "cmvsla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla1i")) - "cmvsla1i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x3) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat30)) (c-call "check_option_cp" pc) -(set concat30 (sll (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat30 0)) -(set avc2copCCR5 (subword SI concat30 1)) -) - ()) -(dncpi cmvsra1i_avc2_c3 "cmvsra1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra1i")) - "cmvsra1i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat31)) (c-call "check_option_cp" pc) -(set concat31 (sra (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat31 0)) -(set avc2copCCR5 (subword SI concat31 1)) -) - ()) -(dncpi csraa0i_avc2_c3 "csraa0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0i")) - "csraa0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat32)) (c-call "check_option_cp" pc) -(set concat32 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat32 0)) -(set avc2copCCR3 (subword SI concat32 1)) -) - ()) -(dncpi csraa1i_avc2_c3 "csraa1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1i")) - "csraa1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat33)) (c-call "check_option_cp" pc) -(set concat33 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat33 0)) -(set avc2copCCR5 (subword SI concat33 1)) -) - ()) -(dncpi csrla0i_avc2_c3 "csrla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0i")) - "csrla0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat34)) (c-call "check_option_cp" pc) -(set concat34 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat34 0)) -(set avc2copCCR3 (subword SI concat34 1)) -) - ()) -(dncpi csrla1i_avc2_c3 "csrla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1i")) - "csrla1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat35)) (c-call "check_option_cp" pc) -(set concat35 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat35 0)) -(set avc2copCCR5 (subword SI concat35 1)) -) - ()) -(dncpi cslla0i_avc2_c3 "cslla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0i")) - "cslla0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat36)) (c-call "check_option_cp" pc) -(set concat36 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat36 0)) -(set avc2copCCR3 (subword SI concat36 1)) -) - ()) -(dncpi cslla1i_avc2_c3 "cslla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1i")) - "cslla1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat37)) (c-call "check_option_cp" pc) -(set concat37 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat37 0)) -(set avc2copCCR5 (subword SI concat37 1)) -) - ()) -(dncpi csraa0_avc2_c3 "csraa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0")) - "csraa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat38)) (c-call "check_option_cp" pc) -(set concat38 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat38 0)) -(set avc2copCCR3 (subword SI concat38 1)) -) - ()) -(dncpi csraa1_avc2_c3 "csraa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1")) - "csraa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat39)) (c-call "check_option_cp" pc) -(set concat39 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat39 0)) -(set avc2copCCR5 (subword SI concat39 1)) -) - ()) -(dncpi csrla0_avc2_c3 "csrla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0")) - "csrla0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat40)) (c-call "check_option_cp" pc) -(set concat40 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat40 0)) -(set avc2copCCR3 (subword SI concat40 1)) -) - ()) -(dncpi csrla1_avc2_c3 "csrla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1")) - "csrla1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat41)) (c-call "check_option_cp" pc) -(set concat41 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat41 0)) -(set avc2copCCR5 (subword SI concat41 1)) -) - ()) -(dncpi cslla0_avc2_c3 "cslla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0")) - "cslla0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat42)) (c-call "check_option_cp" pc) -(set concat42 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat42 0)) -(set avc2copCCR3 (subword SI concat42 1)) -) - ()) -(dncpi cslla1_avc2_c3 "cslla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1")) - "cslla1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat43)) (c-call "check_option_cp" pc) -(set concat43 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat43 0)) -(set avc2copCCR5 (subword SI concat43 1)) -) - ()) -(dncpi cadda0_avc2_c3 "cadda0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda0")) - "cadda0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat44)) (c-call "check_option_cp" pc) -(set concat44 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq))) -(set avc2copCCR2 (subword SI concat44 0)) -(set avc2copCCR3 (subword SI concat44 1)) -) - ()) -(dncpi cadda1_avc2_c3 "cadda1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda1")) - "cadda1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat45)) (c-call "check_option_cp" pc) -(set concat45 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq))) -(set avc2copCCR4 (subword SI concat45 0)) -(set avc2copCCR5 (subword SI concat45 1)) -) - ()) -(dncpi csuba0_avc2_c3 "csuba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba0")) - "csuba0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat46)) (c-call "check_option_cp" pc) -(set concat46 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq))) -(set avc2copCCR2 (subword SI concat46 0)) -(set avc2copCCR3 (subword SI concat46 1)) -) - ()) -(dncpi csuba1_avc2_c3 "csuba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba1")) - "csuba1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat47)) (c-call "check_option_cp" pc) -(set concat47 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq))) -(set avc2copCCR4 (subword SI concat47 0)) -(set avc2copCCR5 (subword SI concat47 1)) -) - ()) -(dncpi cadd2a0_avc2_c3 "cadd2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a0")) - "cadd2a0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat48)) (c-call "check_option_cp" pc) -(set concat48 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat48 0)) -(set avc2copCCR3 (subword SI concat48 1)) -) - ()) -(dncpi cadd2a1_avc2_c3 "cadd2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a1")) - "cadd2a1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat49)) (c-call "check_option_cp" pc) -(set concat49 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat49 0)) -(set avc2copCCR5 (subword SI concat49 1)) -) - ()) -(dncpi csub2a0_avc2_c3 "csub2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a0")) - "csub2a0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat50)) (c-call "check_option_cp" pc) -(set concat50 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat50 0)) -(set avc2copCCR3 (subword SI concat50 1)) -) - ()) -(dncpi csub2a1_avc2_c3 "csub2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a1")) - "csub2a1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat51)) (c-call "check_option_cp" pc) -(set concat51 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat51 0)) -(set avc2copCCR5 (subword SI concat51 1)) -) - ()) -(dncpi caddaa0_avc2_c3 "caddaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa0")) - "caddaa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat52)) (c-call "check_option_cp" pc) -(set concat52 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat52 0)) -(set avc2copCCR3 (subword SI concat52 1)) -) - ()) -(dncpi caddaa1_avc2_c3 "caddaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa1")) - "caddaa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat53)) (c-call "check_option_cp" pc) -(set concat53 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat53 0)) -(set avc2copCCR5 (subword SI concat53 1)) -) - ()) -(dncpi csubaa0_avc2_c3 "csubaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa0")) - "csubaa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat54)) (c-call "check_option_cp" pc) -(set concat54 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat54 0)) -(set avc2copCCR3 (subword SI concat54 1)) -) - ()) -(dncpi csubaa1_avc2_c3 "csubaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa1")) - "csubaa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat55)) (c-call "check_option_cp" pc) -(set concat55 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat55 0)) -(set avc2copCCR5 (subword SI concat55 1)) -) - ()) -(dn16i cnop_avc2_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop")) - "cnop" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x0)) -(c-call "check_option_cp" pc) - ()) -(dnmi cpnop16_avc2_v1 "cpnop16" -(avc2-16-isa NO-DIS) -"cpnop16" -(emit cnop_avc2_v1) -) -(dn16i cmov_avc2_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov")) - "cmov $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq avc2v1CRp) -) - ()) -(dn16i cmovi_avc2_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi")) - "cmovi $avc2v1CRq,$avc2v1Imm8s8" -(+ avc2v1CRq avc2v1Imm8s8 (f-avc2-v1sub4u0 #x2)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI avc2v1Imm8s8)) -) - ()) -(dn16i cadd3_avc2_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3")) - "cadd3 $avc2v1CRo,$avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRo avc2v1CRq avc2v1CRp (f-avc2-v1sub4u0 #x3)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRo (add avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i caddi_avc2_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi")) - "caddi $avc2v1CRq,$avc2v1Imm6s8" -(+ avc2v1CRq avc2v1Imm6s8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (add avc2v1CRq (ext SI avc2v1Imm6s8))) -) - ()) -(dn16i csub_avc2_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub")) - "csub $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sub avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cneg_avc2_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg")) - "cneg $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (neg avc2v1CRp)) -) - ()) -(dn16i cextb_avc2_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb")) - "cextb $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI (and QI (srl avc2v1CRq 0) #xff))) -) - ()) -(dn16i cexth_avc2_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth")) - "cexth $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x2) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI (and HI (srl avc2v1CRq 0) #xffff))) -) - ()) -(dn16i cextub_avc2_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub")) - "cextub $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x8) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (zext SI (and QI (srl avc2v1CRq 0) #xff))) -) - ()) -(dn16i cextuh_avc2_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh")) - "cextuh $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (zext SI (and HI (srl avc2v1CRq 0) #xffff))) -) - ()) -(dn16i cscltz_avc2_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz")) - "cscltz $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dn16i cldz_avc2_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz")) - "cldz $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (and avc2v1CRp #x80000000) (set avc2v1CRq 0) -(if (and avc2v1CRp #x40000000) (set avc2v1CRq 1) -(if (and avc2v1CRp #x20000000) (set avc2v1CRq 2) -(if (and avc2v1CRp #x10000000) (set avc2v1CRq 3) -(if (and avc2v1CRp #x8000000) (set avc2v1CRq 4) -(if (and avc2v1CRp #x4000000) (set avc2v1CRq 5) -(if (and avc2v1CRp #x2000000) (set avc2v1CRq 6) -(if (and avc2v1CRp #x1000000) (set avc2v1CRq 7) -(if (and avc2v1CRp #x800000) (set avc2v1CRq 8) -(if (and avc2v1CRp #x400000) (set avc2v1CRq 9) -(if (and avc2v1CRp #x200000) (set avc2v1CRq 10) -(if (and avc2v1CRp #x100000) (set avc2v1CRq 11) -(if (and avc2v1CRp #x80000) (set avc2v1CRq 12) -(if (and avc2v1CRp #x40000) (set avc2v1CRq 13) -(if (and avc2v1CRp #x20000) (set avc2v1CRq 14) -(if (and avc2v1CRp #x10000) (set avc2v1CRq 15) -(if (and avc2v1CRp #x8000) (set avc2v1CRq 16) -(if (and avc2v1CRp #x4000) (set avc2v1CRq 17) -(if (and avc2v1CRp #x2000) (set avc2v1CRq 18) -(if (and avc2v1CRp #x1000) (set avc2v1CRq 19) -(if (and avc2v1CRp #x800) (set avc2v1CRq 20) -(if (and avc2v1CRp #x400) (set avc2v1CRq 21) -(if (and avc2v1CRp #x200) (set avc2v1CRq 22) -(if (and avc2v1CRp #x100) (set avc2v1CRq 23) -(if (and avc2v1CRp #x80) (set avc2v1CRq 24) -(if (and avc2v1CRp #x40) (set avc2v1CRq 25) -(if (and avc2v1CRp #x20) (set avc2v1CRq 26) -(if (and avc2v1CRp #x10) (set avc2v1CRq 27) -(if (and avc2v1CRp #x8) (set avc2v1CRq 28) -(if (and avc2v1CRp #x4) (set avc2v1CRq 29) -(if (and avc2v1CRp #x2) (set avc2v1CRq 30) -(if (and avc2v1CRp #x1) (set avc2v1CRq 31) -(set avc2v1CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dn16i cabs_avc2_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs")) - "cabs $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (abs (ext SI (subword SI (sub avc2v1CRq avc2v1CRp) 1)))) -) - ()) -(dn16i cad1s_avc2_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s")) - "cad1s $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (add avc2v1CRq avc2v1CRp) 1)) -(set avc2v1CRq (sra tmp0 1)) -) - ()) -(dn16i csb1s_avc2_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s")) - "csb1s $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (sub avc2v1CRq avc2v1CRp) 1)) -(set avc2v1CRq (sra tmp0 1)) -) - ()) -(dn16i cmin_avc2_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin")) - "cmin $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cmax_avc2_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax")) - "cmax $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cminu_avc2_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu")) - "cminu $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cmaxu_avc2_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu")) - "cmaxu $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cclipi_avc2_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi")) - "cclipi $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x4) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0) -(sequence() (set tmp0 (sll 1 (sub avc2v1Imm5u8 1))) -(set tmp1 (sub tmp0 1)) -(if (gt (ext SI avc2v1CRq) (ext SI tmp1)) (set avc2v1CRq tmp1) -(if (lt (ext SI avc2v1CRq) (ext SI (neg tmp0))) (set avc2v1CRq (neg tmp0)) -(set avc2v1CRq avc2v1CRq) -) -) -) -) -) - ()) -(dn16i cclipiu_avc2_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu")) - "cclipiu $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x5) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0) -(sequence() (set tmp0 (sub (sll 1 avc2v1Imm5u8) 1)) -(if (gtu (ext SI avc2v1CRq) (zext SI tmp0)) (set avc2v1CRq tmp0) -(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2v1CRq 0) -(set avc2v1CRq avc2v1CRq) -) -) -) -) -) - ()) -(dn16i cor_avc2_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor")) - "cor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (or avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cand_avc2_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand")) - "cand $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (and avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cxor_avc2_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor")) - "cxor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (xor avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cnor_avc2_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor")) - "cnor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (inv (or avc2v1CRq avc2v1CRp))) -) - ()) -(dn16i csra_avc2_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra")) - "csra $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sra avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csrl_avc2_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl")) - "csrl $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (srl avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csll_avc2_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll")) - "csll $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sll avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csrai_avc2_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai")) - "csrai $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x2) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sra avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i csrli_avc2_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli")) - "csrli $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x3) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (srl avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i cslli_avc2_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli")) - "cslli $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x6) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sll avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i cfsft_avc2_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft")) - "cfsft $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2v1CRq)) 32) (zext DI avc2v1CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta0_avc2_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0")) - "cfsfta0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta1_avc2_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1")) - "cfsfta1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cmula0_avc2_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0")) - "cmula0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat56)) (c-call "check_option_cp" pc) -(set concat56 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat56 0)) -(set avc2copCCR3 (subword SI concat56 1)) -) - ()) -(dn16i cmulua0_avc2_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0")) - "cmulua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat57)) (c-call "check_option_cp" pc) -(set concat57 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat57 0)) -(set avc2copCCR3 (subword SI concat57 1)) -) - ()) -(dn16i cnmula0_avc2_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0")) - "cnmula0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat58)) (c-call "check_option_cp" pc) -(set concat58 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat58 0)) -(set avc2copCCR3 (subword SI concat58 1)) -) - ()) -(dn16i cmada0_avc2_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0")) - "cmada0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat59)) (c-call "check_option_cp" pc) -(set concat59 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat59 0)) -(set avc2copCCR3 (subword SI concat59 1)) -) - ()) -(dn16i cmadua0_avc2_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0")) - "cmadua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat60)) (c-call "check_option_cp" pc) -(set concat60 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat60 0)) -(set avc2copCCR3 (subword SI concat60 1)) -) - ()) -(dn16i cmsba0_avc2_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0")) - "cmsba0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat61)) (c-call "check_option_cp" pc) -(set concat61 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat61 0)) -(set avc2copCCR3 (subword SI concat61 1)) -) - ()) -(dn16i cmsbua0_avc2_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0")) - "cmsbua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat62)) (c-call "check_option_cp" pc) -(set concat62 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat62 0)) -(set avc2copCCR3 (subword SI concat62 1)) -) - ()) -(dn16i cmula1_avc2_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1")) - "cmula1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat63)) (c-call "check_option_cp" pc) -(set concat63 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat63 0)) -(set avc2copCCR5 (subword SI concat63 1)) -) - ()) -(dn16i cmulua1_avc2_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1")) - "cmulua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat64)) (c-call "check_option_cp" pc) -(set concat64 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat64 0)) -(set avc2copCCR5 (subword SI concat64 1)) -) - ()) -(dn16i cnmula1_avc2_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1")) - "cnmula1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat65)) (c-call "check_option_cp" pc) -(set concat65 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat65 0)) -(set avc2copCCR5 (subword SI concat65 1)) -) - ()) -(dn16i cmada1_avc2_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1")) - "cmada1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat66)) (c-call "check_option_cp" pc) -(set concat66 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat66 0)) -(set avc2copCCR5 (subword SI concat66 1)) -) - ()) -(dn16i cmadua1_avc2_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1")) - "cmadua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat67)) (c-call "check_option_cp" pc) -(set concat67 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat67 0)) -(set avc2copCCR5 (subword SI concat67 1)) -) - ()) -(dn16i cmsba1_avc2_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1")) - "cmsba1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat68)) (c-call "check_option_cp" pc) -(set concat68 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat68 0)) -(set avc2copCCR5 (subword SI concat68 1)) -) - ()) -(dn16i cmsbua1_avc2_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1")) - "cmsbua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat69)) (c-call "check_option_cp" pc) -(set concat69 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat69 0)) -(set avc2copCCR5 (subword SI concat69 1)) -) - ()) -(dn16i cclipa0_avc2_v1 "cclipa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa0")) - "cclipa0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) -) -) -(set avc2v1CRq (subword SI tmp_rslt 1)) -) - ()) -(dn16i cclipa1_avc2_v1 "cclipa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa1")) - "cclipa1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) -) -) -(set avc2v1CRq (subword SI tmp_rslt 1)) -) - ()) -(dn16i cmvsla0i_avc2_v1 "cmvsla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla0i")) - "cmvsla0i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x2) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat70)) (c-call "check_option_cp" pc) -(set concat70 (sll (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat70 0)) -(set avc2copCCR3 (subword SI concat70 1)) -) - ()) -(dn16i cmvsra0i_avc2_v1 "cmvsra0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra0i")) - "cmvsra0i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat71)) (c-call "check_option_cp" pc) -(set concat71 (sra (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat71 0)) -(set avc2copCCR3 (subword SI concat71 1)) -) - ()) -(dn16i cmvsla1i_avc2_v1 "cmvsla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla1i")) - "cmvsla1i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x3) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat72)) (c-call "check_option_cp" pc) -(set concat72 (sll (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat72 0)) -(set avc2copCCR5 (subword SI concat72 1)) -) - ()) -(dn16i cmvsra1i_avc2_v1 "cmvsra1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra1i")) - "cmvsra1i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat73)) (c-call "check_option_cp" pc) -(set concat73 (sra (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat73 0)) -(set avc2copCCR5 (subword SI concat73 1)) -) - ()) -(dn16i csraa0i_avc2_v1 "csraa0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0i")) - "csraa0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat74)) (c-call "check_option_cp" pc) -(set concat74 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat74 0)) -(set avc2copCCR3 (subword SI concat74 1)) -) - ()) -(dn16i csraa1i_avc2_v1 "csraa1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1i")) - "csraa1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat75)) (c-call "check_option_cp" pc) -(set concat75 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat75 0)) -(set avc2copCCR5 (subword SI concat75 1)) -) - ()) -(dn16i csrla0i_avc2_v1 "csrla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0i")) - "csrla0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat76)) (c-call "check_option_cp" pc) -(set concat76 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat76 0)) -(set avc2copCCR3 (subword SI concat76 1)) -) - ()) -(dn16i csrla1i_avc2_v1 "csrla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1i")) - "csrla1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat77)) (c-call "check_option_cp" pc) -(set concat77 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat77 0)) -(set avc2copCCR5 (subword SI concat77 1)) -) - ()) -(dn16i cslla0i_avc2_v1 "cslla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0i")) - "cslla0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat78)) (c-call "check_option_cp" pc) -(set concat78 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat78 0)) -(set avc2copCCR3 (subword SI concat78 1)) -) - ()) -(dn16i cslla1i_avc2_v1 "cslla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1i")) - "cslla1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat79)) (c-call "check_option_cp" pc) -(set concat79 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat79 0)) -(set avc2copCCR5 (subword SI concat79 1)) -) - ()) -(dn16i csraa0_avc2_v1 "csraa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0")) - "csraa0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat80)) (c-call "check_option_cp" pc) -(set concat80 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat80 0)) -(set avc2copCCR3 (subword SI concat80 1)) -) - ()) -(dn16i csraa1_avc2_v1 "csraa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1")) - "csraa1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat81)) (c-call "check_option_cp" pc) -(set concat81 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat81 0)) -(set avc2copCCR5 (subword SI concat81 1)) -) - ()) -(dn16i csrla0_avc2_v1 "csrla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0")) - "csrla0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat82)) (c-call "check_option_cp" pc) -(set concat82 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat82 0)) -(set avc2copCCR3 (subword SI concat82 1)) -) - ()) -(dn16i csrla1_avc2_v1 "csrla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1")) - "csrla1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat83)) (c-call "check_option_cp" pc) -(set concat83 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat83 0)) -(set avc2copCCR5 (subword SI concat83 1)) -) - ()) -(dn16i cslla0_avc2_v1 "cslla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0")) - "cslla0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat84)) (c-call "check_option_cp" pc) -(set concat84 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat84 0)) -(set avc2copCCR3 (subword SI concat84 1)) -) - ()) -(dn16i cslla1_avc2_v1 "cslla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1")) - "cslla1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat85)) (c-call "check_option_cp" pc) -(set concat85 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat85 0)) -(set avc2copCCR5 (subword SI concat85 1)) -) - ()) -(dn16i cadda0_avc2_v1 "cadda0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda0")) - "cadda0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat86)) (c-call "check_option_cp" pc) -(set concat86 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq))) -(set avc2copCCR2 (subword SI concat86 0)) -(set avc2copCCR3 (subword SI concat86 1)) -) - ()) -(dn16i cadda1_avc2_v1 "cadda1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda1")) - "cadda1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat87)) (c-call "check_option_cp" pc) -(set concat87 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq))) -(set avc2copCCR4 (subword SI concat87 0)) -(set avc2copCCR5 (subword SI concat87 1)) -) - ()) -(dn16i csuba0_avc2_v1 "csuba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba0")) - "csuba0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat88)) (c-call "check_option_cp" pc) -(set concat88 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq))) -(set avc2copCCR2 (subword SI concat88 0)) -(set avc2copCCR3 (subword SI concat88 1)) -) - ()) -(dn16i csuba1_avc2_v1 "csuba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba1")) - "csuba1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat89)) (c-call "check_option_cp" pc) -(set concat89 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq))) -(set avc2copCCR4 (subword SI concat89 0)) -(set avc2copCCR5 (subword SI concat89 1)) -) - ()) -(dn16i cadd2a0_avc2_v1 "cadd2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a0")) - "cadd2a0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat90)) (c-call "check_option_cp" pc) -(set concat90 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat90 0)) -(set avc2copCCR3 (subword SI concat90 1)) -) - ()) -(dn16i cadd2a1_avc2_v1 "cadd2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a1")) - "cadd2a1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat91)) (c-call "check_option_cp" pc) -(set concat91 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat91 0)) -(set avc2copCCR5 (subword SI concat91 1)) -) - ()) -(dn16i csub2a0_avc2_v1 "csub2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a0")) - "csub2a0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat92)) (c-call "check_option_cp" pc) -(set concat92 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat92 0)) -(set avc2copCCR3 (subword SI concat92 1)) -) - ()) -(dn16i csub2a1_avc2_v1 "csub2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a1")) - "csub2a1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat93)) (c-call "check_option_cp" pc) -(set concat93 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat93 0)) -(set avc2copCCR5 (subword SI concat93 1)) -) - ()) -(dn16i caddaa0_avc2_v1 "caddaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa0")) - "caddaa0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat94)) (c-call "check_option_cp" pc) -(set concat94 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat94 0)) -(set avc2copCCR3 (subword SI concat94 1)) -) - ()) -(dn16i caddaa1_avc2_v1 "caddaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa1")) - "caddaa1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat95)) (c-call "check_option_cp" pc) -(set concat95 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat95 0)) -(set avc2copCCR5 (subword SI concat95 1)) -) - ()) -(dn16i csubaa0_avc2_v1 "csubaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa0")) - "csubaa0" -(+ (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat96)) (c-call "check_option_cp" pc) -(set concat96 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat96 0)) -(set avc2copCCR3 (subword SI concat96 1)) -) - ()) -(dn16i csubaa1_avc2_v1 "csubaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa1")) - "csubaa1" -(+ (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat97)) (c-call "check_option_cp" pc) -(set concat97 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat97 0)) -(set avc2copCCR5 (subword SI concat97 1)) -) - ()) -(dn32i cmov1_avc2_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1")) - "cmov $avc2v3CRn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CRn avc2v3Rm) -) - ()) -(dn32i cmov2_avc2_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2")) - "cmov $avc2v3Rm,$avc2v3CRn" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CRn (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3Rm avc2v3CRn) -) - ()) -(dn32i cmovi_avc2_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi")) - "cmovi $avc2v3CRq,$avc2v3Imm16s4x24e32" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRq avc2v3Imm16s4x24e32 (f-avc2-v3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CRq (ext SI avc2v3Imm16s4x24e32)) -) - ()) -(dn32i cmovc1_avc2_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1")) - "cmovc $avc2v3CCRn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CCRn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CCRn avc2v3Rm) -) - ()) -(dn32i cmovc2_avc2_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2")) - "cmovc $avc2v3Rm,$avc2v3CCRn" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CCRn (f-avc2-v3sub4u28 #x3) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3Rm avc2v3CCRn) -) - ()) -(dn32i xmula0_avc2_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0")) - "xmula0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat98)) (c-call "check_option_cp" pc) -(set concat98 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))) -(set avc2copCCR2 (subword SI concat98 0)) -(set avc2copCCR3 (subword SI concat98 1)) -) - ()) -(dn32i xmulua0_avc2_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0")) - "xmulua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat99)) (c-call "check_option_cp" pc) -(set concat99 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))) -(set avc2copCCR2 (subword SI concat99 0)) -(set avc2copCCR3 (subword SI concat99 1)) -) - ()) -(dn32i xnmula0_avc2_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0")) - "xnmula0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat100)) (c-call "check_option_cp" pc) -(set concat100 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat100 0)) -(set avc2copCCR3 (subword SI concat100 1)) -) - ()) -(dn32i xmada0_avc2_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0")) - "xmada0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x4) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat101)) (c-call "check_option_cp" pc) -(set concat101 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat101 0)) -(set avc2copCCR3 (subword SI concat101 1)) -) - ()) -(dn32i xmadua0_avc2_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0")) - "xmadua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x5) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat102)) (c-call "check_option_cp" pc) -(set concat102 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat102 0)) -(set avc2copCCR3 (subword SI concat102 1)) -) - ()) -(dn32i xmsba0_avc2_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0")) - "xmsba0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x6) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat103)) (c-call "check_option_cp" pc) -(set concat103 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat103 0)) -(set avc2copCCR3 (subword SI concat103 1)) -) - ()) -(dn32i xmsbua0_avc2_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x7) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat104)) (c-call "check_option_cp" pc) -(set concat104 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat104 0)) -(set avc2copCCR3 (subword SI concat104 1)) -) - ()) -(dn32i xmula1_avc2_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1")) - "xmula1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x8) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat105)) (c-call "check_option_cp" pc) -(set concat105 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))) -(set avc2copCCR4 (subword SI concat105 0)) -(set avc2copCCR5 (subword SI concat105 1)) -) - ()) -(dn32i xmulua1_avc2_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1")) - "xmulua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x9) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat106)) (c-call "check_option_cp" pc) -(set concat106 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))) -(set avc2copCCR4 (subword SI concat106 0)) -(set avc2copCCR5 (subword SI concat106 1)) -) - ()) -(dn32i xnmula1_avc2_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1")) - "xnmula1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xa) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat107)) (c-call "check_option_cp" pc) -(set concat107 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat107 0)) -(set avc2copCCR5 (subword SI concat107 1)) -) - ()) -(dn32i xmada1_avc2_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1")) - "xmada1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xc) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat108)) (c-call "check_option_cp" pc) -(set concat108 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat108 0)) -(set avc2copCCR5 (subword SI concat108 1)) -) - ()) -(dn32i xmadua1_avc2_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1")) - "xmadua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xd) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat109)) (c-call "check_option_cp" pc) -(set concat109 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat109 0)) -(set avc2copCCR5 (subword SI concat109 1)) -) - ()) -(dn32i xmsba1_avc2_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1")) - "xmsba1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xe) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat110)) (c-call "check_option_cp" pc) -(set concat110 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat110 0)) -(set avc2copCCR5 (subword SI concat110 1)) -) - ()) -(dn32i xmsbua1_avc2_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xf) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat111)) (c-call "check_option_cp" pc) -(set concat111 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat111 0)) -(set avc2copCCR5 (subword SI concat111 1)) -) - ()) diff --git a/cpu/mep-c5.cpu b/cpu/mep-c5.cpu deleted file mode 100644 index e70cee8..0000000 --- a/cpu/mep-c5.cpu +++ /dev/null @@ -1,260 +0,0 @@ -; Insns introduced for the MeP-c5 core -; - -(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4) -(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4) -(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4) -(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4) -(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4) -(df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f) - -(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5) -(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20) - -(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5)) - "stcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 12)) - (c-call VOID "do_stcb" rn (and rma #xffff)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3)) - "ldcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 13)) - (set rn (c-call SI "do_ldcb" (and rma #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - -(dnci pref "cache prefetch" ((MACH c5) VOLATILE) - "pref $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 5)) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 rma pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci prefd "cache prefetch" ((MACH c5) VOLATILE) - "pref $cimm4,$sdisp16($rma)" - (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "casb3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0)) - (sequence () - (c-call VOID "do_casb3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - -(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "cash3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1)) - (sequence () - (c-call VOID "do_cash3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - -(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "casw3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2)) - (sequence () - (c-call VOID "do_casw3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - - - -(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "sbcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12))) - (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lbcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lbucp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "shcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12))) - (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lhcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lhucp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5)) - "lbucpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (add rma cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5)) - "lhucpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5)) - "lbucpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5)) - "lhucpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5)) - "lbucpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5)) - "lhucpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci uci "uci" ((MACH c5) VOLATILE) - "uci $rn,$rm,$uimm16" - (+ MAJ_15 rn rm (f-sub4 2) simm16) - (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8) -(dnf f-c5-rm "register m" (all-mep-isas) 8 4) -(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f) - -(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT - (f-c5-rm f-c5-16u16) - (sequence () ; insert - (set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16)) - (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff)) - ) - (sequence () ; extract - (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16) - (sll (ifield f-c5-rm) 16))) - ) - ) -(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20) - -(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT - (f-c5-rnm f-c5-16u16) - (sequence () ; insert - (set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16)) - (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff)) - ) - (sequence () ; extract - (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16) - (sll (ifield f-c5-rnm) 16))) - ) - ) -(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24) - -(dnci dsp "dsp" ((MACH c5) VOLATILE) - "dsp $rn,$rm,$uimm16" - (+ MAJ_15 rn rm (f-sub4 0) uimm16) - (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS) - "dsp0 $c5rnmuimm24" - (+ MAJ_15 c5rnmuimm24 (f-sub4 0)) - (c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc) - ((mep (unit u-exec)))) - -(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS) - "dsp1 $rn,$c5rmuimm20" - (+ MAJ_15 rn (f-sub4 0) c5rmuimm20) - (set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) diff --git a/cpu/mep-core.cpu b/cpu/mep-core.cpu deleted file mode 100644 index 18e09d1..0000000 --- a/cpu/mep-core.cpu +++ /dev/null @@ -1,3065 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2001, 2002, 2003, 2004, 2005 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -(include "simplify.inc") - -(define-pmacro isa-enum () - (isas mep -; begin-isa-enum - ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64 -; end-isa-enum - ) -) - -(define-arch - (name mep) - (comment "Toshiba MeP Media Engine") - (insn-lsb0? #f) ;; work around cgen limitation - (machs mep h1 c5) - isa-enum -) - -(define-isa - (name mep) - (comment "MeP core instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -; begin-isas -(define-isa - (name ext_core1) - (comment "MeP core extension instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_16) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_32) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_48) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_64) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) - -(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32)) - -(define-pmacro all-core-isa-list () mep,ext_core1) -; end-isas - -(define-cpu - (name mepf) - (comment "MeP family") - (endian either) - (insn-chunk-bitsize 16) - (word-bitsize 32) -) - -(define-mach - (name mep) - (comment "MeP media engine") - (cpu mepf) - isa-enum -) - -(define-mach - (name h1) - (comment "H1 media engine") - (cpu mepf) - isa-enum -) - -(define-mach - (name c5) - (comment "C5 media engine") - (cpu mepf) - isa-enum -) - -(define-model - (name mep) - (comment "MeP media engine processor") - (mach c5) ; mach gets changed by MeP-Integrator - - (unit u-exec "execution unit" () - 1 1 ; issue done - () () () ()) - - ; Branch unit - (unit u-branch "Branch Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - - ; Multiply unit - (unit u-multiply "Multiply Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Divide unit - (unit u-divide "Divide Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Stcb unit - (unit u-stcb "stcb Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Ldcb unit - (unit u-ldcb "ldcb Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Load gpr unit - (unit u-load-gpr "Load into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((loadreg INT -1)) ; outputs - () ; profile action (default) - ) - - (unit u-ldcb-gpr "Ldcb into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((loadreg INT -1)) ; outputs - () ; profile action (default) - ) - - ; Multiply into GPR unit - (unit u-mul-gpr "Multiply into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((resultreg INT -1)) ; outputs - () ; profile action (default) - ) - - ; Use gpr unit -- stalls if GPR not ready - (unit u-use-gpr "Use GPR Unit" () - 0 0 ; issue done - () ; state - ((usereg INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Use ctrl-reg unit -- stalls if CTRL-REG not ready - (unit u-use-ctrl-reg "Use CTRL-REG Unit" () - 0 0 ; issue done - () ; state - ((usereg INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Store ctrl-reg unit -- stalls if CTRL-REG not ready - (unit u-store-ctrl-reg "Store CTRL-REG Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((storereg INT -1)) ; outputs - () ; profile action (default) - ) -) - -; Hardware elements. - -(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ()) - -(define-hardware - (name h-gpr) - (comment "General purpose registers") - (attrs all-mep-isas CACHE-ADDR PROFILE) - (type register SI (16)) - (indices keyword "$" - (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) - ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) - ; "$8" is the preferred name for register 8, but "$tp", "$gp" - ; and "$sp" are preferred for their respective registers. - (fp 8) (tp 13) (gp 14) (sp 15) - ("12" 12) ("13" 13) ("14" 14) ("15" 15))) -) - -(define-hardware - (name h-csr) - (comment "Control/special registers") - (attrs all-mep-isas PROFILE) - (type register SI (32)) - (indices keyword "$" - ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6) - (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15) - (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21) - (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28) -; begin-extra-csr-registers - (vid 22) -; end-extra-csr-registers - )) - (get (index) (c-call SI "cgen_get_csr_value" index)) - (set (index newval) (c-call VOID "cgen_set_csr_value" index newval)) -) - -(define-pmacro (-reg-pair n) ((.sym n) n)) -(define-hardware - (name h-cr64) - (comment "64-bit coprocessor registers") - (attrs all-mep-isas) - ; This assumes that the data path of the co-pro is 64 bits. - (type register DI (32)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) - (set (index newval) (c-call VOID "h_cr64_queue_set" index newval)) -) -(define-hardware - (name h-cr64-w) - (comment "64-bit coprocessor registers, pending writes") - (attrs all-mep-isas) - ; This assumes that the data path of the co-pro is 64 bits. - (type register DI (32)) -) - -(define-hardware - (name h-cr) - (comment "32-bit coprocessor registers") - (attrs all-mep-isas VIRTUAL) - (type register SI (32)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) -) - -;; Given a coprocessor control register number N, expand to a -;; name/index pair: ($ccrN N) -(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n)) - -(define-hardware - (name h-ccr) - (comment "Coprocessor control registers") - (attrs all-mep-isas) - (type register SI (64)) - (indices keyword "" (.map -ccr-reg-pair (.iota 64))) - (set (index newval) (c-call VOID "h_ccr_queue_set" index newval)) -) -(define-hardware - (name h-ccr-w) - (comment "Coprocessor control registers, pending writes") - (attrs all-mep-isas) - (type register SI (64)) -) - - -; Instruction fields. Bit numbering reversed. - -; Conventions: -; -; N = number of bits in value -; A = alignment (2 or 4, omit for 1) -; B = leftmost (i.e. closest to zero) bit position -; -; -- Generic Fields (f-*) -- -; N number of bits in *value* (1-24) -; [us] signed vs unsigned -; B position of left-most bit (4-16) -; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc) -; n opt. for noncontiguous fields -; f-foo-{hi,lo} msb/lsb parts of field f-foo -; -; -- Operands -- -; pcrelNaA PC-relative branch target (signed) -; pcabsNaA Absolute branch target (unsigned) -; -; [us]dispNaA [un]signed displacement -; [us]immN [un]signed immediate value -; addrNaA absolute address (unsigned) -; -; Additional prefixes may be used for special cases. - -(dnf f-major "major opcode" (all-mep-core-isas) 0 4) - -(dnf f-rn "register n" (all-mep-core-isas) 4 4) -(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3) -(dnf f-rm "register m" (all-mep-core-isas) 8 4) -(dnf f-rl "register l" (all-mep-core-isas) 12 4) -(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2) -(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3) -(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4) -(dnf f-ext "extended field" (all-mep-core-isas) 16 8) -(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4) -(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2) -(dnf f-crn "copro register n" (all-mep-core-isas) 4 4) - -(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f) -(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f) -(define-multi-ifield - (name f-csrn) - (comment "control reg") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-csrn-hi f-csrn-lo) - (insert (sequence () - (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf)) - (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4)))) - (extract (set (ifield f-csrn) - (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo)))) - ) - -(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f) -(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) -(define-multi-ifield - (name f-crnx) - (comment "copro register n (0-31)") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-crnx-hi f-crnx-lo) - (insert (sequence () - (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf)) - (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4)))) - (extract (set (ifield f-crnx) - (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo)))) - ) - -; Miscellaneous fields. - -(define-pmacro (dnfb n) - (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1)) - -; Define small fields used throughout the instruction set description. -; Each field (eg. `f-N') is at single bit field at position N. - -(dnfb 0) -(dnfb 1) -(dnfb 2) -(dnfb 3) -(dnfb 4) -(dnfb 5) -(dnfb 6) -(dnfb 7) -(dnfb 8) -(dnfb 9) -(dnfb 10) -(dnfb 11) -(dnfb 12) -(dnfb 13) -(dnfb 14) -(dnfb 15) -(dnfb 16) -(dnfb 17) -(dnfb 18) -(dnfb 19) -(dnfb 20) -(dnfb 21) -(dnfb 22) -(dnfb 23) -(dnfb 24) -(dnfb 25) -(dnfb 26) -(dnfb 27) -(dnfb 28) -(dnfb 29) -(dnfb 30) -(dnfb 31) - -; Branch/Jump target addresses - -(df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f) -(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f) -(define-multi-ifield - (name f-24s5a2n) - (comment "pc-rel addr (24 bits align 2)") - (attrs all-mep-core-isas PCREL-ADDR) - (mode INT) - (subfields f-24s5a2n-hi f-24s5a2n-lo) - (insert (sequence () - (set (ifield f-24s5a2n) - (sub (ifield f-24s5a2n) pc)) - (set (ifield f-24s5a2n-lo) - (srl (and (ifield f-24s5a2n) #xfe) 1)) - (set (ifield f-24s5a2n-hi) - (sra INT (ifield f-24s5a2n) 8)))) - (extract (set (ifield f-24s5a2n) - (add SI (or (sll (ifield f-24s5a2n-hi) 8) - (sll (ifield f-24s5a2n-lo) 1)) - pc))) - ) - -(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f) -(define-multi-ifield - (name f-24u5a2n) - (comment "abs jump target (24 bits, alignment 2)") - (attrs all-mep-core-isas ABS-ADDR) - (mode UINT) - (subfields f-24u5a2n-hi f-24u5a2n-lo) - (insert (sequence () - (set (ifield f-24u5a2n-lo) - (srl (and (ifield f-24u5a2n) #xff) 1)) - (set (ifield f-24u5a2n-hi) - (srl (ifield f-24u5a2n) 8)) - )) - (extract (set (ifield f-24u5a2n) - (or (sll (ifield f-24u5a2n-hi) 8) - (sll (ifield f-24u5a2n-lo) 1)))) - ) - -; Displacement fields. - -(df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f) -(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f) -(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT - ((value pc) (srl SI value 1)) - ((value pc) (sll SI value 1))) -(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT - ((value pc) (srl SI value 2)) - ((value pc) (sll SI value 2))) -(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f) - -; Immediate fields. - -(df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f) -(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f) -(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f) -(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f) -(df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f) -(df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f) -(df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f) -(df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f) -(df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f) - - -; These are all for the coprocessor opcodes - -; The field is like IJKiiiiiii where I and J are toggled if K is set, -; for compatibility with older cores. -(define-pmacro (compute-cdisp10 val) - (cond SI - ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200) - (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400)) - (else - (cond SI ((and SI val #x80) (xor SI val #x300)) (else val))) - ) - ) -(define-pmacro (extend-cdisp10 val) - (cond SI - ((and SI (compute-cdisp10 val) #x200) - (sub (and SI (compute-cdisp10 val) #x3ff) #x400)) - (else - (and SI (compute-cdisp10 val) #x3ff)) - ) - ) - -(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 INT - ((value pc) (extend-cdisp10 value)) - ((value pc) (extend-cdisp10 value)) - ) - -; Non-contiguous fields. - -(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f) -(define-multi-ifield - (name f-24u8a4n) - (comment "absolute 24-bit address") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u8a4n-hi f-24u8a4n-lo) - (insert (sequence () - (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8)) - (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2)))) - (extract (set (ifield f-24u8a4n) - (or (sll (ifield f-24u8a4n-hi) 8) - (sll (ifield f-24u8a4n-lo) 2)))) - ) - -(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f) -(define-multi-ifield - (name f-24u8n) - (comment "24-bit constant") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u8n-hi f-24u8n-lo) - (insert (sequence () - (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8)) - (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff)))) - (extract (set (ifield f-24u8n) - (or (sll (ifield f-24u8n-hi) 8) - (ifield f-24u8n-lo)))) - ) - -(df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f) -(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(define-multi-ifield - (name f-24u4n) - (comment "coprocessor code") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u4n-hi f-24u4n-lo) - (insert (sequence () - (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16)) - (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff)))) - (extract (set (ifield f-24u4n) - (or (sll (ifield f-24u4n-hi) 16) - (ifield f-24u4n-lo)))) - ) - -(define-multi-ifield - (name f-callnum) - (comment "system call number field") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-5 f-6 f-7 f-11) - (insert (sequence () - (set (ifield f-5) (and (srl (ifield f-callnum) 3) 1)) - (set (ifield f-6) (and (srl (ifield f-callnum) 2) 1)) - (set (ifield f-7) (and (srl (ifield f-callnum) 1) 1)) - (set (ifield f-11) (and (ifield f-callnum) 1)))) - (extract (set (ifield f-callnum) - (or (sll (ifield f-5) 3) - (or (sll (ifield f-6) 2) - (or (sll (ifield f-7) 1) - (ifield f-11)))))) - ) - -(df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f) -(df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) -(define-multi-ifield - (name f-ccrn) - (comment "Coprocessor register number field") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-ccrn-hi f-ccrn-lo) - (insert (sequence () - (set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3)) - (set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf)))) - (extract (set (ifield f-ccrn) - (or (sll (ifield f-ccrn-hi) 4) - (ifield f-ccrn-lo)))) - ) - -; Operands. - -;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct -;; operation. The others are mostly kept for backwards compatibility, -;; although they do affect the dummy prototypes in -;; gcc/config/mep/intrinsics.h. -(define-attr - (type enum) - (for operand) - (name CDATA) - (comment "datatype to use for C intrinsics mapping") - (values LABEL REGNUM FMAX_FLOAT FMAX_INT - POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT) - (default LONG)) - -(define-attr - (type enum) - (for insn) - (name CPTYPE) - (comment "datatype to use for coprocessor values") - (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI) - (default CP_DATA_BUS_INT)) - -(define-attr - (type enum) - (for insn) - (name CRET) - ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed. - ;; FIRST - the first argument is the return value. - ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter. - (values VOID FIRST FIRSTCOPY) - (default VOID) - (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.")) - -(define-attr - (type integer) - (for operand) - (name ALIGN) - (comment "alignment of immediate operands") - (default 1)) - -(define-attr - (for operand) - (type boolean) - (name RELOC_IMPLIES_OVERFLOW) - (comment "Operand should not be considered as a candidate for relocs")) - -(define-attr - (for hardware) - (type boolean) - (name IS_FLOAT) - (comment "Register contains a floating point value")) - -(define-pmacro (dpop name commment attrib hwr field func) - (define-full-operand name comment attrib - hwr DFLT field ((parse func)) () ())) -(define-pmacro (dprp name commment attrib hwr field pafunc prfunc) - (define-full-operand name comment attrib - hwr DFLT field ((parse pafunc) (print prfunc)) () ())) - -(dnop r0 "register 0" (all-mep-core-isas) h-gpr 0) -(dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn) -(dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm) -(dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl) -(dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3) - -;; Variants of RM/RN with different CDATA attributes. See comment above -;; CDATA for more details. - -(dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm) - -(dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn) - -(dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3) - - -(dnop lp "link pointer" (all-mep-core-isas) h-csr 1) -(dnop sar "shift amount register" (all-mep-core-isas) h-csr 2) -(dnop hi "high result" (all-mep-core-isas) h-csr 7) -(dnop lo "low result" (all-mep-core-isas) h-csr 8) -(dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12) -(dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13) -(dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14) -(dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15) -(dnop psw "program status word" (all-mep-core-isas) h-csr 16) -(dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19) -(dnop exc "exception cause" (all-mep-core-isas) h-csr 20) -(dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23) -(dnop dbg "debug register" (all-mep-core-isas) h-csr 24) -(dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25) -(dnop opt "option register" (all-mep-core-isas) h-csr 26) -(dnop r1 "register 1" (all-mep-core-isas) h-gpr 1) -(dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13) -(dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15) -(dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg") -(dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg") - -(define-full-operand - csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr - DFLT f-csrn ((parse "csrn")) () () -) - -(dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn) -(dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn) -(dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn) -(dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx) -(dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx) -(dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn) -(dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm) - -(dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address") -(dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address") -(dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address") -(dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address") -(dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address") - -(dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") -(dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") -(dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16") -(dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16) - -(dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6) -(dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10) - -(dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8) -(dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW) - h-sint f-8s8) - -(dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu") -(dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n) - -(dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum) -(dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5) -(dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8) -(dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8) - -(dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7") -(dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7") -(dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7") -(dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu") - -(dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n) - -(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn) -(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24) - -(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") - -; Special operand representing the various ways that the literal zero can be -; specified. -(define-full-operand - zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil - ((parse "zero")) () () -) - -; Attributes. - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_BIT_INSN) - (comment "optional bit manipulation instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_MUL_INSN) - (comment "optional 32-bit multiply instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DIV_INSN) - (comment "optional 32-bit divide instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DEBUG_INSN) - (comment "optional debug instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_LDZ_INSN) - (comment "optional leading zeroes instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_ABS_INSN) - (comment "optional absolute difference instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_AVE_INSN) - (comment "optional average instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_MINMAX_INSN) - (comment "optional min/max instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CLIP_INSN) - (comment "optional clipping instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_SAT_INSN) - (comment "optional saturation instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_UCI_INSN) - (comment "optional UCI instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DSP_INSN) - (comment "optional DSP instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CP_INSN) - (comment "optional coprocessor-related instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CP64_INSN) - (comment "optional coprocessor-related 64 data bit instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_VLIW64) - (comment "optional vliw64 mode (vliw32 is default)")) - -(define-attr - (for insn) - (type enum) - (name STALL) - (attrs META) - (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET - ADVCK MUL MULR DIV) - (default NONE) - (comment "gcc stall attribute")) - -(define-attr - (for insn) - (type string) - (name INTRINSIC) - (attrs META) - (comment "gcc intrinsic name")) - -(define-attr - (for insn) - (type enum) - (name SLOT) - (attrs META) - (values NONE C3 V1 V3 P0S P0 P1) - (default NONE) - (comment "coprocessor slot type")) - -(define-attr - (for insn) - (type boolean) - (name MAY_TRAP) - (comment "instruction may generate an exception")) - -; Attributes for scheduling restrictions in vliw mode - -(define-attr - (for insn) - (type boolean) - (name VLIW_ALONE) - (comment "instruction can be scheduled alone in vliw mode")) - -(define-attr - (for insn) - (type boolean) - (name VLIW_NO_CORE_NOP) - (comment "there is no corresponding nop core instruction")) - -(define-attr - (for insn) - (type boolean) - (name VLIW_NO_COP_NOP) - (comment "there is no corresponding nop coprocessor instruction")) - -(define-attr - (for insn) - (type boolean) - (name VLIW64_NO_MATCHING_NOP) - (comment "there is no corresponding nop coprocessor instruction")) -(define-attr - (for insn) - (type boolean) - (name VLIW32_NO_MATCHING_NOP) - (comment "there is no corresponding nop coprocessor instruction")) - -(define-attr - (for insn) - (type boolean) - (name VOLATILE) - (comment "Insn is volatile.")) - -(define-attr - (for insn) - (type integer) - (name LATENCY) - (comment "The latency of this insn, used for scheduling as an intrinsic in gcc") - (default 0)) - -; The MeP config tool will edit this. -(define-attr - (type enum) - (for insn) - (name CONFIG) - (values NONE ; config-attr-start - default - ) ; config-attr-end -) - - -; Enumerations. - -(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_ - f-major - (.map .str (.iota 16)) -) - - -(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa) - (define-insn - (name xname) - (comment xcomment) - (.splice attrs (.unsplice xattrs) (ISA isa)) - (syntax xsyntax) - (format xformat) - (semantics xsemantics) - (.splice timing (.unsplice xtiming)) - ) -) - -(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa) - (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit) -) - -; For making profiling calls and dynamic configuration -(define-pmacro (cg-profile caller callee) - (c-call "cg_profile" caller callee) -) -; For dynamic configuration only -(define-pmacro (cg-profile-jump caller callee) - (c-call "cg_profile_jump" caller callee) -) - -; For defining Core Instructions -(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list) -) -(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit) - (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list) -) - -; For defining Coprocessor Instructions -;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop) -;) - -;; flag setting macro -(define-pmacro (set-bit xop xbitnum xval) - (set xop (or - (and xop (inv (sll 1 xbitnum))) - (and (sll 1 xbitnum) (sll xval xbitnum))))) - -;; some flags we commonly use in vliw reasoning / mode-switching etc. -(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1)) -(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1)) -(define-pmacro (get-rm.lsb) (and rm 1)) -(define-pmacro (get-psw.om) (and (srl psw 12) 1)) -(define-pmacro (get-psw.nmi) (and (srl psw 9) 1)) -(define-pmacro (get-psw.iep) (and (srl psw 1) 1)) -(define-pmacro (get-psw.ump) (and (srl psw 3) 1)) -(define-pmacro (get-epc.etom) (and epc 1)) -(define-pmacro (get-npc.ntom) (and npc 1)) -(define-pmacro (get-lp.ltom) (and lp 1)) - -(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval)) -(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval)) -(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval)) -(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval)) -(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval)) - - -;; the "3 way switch" depending on our current operating mode and vliw status flags -(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl) - (cond - ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl) - ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl) - (else core-rtl))) - -;; the varying-pcrel idiom -(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc) - (core-vliw-switch (set xtarg (add pc xa)) - (set xtarg (add pc xb)) - (set xtarg (add pc xc)))) - -;; the increasing-alignment idiom in branch displacements -(define-pmacro (set-vliw-alignment-modified xtarg zaddr) - (core-vliw-switch (set xtarg (and zaddr (inv 1))) - (set xtarg (and zaddr (inv 3))) - (set xtarg (and zaddr (inv 7))))) - -;; the increasing-alignment idiom in option-only form -(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr) - (if (get-opt.vliw32) - (set xtarg (and zaddr (inv 3))) - (set xtarg (and zaddr (inv 7))))) - - - -; pmacros needed for coprocessor modulo addressing. - -; Taken from supplement ``The operation of the modulo addressing'' in -; Toshiba documentation rev 2.2, p. 34. - -(define-pmacro (compute-mask0) - (sequence SI ((SI temp)) - (set temp (or mb0 me0)) - (srl (const SI -1) (c-call SI "do_ldz" temp)))) - -(define-pmacro (mod0 immed) - (sequence SI ((SI modulo-mask)) - (set modulo-mask (compute-mask0)) - (if SI (eq (and rma modulo-mask) me0) - (or (and rma (inv modulo-mask)) mb0) - (add rma (ext SI immed))))) - -(define-pmacro (compute-mask1) - (sequence SI ((SI temp)) - (set temp (or mb1 me1)) - (srl (const SI -1) (c-call SI "do_ldz" temp)))) - -(define-pmacro (mod1 immed) - (sequence SI ((SI modulo-mask)) - (set modulo-mask (compute-mask1)) - (if SI (eq (and rma modulo-mask) me1) - (or (and rma (inv modulo-mask)) mb1) - (add rma (ext SI immed))))) - - -; Instructions. - -; A pmacro for use in semantic bodies of unimplemented insns. -(define-pmacro (unimp mnemonic) (nop)) - -; Core specific instructions -; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator -(include "mep-c5.cpu") ; -- exposed by MeP-Integrator - -; Load/store instructions. - -(dnci sb "store byte (register indirect)" ((STALL STORE)) - "sb $rnc,($rma)" - (+ MAJ_0 rnc rma (f-sub4 8)) - (sequence () - (c-call VOID "check_write_to_text" rma) - (set (mem UQI rma) (and rnc #xff))) - ((mep (unit u-use-gpr (in usereg rnc)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sh "store half-word (register indirect)" ((STALL STORE)) - "sh $rns,($rma)" - (+ MAJ_0 rns rma (f-sub4 9)) - (sequence () - (c-call VOID "check_write_to_text" (and rma (inv 1))) - (set (mem UHI (and rma (inv 1))) (and rns #xffff))) - ((mep (unit u-use-gpr (in usereg rns)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sw "store word (register indirect)" ((STALL STORE)) - "sw $rnl,($rma)" - (+ MAJ_0 rnl rma (f-sub4 10)) - (sequence () - (c-call VOID "check_write_to_text" (and rma (inv 3))) - (set (mem USI (and rma (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lb $rnc,($rma)" - (+ MAJ_0 rnc rma (f-sub4 12)) - (set rnc (ext SI (mem QI rma))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnc))))) - -(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lh $rns,($rma)" - (+ MAJ_0 rns rma (f-sub4 13)) - (set rns (ext SI (mem HI (and rma (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rns))))) - -(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,($rma)" - (+ MAJ_0 rnl rma (f-sub4 14)) - (set rnl (mem SI (and rma (inv 3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lbu $rnuc,($rma)" - (+ MAJ_0 rnuc rma (f-sub4 11)) - (set rnuc (zext SI (mem UQI rma))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnuc))))) - -(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lhu $rnus,($rma)" - (+ MAJ_0 rnus rma (f-sub4 15)) - (set rnus (zext SI (mem UHI (and rma (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnus))))) - -(dnci sw-sp "store word (sp relative)" ((STALL STORE)) - "sw $rnl,$udisp7a4($spr)" - (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3))) - (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg sp)) - (unit u-exec)))) - - -(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,$udisp7a4($spr)" - (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3)) - (set rnl (mem SI (and (add udisp7a4 sp) (inv 3)))) - ((mep (unit u-use-gpr (in usereg sp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci sb-tp "store byte (tp relative)" ((STALL STORE)) - "sb $rn3c,$udisp7($tpr)" - (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7) - (sequence () - (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp)) - (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff))) - ((mep (unit u-use-gpr (in usereg rn3c)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci sh-tp "store half-word (tp relative)" ((STALL STORE)) - "sh $rn3s,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0)) - (sequence () - (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1))) - (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff))) - ((mep (unit u-use-gpr (in usereg rn3s)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci sw-tp "store word (tp relative)" ((STALL STORE)) - "sw $rn3l,$udisp7a4($tpr)" - (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3))) - (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l)) - ((mep (unit u-use-gpr (in usereg rn3l)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lb $rn3c,$udisp7($tpr)" - (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7) - (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3c))))) - -(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lh $rn3s,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0)) - (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3s))))) - -(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lw $rn3l,$udisp7a4($tpr)" - (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3)) - (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3l))))) - -(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lbu $rn3uc,$udisp7($tpr)" - (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7) - (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3uc))))) - -(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lhu $rn3us,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1)) - (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3us))))) - -(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE)) - "sb $rnc,$sdisp16($rma)" - (+ MAJ_12 rnc rma (f-sub4 8) sdisp16) - (sequence () - (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16))) - (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff))) - ((mep (unit u-use-gpr (in usereg rnc)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE)) - "sh $rns,$sdisp16($rma)" - (+ MAJ_12 rns rma (f-sub4 9) sdisp16) - (sequence () - (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1))) - (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff))) - ((mep (unit u-use-gpr (in usereg rns)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sw16 "store word (16 bit displacement)" ((STALL STORE)) - "sw $rnl,$sdisp16($rma)" - (+ MAJ_12 rnl rma (f-sub4 10) sdisp16) - (sequence () - (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3))) - (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lb $rnc,$sdisp16($rma)" - (+ MAJ_12 rnc rma (f-sub4 12) sdisp16) - (set rnc (ext SI (mem QI (add rma (ext SI sdisp16))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnc))))) - -(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lh $rns,$sdisp16($rma)" - (+ MAJ_12 rns rma (f-sub4 13) sdisp16) - (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rns))))) - -(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,$sdisp16($rma)" - (+ MAJ_12 rnl rma (f-sub4 14) sdisp16) - (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lbu $rnuc,$sdisp16($rma)" - (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16) - (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnuc))))) - -(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lhu $rnus,$sdisp16($rma)" - (+ MAJ_12 rnus rma (f-sub4 15) sdisp16) - (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnus))))) - -(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE)) - "sw $rnl,($addr24a4)" - (+ MAJ_14 rnl addr24a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (zext SI addr24a4)) - (set (mem SI (zext SI addr24a4)) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-exec)))) - -(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,($addr24a4)" - (+ MAJ_14 rnl addr24a4 (f-sub2 3)) - (set rnl (mem SI (zext SI addr24a4))) - ((mep (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - - -; Extension instructions. - -(dnci extb "sign extend byte" () - "extb $rn" - (+ MAJ_1 rn (f-rm 0) (f-sub4 13)) - (set rn (ext SI (and QI rn #xff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci exth "sign extend half-word" () - "exth $rn" - (+ MAJ_1 rn (f-rm 2) (f-sub4 13)) - (set rn (ext SI (and HI rn #xffff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci extub "zero extend byte" () - "extub $rn" - (+ MAJ_1 rn (f-rm 8) (f-sub4 13)) - (set rn (zext SI (and rn #xff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci extuh "zero extend half-word" () - "extuh $rn" - (+ MAJ_1 rn (f-rm 10) (f-sub4 13)) - (set rn (zext SI (and rn #xffff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Shift amount manipulation instructions. - -(dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE) - "ssarb $udisp2($rm)" - (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12)) - (if (c-call BI "big_endian_p") - (set sar (zext SI (mul (and (add udisp2 rm) 3) 8))) - (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8))))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Move instructions. - -(dnci mov "move" () - "mov $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 0)) - (set rn rm) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci movi8 "move 8-bit immediate" () - "mov $rn,$simm8" - (+ MAJ_5 rn simm8) - (set rn (ext SI simm8)) - ()) - -(dnci movi16 "move 16-bit immediate" () - "mov $rn,$simm16" - (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16) - (set rn (ext SI simm16)) - ()) - -(dnci movu24 "move 24-bit unsigned immediate" () - "movu $rn3,$uimm24" - (+ MAJ_13 (f-4 0) rn3 uimm24) - (set rn3 (zext SI uimm24)) - ()) - -(dnci movu16 "move 16-bit unsigned immediate" () - "movu $rn,$uimm16" - (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16) - (set rn (zext SI uimm16)) - ()) - -(dnci movh "move high 16-bit immediate" () - "movh $rn,$uimm16" - (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16) - (set rn (sll uimm16 16)) - ()) - - -; Arithmetic instructions. - -(dnci add3 "add three registers" () - "add3 $rl,$rn,$rm" - (+ MAJ_9 rn rm rl) - (set rl (add rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci add "add" () - "add $rn,$simm6" - (+ MAJ_6 rn simm6 (f-sub2 0)) - (set rn (add rn (ext SI simm6))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci add3i "add two registers and immediate" () - "add3 $rn,$spr,$uimm7a4" - (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0)) - (set rn (add sp (zext SI uimm7a4))) - ((mep (unit u-use-gpr (in usereg sp)) - (unit u-exec)))) - -(dnci advck3 "add overflow check" ((STALL ADVCK)) - "advck3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 7)) - (if (add-oflag rn rm 0) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sub "subtract" () - "sub $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 4)) - (set rn (sub rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm))))) - -(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK)) - "sbvck3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 5)) - (if (sub-oflag rn rm 0) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci neg "negate" () - "neg $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 1)) - (set rn (neg rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3 "set if less than" () - "slt3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 2)) - (if (lt rn rm) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sltu3 "set less than unsigned" () - "sltu3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 3)) - (if (ltu rn rm) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3i "set if less than immediate" () - "slt3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 1)) - (if (lt rn (zext SI uimm5)) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci sltu3i "set if less than unsigned immediate" () - "sltu3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 5)) - (if (ltu rn (zext SI uimm5)) - (set r0 1) - (set r0 0)) - ()) - -(dnci sl1ad3 "shift left one and add" ((STALL INT2)) - "sl1ad3 \\$0,$rn,$rm" - (+ MAJ_2 rn rm (f-sub4 6)) - (set r0 (add (sll rn 1) rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sl2ad3 "shift left two and add" ((STALL INT2)) - "sl2ad3 \\$0,$rn,$rm" - (+ MAJ_2 rn rm (f-sub4 7)) - (set r0 (add (sll rn 2) rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci add3x "three operand add (extended)" () - "add3 $rn,$rm,$simm16" - (+ MAJ_12 rn rm (f-sub4 0) simm16) - (set rn (add rm (ext SI simm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3x "set if less than (extended)" () - "slt3 $rn,$rm,$simm16" - (+ MAJ_12 rn rm (f-sub4 2) simm16) - (if (lt rm (ext SI simm16)) - (set rn 1) - (set rn 0)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sltu3x "set if less than unsigned (extended)" () - "sltu3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 3) uimm16) - (if (ltu rm (zext SI uimm16)) - (set rn 1) - (set rn 0)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Logical instructions. - -(dnci or "bitwise or" () - "or $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 0)) - (set rn (or rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci and "bitwise and" () - "and $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 1)) - (set rn (and rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci xor "bitwise exclusive or" () - "xor $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 2)) - (set rn (xor rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci nor "bitwise negated or" () - "nor $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 3)) - (set rn (inv (or rn rm))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci or3 "or three operand" () - "or3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 4) uimm16) - (set rn (or rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci and3 "and three operand" () - "and3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 5) uimm16) - (set rn (and rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci xor3 "exclusive or three operand" () - "xor3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 6) uimm16) - (set rn (xor rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Shift instructions. - -(dnci sra "shift right arithmetic" ((STALL INT2)) - "sra $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 13)) - (set rn (sra rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci srl "shift right logical" ((STALL INT2)) - "srl $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 12)) - (set rn (srl rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sll "shift left logical" ((STALL INT2)) - "sll $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 14)) - (set rn (sll rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI)) - "sra $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 3)) - (set rn (sra rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci srli "shift right logical (immediate)" ((STALL SHIFTI)) - "srl $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 2)) - (set rn (srl rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci slli "shift left logical (immediate)" ((STALL SHIFTI)) - "sll $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 6)) - (set rn (sll rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci sll3 "three-register shift left logical" ((STALL INT2)) - "sll3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 7)) - (set r0 (sll rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci fsft "field shift" ((STALL FSFT) VOLATILE) - "fsft $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 15)) - (sequence ((DI temp) (QI shamt)) - (set shamt (and sar #x3f)) - (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt)) - (set rn (subword SI (srl temp 32) 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Branch/jump instructions. - -(dnci bra "branch" (RELAXABLE) - "bra $pcrel12a2" - (+ MAJ_11 pcrel12a2 (f-15 0)) - (set-vliw-alignment-modified pc pcrel12a2) - ((mep (unit u-branch) - (unit u-exec)))) - -(dnci beqz "branch if equal zero" (RELAXABLE) - "beqz $rn,$pcrel8a2" - (+ MAJ_10 rn pcrel8a2 (f-15 0)) - (if (eq rn 0) - (set-vliw-alignment-modified pc pcrel8a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bnez "branch if not equal zero" (RELAXABLE) - "bnez $rn,$pcrel8a2" - (+ MAJ_10 rn pcrel8a2 (f-15 1)) - (if (ne rn 0) - (set-vliw-alignment-modified pc pcrel8a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci beqi "branch equal immediate" (RELAXABLE) - "beqi $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2) - (if (eq rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bnei "branch not equal immediate" (RELAXABLE) - "bnei $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2) - (if (ne rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci blti "branch less than immediate" (RELAXABLE) - "blti $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2) - (if (lt rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bgei "branch greater than immediate" (RELAXABLE) - "bgei $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2) - (if (ge rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci beq "branch equal" () - "beq $rn,$rm,$pcrel17a2" - (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2) - (if (eq rn rm) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bne "branch not equal" () - "bne $rn,$rm,$pcrel17a2" - (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2) - (if (ne rn rm) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE) - "bsr $pcrel12a2" - (+ MAJ_11 pcrel12a2 (f-15 1)) - (sequence () - (cg-profile pc pcrel12a2) - (set-vliw-modified-pcrel-offset lp 2 4 8) - (set-vliw-alignment-modified pc pcrel12a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci bsr24 "branch to subroutine (24 bit displacement)" () - "bsr $pcrel24a2" - (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2) - (sequence () - (cg-profile pc pcrel24a2) - (set-vliw-modified-pcrel-offset lp 4 4 8) - (set-vliw-alignment-modified pc pcrel24a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci jmp "jump" () - "jmp $rm" - (+ MAJ_1 (f-rn 0) rm (f-sub4 14)) - (sequence () - (if (eq (get-psw.om) 0) - ;; core mode - (if (get-rm.lsb) - (sequence () - (set-psw.om 1) ;; enter VLIW mode - (set-vliw-aliignment-modified-by-option pc rm)) - (set pc (and rm (inv 1)))) - ;; VLIW mode - (if (get-rm.lsb) - (sequence () - (set-psw.om 0) ;; enter core mode - (set pc (and rm (inv 1)))) - (set-vliw-aliignment-modified-by-option pc rm))) - (cg-profile-jump pc rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci jmp24 "jump (24 bit target)" () - "jmp $pcabs24a2" - (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2) - (sequence () - (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2)) - (cg-profile-jump pc pcabs24a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci jsr "jump to subroutine" () - "jsr $rm" - (+ MAJ_1 (f-rn 0) rm (f-sub4 15)) - (sequence () - (cg-profile pc rm) - (set-vliw-modified-pcrel-offset lp 2 4 8) - (set-vliw-alignment-modified pc rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci ret "return from subroutine" ((STALL RET)) - "ret" - (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2)) - (sequence () - (if (eq (get-psw.om) 0) - ;; core mode - (if (get-lp.ltom) ;; link-pointer "toggle mode" bit - (sequence () - (set-psw.om 1) ;; enter VLIW mode - (set-vliw-aliignment-modified-by-option pc lp)) - (set pc (and lp (inv 1)))) - ;; VLIW mode - (if (get-lp.ltom) ;; link-pointer "toggle mode" bit - (sequence () - (set-psw.om 0) ;; enter VLIW mode - (set pc (and lp (inv 1)))) - (set-vliw-aliignment-modified-by-option pc lp))) - (c-call VOID "notify_ret" pc)) - ((mep (unit u-exec) - (unit u-branch)))) - - -; Repeat instructions. - -(dnci repeat "repeat specified repeat block" () - "repeat $rn,$pcrel17a2" - (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2) - (sequence () - (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) - (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) - (set (reg h-csr 6) rn)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci erepeat "endless repeat" () - "erepeat $pcrel17a2" - (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2) - (sequence () - (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) - (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) - (set-rpe.elr 1) - ; rpc may be undefined for erepeat - ; use 1 to trigger repeat logic in the sim's main loop - (set (reg h-csr 6) 1)) - ()) - - -; Control instructions. - -;; special store variants - -(dnci stc_lp "store to control register lp" ((STALL STC)) - "stc $rn,\\$lp" - (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set lp rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg lp)) - (unit u-exec)))) - -(dnci stc_hi "store to control register hi" ((STALL STC)) - "stc $rn,\\$hi" - (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set hi rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg hi)) - (unit u-exec)))) - -(dnci stc_lo "store to control register lo" ((STALL STC)) - "stc $rn,\\$lo" - (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set lo rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg lo)) - (unit u-exec)))) - -;; general store - -(dnci stc "store to control register" (VOLATILE (STALL STC)) - "stc $rn,$csrn" - (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0)) - (set csrn rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg csrn)) - (unit u-exec)))) - -;; special load variants - -(dnci ldc_lp "load from control register lp" ((STALL LDC)) - "ldc $rn,\\$lp" - (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn lp) - ((mep (unit u-use-ctrl-reg (in usereg lp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - - -(dnci ldc_hi "load from control register hi" ((STALL LDC)) - "ldc $rn,\\$hi" - (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn hi) - ((mep (unit u-use-ctrl-reg (in usereg hi)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -(dnci ldc_lo "load from control register lo" ((STALL LDC)) - "ldc $rn,\\$lo" - (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn lo) - ((mep (unit u-use-ctrl-reg (in usereg lo)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -;; general load - -(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2)) - "ldc $rn,$csrn" - (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1)) - (if (eq (ifield f-csrn) 0) - ;; loading from the pc - (set-vliw-modified-pcrel-offset rn 2 4 8) - ;; loading from something else - (set rn csrn)) - ((mep (unit u-use-ctrl-reg (in usereg csrn)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -(dnci di "disable interrupt" (VOLATILE) - "di" - (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0)) - ; clear psw.iec - (set psw (sll (srl psw 1) 1)) - ()) - -(dnci ei "enable interrupt" (VOLATILE) - "ei" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0)) - ; set psw.iec - (set psw (or psw 1)) - ()) - -(dnci reti "return from interrupt" ((STALL RET)) - "reti" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2)) - (if (eq (get-psw.om) 0) - ;; core operation mode - (if (get-psw.nmi) - ;; return from NMI - (if (get-npc.ntom) - ;; return in VLIW operation mode - (sequence () - (set-psw.om 1) - (set-vliw-aliignment-modified-by-option pc npc) - (set-psw.nmi 0)) - ;; return in core mode - (sequence () - (set pc (and npc (inv 1))) - (set-psw.nmi 0))) - ;; return from non-NMI - (if (get-epc.etom) - ;; return in VLIW mode - (sequence () - (set-psw.om 1) - (set-vliw-aliignment-modified-by-option pc epc) - (set-psw.umc (get-psw.ump)) - (set-psw.iec (get-psw.iep))) - ;; return in core mode - (sequence () - (set pc (and epc (inv 1))) - (set-psw.umc (get-psw.ump)) - (set-psw.iec (get-psw.iep))))) - ;; VLIW operation mode - ;; xxx undefined - (nop)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci halt "halt pipeline" (VOLATILE) - "halt" - (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2)) - ; set psw.halt - (set (raw-reg h-csr 16) (or psw (sll 1 11))) - ()) - -(dnci sleep "sleep pipeline" (VOLATILE) - "sleep" - (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2)) - (c-call VOID "do_sleep") - ()) - -(dnci swi "software interrupt" (MAY_TRAP VOLATILE) - "swi $uimm2" - (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6)) - (cond - ((eq uimm2 0) (set exc (or exc (sll 1 4)))) - ((eq uimm2 1) (set exc (or exc (sll 1 5)))) - ((eq uimm2 2) (set exc (or exc (sll 1 6)))) - ((eq uimm2 3) (set exc (or exc (sll 1 7))))) - ()) - -(dnci break "break exception" (MAY_TRAP VOLATILE) - "break" - (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2)) - (set pc (c-call USI "break_exception" pc)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci syncm "synchronise with memory" (VOLATILE) - "syncm" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1)) - (unimp "syncm") - ()) - -(dnci stcb "store in control bus space" (VOLATILE (STALL STCB)) - "stcb $rn,$uimm16" - (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16) - (c-call VOID "do_stcb" rn uimm16) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3)) - "ldcb $rn,$uimm16" - (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16) - (set rn (c-call SI "do_ldcb" uimm16)) - ((mep (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - - -; Bit manipulation instructions. -; The following instructions become the reserved instruction when the -; bit manipulation option is off. - -(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN) - "bsetm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN) - "bclrm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN) - "bnotm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN) - "btstm \\$0,($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3)) - (sequence () - (c-call "check_option_bit" pc) - (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci tas "test and set" (OPTIONAL_BIT_INSN) - "tas $rn,($rma)" - (+ MAJ_2 rn rma (f-sub4 4)) - (sequence ((SI result)) - (c-call "check_option_bit" pc) - (set result (zext SI (mem UQI rma))) - (set (mem UQI rma) 1) - (set rn result)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -; Data cache instruction. - -(dnci cache "cache operations" (VOLATILE) - "cache $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 4)) - (c-call VOID "do_cache" cimm4 rma pc) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -; Multiply instructions. -; These instructions become the RI when the 32-bit multiply -; instruction option is off. - -(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL)) - "mul $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 4)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (ext DI rn) (ext DI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) - "mulu $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 5)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (zext UDI rn) (zext UDI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "mulr $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 6)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (ext DI rn) (ext DI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "mulru $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 7)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (zext UDI rn) (zext UDI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL)) - "madd $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (ext DI rn) (ext DI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) - "maddu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (zext UDI rn) (zext UDI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - - -(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "maddr $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (ext DI rn) (ext DI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "maddru $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (zext UDI rn) (zext UDI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - - -; Divide instructions. -; These instructions become the RI when the 32-bit divide instruction -; option is off. - -(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) - "div $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 8)) - (sequence () - (c-call "check_option_div" pc) - (if (eq rm 0) - (set pc (c-call USI "zdiv_exception" pc)) - ; Special case described on p. 76. - (if (and (eq rn #x80000000) - (eq rm #xffffffff)) - (sequence () - (set lo #x80000000) - (set hi 0)) - (sequence () - (set lo (div rn rm)) - (set hi (mod rn rm)))))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-divide) - (unit u-branch)))) - -(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) - "divu $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 9)) - (sequence () - (c-call "check_option_div" pc) - (if (eq rm 0) - (set pc (c-call USI "zdiv_exception" pc)) - (sequence () - (set lo (udiv rn rm)) - (set hi (umod rn rm))))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-divide) - (unit u-branch)))) - - -; Debug functions. -; These instructions become the RI when the debug function option is -; off. - -(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN) - "dret" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3)) - (sequence () - (c-call "check_option_debug" pc) - ; set DBG.DM. - (set dbg (and dbg (inv (sll SI 1 15)))) - (set pc depc)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE) - "dbreak" - (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3)) - (sequence () - (c-call "check_option_debug" pc) - ; set DBG.DPB. - (set dbg (or dbg 1))) - ()) - - -; Leading zero instruction. - -(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2)) - "ldz $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0)) - (sequence () - (c-call "check_option_ldz" pc) - (set rn (c-call SI "do_ldz" rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Absolute difference instruction. - -(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2)) - "abs $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3)) - (sequence () - (c-call "check_option_abs" pc) - (set rn (abs (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Average instruction. - -(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2)) - "ave $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2)) - (sequence () - (c-call "check_option_ave" pc) - (set rn (sra (add (add rn rm) 1) 1))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; MIN/MAX instructions. - -(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "min $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4)) - (sequence () - (c-call "check_option_minmax" pc) - (if (gt rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "max $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5)) - (sequence () - (c-call "check_option_minmax" pc) - (if (lt rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "minu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6)) - (sequence () - (c-call "check_option_minmax" pc) - (if (gtu rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "maxu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7)) - (sequence () - (c-call "check_option_minmax" pc) - (if (ltu rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Clipping instruction. - -(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2)) - "clip $rn,$cimm5" - (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0)) - (sequence ((SI min) (SI max)) - (c-call "check_option_clip" pc) - (set max (sub (sll 1 (sub cimm5 1)) 1)) - (set min (neg (sll 1 (sub cimm5 1)))) - (cond - ((eq cimm5 0) (set rn 0)) - ((gt rn max) (set rn max)) - ((lt rn min) (set rn min)))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2)) - "clipu $rn,$cimm5" - (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1)) - (sequence ((SI max)) - (c-call "check_option_clip" pc) - (set max (sub (sll 1 cimm5) 1)) - (cond - ((eq cimm5 0) (set rn 0)) - ((gt rn max) (set rn max)) - ((lt rn 0) (set rn 0)))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Saturation instructions. - -(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2)) - "sadd $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8)) - (sequence () - (c-call "check_option_sat" pc) - (if (add-oflag rn rm 0) - (if (nflag rn) - ; underflow - (set rn (neg (sll 1 31))) - ; overflow - (set rn (sub (sll 1 31) 1))) - (set rn (add rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) - "ssub $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10)) - (sequence () - (c-call "check_option_sat" pc) - (if (sub-oflag rn rm 0) - (if (nflag rn) - ; underflow - (set rn (neg (sll 1 31))) - ; overflow - (set rn (sub (sll 1 31) 1))) - (set rn (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2)) - "saddu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9)) - (sequence () - (c-call "check_option_sat" pc) - (if (add-cflag rn rm 0) - (set rn (inv 0)) - (set rn (add rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) - "ssubu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11)) - (sequence () - (c-call "check_option_sat" pc) - (if (sub-cflag rn rm 0) - (set rn 0) - (set rn (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; UCI and DSP options are defined in an external file. -; See `mep-sample-ucidsp.cpu' for a sample. - - -; Coprocessor instructions. - -(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "swcp $crn,($rma)" - (+ MAJ_3 crn rma (f-sub4 8)) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcp $crn,($rma)" - (+ MAJ_3 crn rma (f-sub4 9)) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcp $crn64,($rma)" - (+ MAJ_3 crn64 rma (f-sub4 10)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcp" rma crn64 pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcp $crn64,($rma)" - (+ MAJ_3 crn64 rma (f-sub4 11)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE)) - "swcpi $crn,($rma+)" - (+ MAJ_3 crn rma (f-sub4 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (add rma 4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcpi $crn,($rma+)" - (+ MAJ_3 crn rma (f-sub4 1)) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (add rma 4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcpi $crn64,($rma+)" - (+ MAJ_3 crn64 rma (f-sub4 2)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcpi" (index-of rma) crn64 pc) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcpi $crn64,($rma+)" - (+ MAJ_3 crn64 rma (f-sub4 3)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc)) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE)) - "swcp $crn,$sdisp16($rma)" - (+ MAJ_15 crn rma (f-sub4 12) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcp $crn,$sdisp16($rma)" - (+ MAJ_15 crn rma (f-sub4 13) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and (add rma sdisp16) (inv SI 3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcp $crn64,$sdisp16($rma)" - (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call "do_smcp16" rma sdisp16 crn64 pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcp $crn64,$sdisp16($rma)" - (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "sbcpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (add rma (ext SI cdisp10)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lbcpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (add rma (ext SI cdisp10)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "shcpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lhcpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "swcpa $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (add rma (ext SI cdisp10a4)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcpa $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (add rma (ext SI cdisp10a4)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcpa $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcpa $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc)) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN) - "sbcpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN) - "lbcpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN) - "shcpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN) - "lhcpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN) - "swcpm0 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (mod0 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN) - "lwcpm0 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (mod0 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "smcpm0 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcp" rma crn64 pc) - (set rma (mod0 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "lmcpm0 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc)) - (set rma (mod0 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN) - "sbcpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN) - "lbcpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN) - "shcpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN) - "lhcpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN) - "swcpm1 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (mod1 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN) - "lwcpm1 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem SI (and rma (inv SI 3))))) - (set rma (mod1 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "smcpm1 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call "do_smcp" rma crn64 pc) - (c-call VOID "check_write_to_text" rma) - (set rma (mod1 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "lmcpm1 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc)) - (set rma (mod1 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1) - -(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE) - "bcpeq $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (eq (xor cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE) - "bcpne $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (ne (xor cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE) - "bcpat $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (ne (and cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE) - "bcpaf $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (eq (and cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN) - "synccp" - (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1)) - (sequence () - (c-call "check_option_cp" pc) - (unimp "synccp")) - ()) - -(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN) - "jsrv $rm" - (+ MAJ_1 (f-rn 8) rm (f-sub4 15)) - (sequence () - (cg-profile pc rm) - (c-call "check_option_cp" pc) - (core-vliw-switch - - ;; in core operating mode - (sequence () - (set lp (or (add pc 2) 1)) - (set-vliw-aliignment-modified-by-option pc rm) - (set-psw.om 1)) ;; to VLIW operation mode - - ;; in VLIW32 operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set pc (and rm (inv 1))) - (set-psw.om 0)) ;; to core operation mode - - ;; in VLIW64 operating mode - (sequence () - (set lp (or (add pc 8) 1)) - (set pc (and rm (inv 1))) - (set-psw.om 0)))) ;; to core operation mode - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN) - "bsrv $pcrel24a2" - (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2) - (sequence () - (cg-profile pc pcrel24a2) - (c-call "check_option_cp" pc) - (core-vliw-switch - - ;; in core operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set-vliw-aliignment-modified-by-option pc pcrel24a2) - (set-psw.om 1)) ;; to VLIW operation mode - - ;; in VLIW32 operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set pc (and pcrel24a2 (inv 1))) - (set-psw.om 0)) ;; to core operation mode - - ;; in VLIW64 operating mode - (sequence () - (set lp (or (add pc 8) 1)) - (set pc (and pcrel24a2 (inv 1))) - (set-psw.om 0)))) ;; to core operation mode - ((mep (unit u-exec) - (unit u-branch)))) - - -; An instruction for test instrumentation. -; Using a reserved opcode. - -(dnci sim-syscall "simulator system call" () - "--syscall--" - (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0)) - (c-call "do_syscall" pc callnum) - ()) - -(define-pmacro (dnri n major minor) - (dnci (.sym ri- n) "reserved instruction" () - "--reserved--" - (+ major rn rm (f-sub4 minor)) - (set pc (c-call USI "ri_exception" pc)) - ((mep (unit u-exec) - (unit u-branch))))) - -(dnri 0 MAJ_0 6) -(dnri 1 MAJ_1 10) -(dnri 2 MAJ_1 11) -(dnri 3 MAJ_2 5) -(dnri 4 MAJ_2 8) -(dnri 5 MAJ_2 9) -(dnri 6 MAJ_2 10) -(dnri 7 MAJ_2 11) -(dnri 8 MAJ_3 4) -(dnri 9 MAJ_3 5) -(dnri 10 MAJ_3 6) -(dnri 11 MAJ_3 7) -(dnri 12 MAJ_3 12) -(dnri 13 MAJ_3 13) -(dnri 14 MAJ_3 14) -(dnri 15 MAJ_3 15) -(dnri 17 MAJ_7 7) -(dnri 20 MAJ_7 14) -(dnri 21 MAJ_7 15) -(dnri 22 MAJ_12 7) -(dnri 23 MAJ_14 13) -;(dnri 24 MAJ_15 3) -(dnri 26 MAJ_15 8) -; begin core-specific reserved insns -; end core-specific reserved insns - - -; Macro instructions. - -(dnmi nop "nop" - () - "nop" - (emit mov (rn 0) (rm 0))) - -; Emit the 16 bit form of these 32 bit insns when the displacement is zero. -; -(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS) - "sb $rnc,$zero($rma)" - (emit sb rnc rma)) - -(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS) - "sh $rns,$zero($rma)" - (emit sh rns rma)) - -(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS) - "sw $rnl,$zero($rma)" - (emit sw rnl rma)) - -(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS) - "lb $rnc,$zero($rma)" - (emit lb rnc rma)) - -(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS) - "lh $rns,$zero($rma)" - (emit lh rns rma)) - -(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS) - "lw $rnl,$zero($rma)" - (emit lw rnl rma)) - -(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS) - "lbu $rnuc,$zero($rma)" - (emit lbu rnuc rma)) - -(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS) - "lhu $rnus,$zero($rma)" - (emit lhu rnus rma)) - -(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) - "swcp $crn,$zero($rma)" - (emit swcp crn rma)) - -(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) - "lwcp $crn,$zero($rma)" - (emit lwcp crn rma)) - -(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) - "smcp $crn64,$zero($rma)" - (emit smcp crn64 rma)) - -(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) - "lmcp $crn64,$zero($rma)" - (emit lmcp crn64 rma)) diff --git a/cpu/mep-default.cpu b/cpu/mep-default.cpu deleted file mode 100644 index d55b20f..0000000 --- a/cpu/mep-default.cpu +++ /dev/null @@ -1,10 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2001 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -; This file serves as a wrapper to bring in the core description plus -; sample implementations of the UCI and DSP instructions. - -(include "mep-core.cpu") -(include "mep-ext-cop.cpu") diff --git a/cpu/mep-ext-cop.cpu b/cpu/mep-ext-cop.cpu deleted file mode 100644 index e245005..0000000 --- a/cpu/mep-ext-cop.cpu +++ /dev/null @@ -1,8 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2003 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -;; begin-user-isa-includes -(include "mep-ivc2.cpu") -;; end-user-isa-includes diff --git a/cpu/mep-fmax.cpu b/cpu/mep-fmax.cpu deleted file mode 100644 index 5c3c417..0000000 --- a/cpu/mep-fmax.cpu +++ /dev/null @@ -1,323 +0,0 @@ -; Toshiba MeP FMAX Coprocessor description. -*- Scheme -*- -; Copyright (C) 2005 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires only the 32 bit insns in the core. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro fmax-core-isa () (ISA ext_core2)) -(define-pmacro all-fmax-isas () (ISA ext_core2)) -; end-isas - -;****************************************************************************** -; ifields -;------------------------------------------------------------------------------ -; opcodes -(dnf f-fmax-0-4 "opcode" (all-fmax-isas) 0 4) -(dnf f-fmax-4-4 "opcode" (all-fmax-isas) 4 4) -(dnf f-fmax-8-4 "opcode" (all-fmax-isas) 8 4) -(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4) -(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4) -(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4) -(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4) -(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1) -(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1) -(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1) -(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1) - -;------------------------------------------------------------------------------ -; FR registers -(define-multi-ifield - (name f-fmax-frd) - (comment "FRd register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-28-1 f-fmax-4-4) - (insert (sequence () - (set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf)) - (set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4)))) - (extract (set (ifield f-fmax-frd) - (or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4)))) -) -(define-multi-ifield - (name f-fmax-frn) - (comment "FRn register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-29-1 f-fmax-20-4) - (insert (sequence () - (set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf)) - (set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4)))) - (extract (set (ifield f-fmax-frn) - (or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4)))) -) -(define-multi-ifield - (name f-fmax-frm) - (comment "FRm register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-30-1 f-fmax-24-4) - (insert (sequence () - (set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf)) - (set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4)))) - (extract (set (ifield f-fmax-frm) - (or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4)))) -) - -;------------------------------------------------------------------------------ -; Core General registers -(dnf f-fmax-rm "opcode" (all-fmax-isas) 8 4) - -;------------------------------------------------------------------------------ -; Condition opcodes enum -(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4 - ("f" "u" "e" "ue" "l" "ul" "le" "ule" - "fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei") -) - -;****************************************************************************** -; Hardware -;------------------------------------------------------------------------------ -; FR registers - -; Given a coprocessor register number N, expand to a -; name/index pair: ($frN N) -(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n)) -(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n)) - -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-fmax) - (comment "Floating point registers") - (attrs all-fmax-isas VIRTUAL IS_FLOAT) - (type register SF (32)) - (indices keyword "$" - (.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32))) - (.unsplice (.map -fmax-cr-reg-pair (.iota 32)))) - ) - (get (index) (c-call SF "fmax_fr_get_handler" index)) - (set (index newval) (c-call VOID "fmax_fr_set_handler" index newval)) -) - -;------------------------------------------------------------------------------ -; Control registers -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-fmax) - (comment "Coprocessor Identifier and Revision Register") - (attrs all-fmax-isas VIRTUAL) - (type register USI (16)) - (indices keyword "$" ( - ("cirr" 0) ("fcr0" 0) ("ccr0" 0) - ("cbcr" 1) ("fcr1" 1) ("ccr1" 1) - ("cerr" 15) ("fcr15" 15) ("ccr15" 15) - ) - ) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) -) - -;------------------------------------------------------------------------------ -; Misc -(define-hardware - (name h-fmax-compare-i-p) - (comment "flag") - (attrs all-fmax-isas) - (type register USI) -) - -;****************************************************************************** -; Operands -;------------------------------------------------------------------------------ -; FR Registers -(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ()) - -(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ()) - -;------------------------------------------------------------------------------ -; Control registers -(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ()) - -(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0) -(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1) -(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15) - -;------------------------------------------------------------------------------ -; Core General Registers -(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm) - -;------------------------------------------------------------------------------ -; misc -(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil) - -;****************************************************************************** -; Instructions -;------------------------------------------------------------------------------ -; Binary Arithmetic -(define-pmacro (fmax-binary-arith op opc sem) - (dni op - (.str op " FRd,FRn,FRm") - (all-fmax-isas MAY_TRAP) - (.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}") - (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0) - fmax-FRn fmax-FRm (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm))) -(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm))) -(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm))) -(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm))) - -;------------------------------------------------------------------------------ -; Unary Arithmetic -(define-pmacro (fmax-unary-arith op opc sem) - (dni op - (.str op " FRd,FRn") - (all-fmax-isas MAY_TRAP) - (.str op " ${fmax-FRd},${fmax-FRn}") - (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) - (f-fmax-16-4 0) fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn))) -(fmax-unary-arith fabss #x5 (set fmax-FRd (abs fmax-FRn))) -(fmax-unary-arith fnegs #x7 (set fmax-FRd (neg fmax-FRn))) -(fmax-unary-arith fmovs #x6 (set fmax-FRd fmax-FRn)) - -;------------------------------------------------------------------------------ -; Conversions -(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem) - (dni op - (.str op " FRd,FRn") - (all-fmax-isas MAY_TRAP) - (.str op " ${" opnd1 "},${" opnd2 "}") - (+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7) - (f-fmax-16-4 opc2) opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn))) -(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn))) -(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn))) -(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn))) -(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn))) -(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int))) - -;------------------------------------------------------------------------------ -; Comparisons -; -; Comparison with no exceptions -(define-pmacro (fmax-f-sem x y) (andif (gt x y) (lt x y))) ; do this to get exception detection -(define-pmacro (fmax-u-sem x y) (not (orif (lt x y) (orif (eq x y) (gt x y))))) -(define-pmacro (fmax-e-sem x y) (eq x y)) -(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y)))) -(define-pmacro (fmax-l-sem x y) (lt x y)) -(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y)))) -(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y))) -(define-pmacro (fmax-ule-sem x y) (not (gt x y))) - -(define-pmacro (fmax-comp cond suffix exceptions) - (dni (.sym fcmp cond suffix s) - (.str "fcmp" cond suffix "s FRn,FRm") - ;; Even though the instruction doesn't really trap if EXCEPTIONS - ;; is zero, we don't want gcc to put it in a repeat or erepeat - ;; block because of the hazards between fcmp instructions and - ;; anything that reads CBCR. - (all-fmax-isas MAY_TRAP) - (.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}") - (+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7) - (f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0)) - (sequence () - (set fmax-Compare-i-p exceptions) - (set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm)) - (set fmax-Compare-i-p 0) - ) - () - ) -) - -; Comparison with no exceptions -(fmax-comp f "" 0) -(fmax-comp u "" 0) -(fmax-comp e "" 0) -(fmax-comp ue "" 0) -(fmax-comp l "" 0) -(fmax-comp ul "" 0) -(fmax-comp le "" 0) -(fmax-comp ule "" 0) - -; Comparison with exceptions -(fmax-comp f i 1) -(fmax-comp u i 1) -(fmax-comp e i 1) -(fmax-comp ue i 1) -(fmax-comp l i 1) -(fmax-comp ul i 1) -(fmax-comp le i 1) -(fmax-comp ule i 1) - -;------------------------------------------------------------------------------ -; Move to/from core registers -(dni cmov-frn-rm - "cmov FRn,Rm" - (all-fmax-isas (INTRINSIC "cmov1")) - "cmov ${fmax-FRd-int},${fmax-Rm}" - (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - (set fmax-FRd-int fmax-Rm) - () -) -(dni cmov-rm-frn - "cmov Rm,FRn" - (all-fmax-isas (INTRINSIC "cmov2")) - "cmov ${fmax-Rm},${fmax-FRd-int}" - (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1)) - (set fmax-Rm fmax-FRd-int) - () -) -(dni cmovc-ccrn-rm - "cmovc CCRn,Rm" - (all-fmax-isas (INTRINSIC "cmovc1")) - "cmovc ${fmax-CCRn},${fmax-Rm}" - (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0)) - (set fmax-CCRn fmax-Rm) - () -) -(dni cmovc-rm-ccrn - "cmovc Rm,CCRn" - (all-fmax-isas (INTRINSIC "cmovc2")) - "cmovc ${fmax-Rm},${fmax-CCRn}" - (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1)) - (set fmax-Rm fmax-CCRn) - () -) diff --git a/cpu/mep-h1.cpu b/cpu/mep-h1.cpu deleted file mode 100644 index 2c3b1c0..0000000 --- a/cpu/mep-h1.cpu +++ /dev/null @@ -1,28 +0,0 @@ -; Insns introduced for the MeP-h1 core -; -(dnci stcb_r "store in control bus space" (VOLATILE (MACH h1)) - "stcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 12)) - (c-call VOID "do_stcb" rn (and rma #xffff)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb_r "load from control bus space" (VOLATILE (MACH h1) (LATENCY 3)) - "ldcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 13)) - (set rn (c-call SI "do_ldcb" (and rma #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - -(dnci pref "cache prefetch" ((MACH h1) VOLATILE) - "pref $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 5)) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 rma pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) diff --git a/cpu/mep-ivc2.cpu b/cpu/mep-ivc2.cpu deleted file mode 100644 index 340610b..0000000 --- a/cpu/mep-ivc2.cpu +++ /dev/null @@ -1,9761 +0,0 @@ -; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*- -; Copyright (C) 2009 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. -; - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; IVC2 uses the isas as follows: -; C3 32 -; P0S 16 -; P0 48 -; P1 64 -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro ivc2-core-isa () (ISA ext_core1)) -(define-pmacro ivc2-16-isa () (ISA ext_cop1_16)) -(define-pmacro ivc2-32-isa () (ISA ext_cop1_32)) -(define-pmacro ivc2-48-isa () (ISA ext_cop1_48)) -(define-pmacro ivc2-64-isa () (ISA ext_cop1_64)) -(define-pmacro all-ivc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-p0s-isa () (ISA ext_cop1_16)) -(define-pmacro ivc2-p0-isa () (ISA ext_cop1_48)) -(define-pmacro ivc2-p0s-p0-isa () (ISA ext_cop1_16,ext_cop1_48)) -(define-pmacro ivc2-p1-isa () (ISA ext_cop1_64)) -(define-pmacro ivc2-p0s-p1-isa () (ISA ext_cop1_16,ext_cop1_64)) -(define-pmacro ivc2-p0-p1-isa () (ISA ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-p0s-p0-p1-isa () (ISA ext_cop1_16,ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-c3-isa () (ISA ext_cop1_32)) -; end-isas - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-ivc2) - (comment "64-bit coprocessor registers for ivc2 coprocessor") - (attrs VIRTUAL all-mep-core-isas (CDATA CP_DATA_BUS_INT)) - (type register DI (64)) - (set (index newval) (c-call VOID "h_cr64_set" index newval)) - (get (index) (c-call DI "h_cr64_get" index)) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) - -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-ivc2) - (comment "Coprocessor control registers for ivc2 coprocessor") - (attrs VIRTUAL all-mep-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - - ($csar0 0) - ($cc 1) - ($cofr0 4) - ($cofr1 5) - ($cofa0 6) - ($cofa1 7) - - ($csar1 15) - - ($acc0_0 16) - ($acc0_1 17) - ($acc0_2 18) - ($acc0_3 19) - ($acc0_4 20) - ($acc0_5 21) - ($acc0_6 22) - ($acc0_7 23) - - ($acc1_0 24) - ($acc1_1 25) - ($acc1_2 26) - ($acc1_3 27) - ($acc1_4 28) - ($acc1_5 29) - ($acc1_6 30) - ($acc1_7 31) - (.unsplice (.map -ccr-reg-pair (.iota 32))) - ) - ) -) - -(define-attr - (type bitset) - (for insn) - (name SLOTS) - (comment "slots for which this opcode is valid - c3, p0s, p0, p1") - (values CORE C3 P0S P0 P1) - (default CORE) - ) - -;----------------------------------------------------------------------------- -; macros for standard opcodes for each slot type - -; C3 -(dnf f-ivc2-2u4 "sub opcode field" (all-mep-isas) 4 2) -(dnf f-ivc2-3u4 "sub opcode field" (all-mep-isas) 4 3) -(dnf f-ivc2-8u4 "sub opcode field" (all-mep-isas) 4 8) -(df f-ivc2-8s4 "sub opcode field" (all-mep-isas) 4 8 INT #f #f) -(dnf f-ivc2-1u6 "sub opcode field" (all-mep-isas) 6 1) -(dnf f-ivc2-2u6 "sub opcode field" (all-mep-isas) 6 2) -(dnf f-ivc2-3u6 "sub opcode field" (all-mep-isas) 6 3) -(dnf f-ivc2-6u6 "sub opcode field" (all-mep-isas) 6 6) -(dnf f-ivc2-5u7 "sub opcode field" (all-mep-isas) 7 5) -(dnf f-ivc2-4u8 "sub opcode field" (all-mep-isas) 8 4) -(dnf f-ivc2-3u9 "sub opcode field" (all-mep-isas) 9 3) -(dnf f-ivc2-5u16 "sub opcode field" (all-mep-isas) 16 5) -(dnf f-ivc2-5u21 "sub opcode field" (all-mep-isas) 21 5) -(dnf f-ivc2-5u26 "sub opcode field" (all-mep-isas) 26 5) -(dnf f-ivc2-1u31 "sub opcode field" (all-mep-isas) 31 1) - -(dnf f-ivc2-4u16 "sub opcode field" (all-mep-isas) 16 4) -(dnf f-ivc2-4u20 "sub opcode field" (all-mep-isas) 20 4) -(dnf f-ivc2-4u24 "sub opcode field" (all-mep-isas) 24 4) -(dnf f-ivc2-4u28 "sub opcode field" (all-mep-isas) 28 4) - -; P0S/P0/P1 -(dnf f-ivc2-2u0 "sub opcode field" (all-mep-isas) 0 2) -(dnf f-ivc2-3u0 "sub opcode field" (all-mep-isas) 0 3) -(dnf f-ivc2-4u0 "sub opcode field" (all-mep-isas) 0 4) -(dnf f-ivc2-5u0 "sub opcode field" (all-mep-isas) 0 5) -(dnf f-ivc2-8u0 "sub opcode field" (all-mep-isas) 0 8) -(df f-ivc2-8s0 "sub opcode field" (all-mep-isas) 0 8 INT #f #f) -(dnf f-ivc2-6u2 "sub opcode field" (all-mep-isas) 2 6) -(dnf f-ivc2-5u3 "sub opcode field" (all-mep-isas) 3 5) -(dnf f-ivc2-4u4 "sub opcode field" (all-mep-isas) 4 4) -(dnf f-ivc2-3u5 "sub opcode field" (all-mep-isas) 5 3) -(dnf f-ivc2-5u8 "sub opcode field" (all-mep-isas) 8 5) -(dnf f-ivc2-4u10 "sub opcode field" (all-mep-isas) 10 4) -(dnf f-ivc2-3u12 "sub opcode field" (all-mep-isas) 12 3) -(dnf f-ivc2-5u13 "sub opcode field" (all-mep-isas) 13 5) -(dnf f-ivc2-2u18 "sub opcode field" (all-mep-isas) 18 2) -(dnf f-ivc2-5u18 "sub opcode field" (all-mep-isas) 18 5) -(dnf f-ivc2-8u20 "sub opcode field" (all-mep-isas) 20 8) -(df f-ivc2-8s20 "sub opcode field" (all-mep-isas) 20 8 INT #f #f) -(dnf f-ivc2-5u23 "sub opcode field" (all-mep-isas) 23 5) -(dnf f-ivc2-2u23 "sub opcode field" (all-mep-isas) 23 2) -(dnf f-ivc2-3u25 "sub opcode field" (all-mep-isas) 25 3) - -(dnmf f-ivc2-imm16p0 "16-bit immediate in P0/P1" (all-mep-isas) UINT - (f-ivc2-8u0 f-ivc2-8u20) - (sequence () ; insert - (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-imm16p0) 8) #xff)) - (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-imm16p0) #xff)) - ) - (sequence () ; extract - (set (ifield f-ivc2-imm16p0) (or (ifield f-ivc2-8u20) - (sll (ifield f-ivc2-8u0) 8))) - ) - ) - -(dnmf f-ivc2-simm16p0 "16-bit immediate in P0/P1" (all-mep-isas) INT - (f-ivc2-8u0 f-ivc2-8u20) - (sequence () ; insert - (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-simm16p0) 8) #xff)) - (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-simm16p0) #xff)) - ) - (sequence () ; extract - (set (ifield f-ivc2-simm16p0) (or (ifield f-ivc2-8u20) - (sll (ifield f-ivc2-8u0) 8))) - ) - ) - -(dnop ivc2_csar0 "ivc2_csar0" (all-ivc2-isas) h-ccr-ivc2 0) -(dnop ivc2_cc "ivc2_cc" (all-ivc2-isas) h-ccr-ivc2 1) -(dnop ivc2_cofr0 "ivc2_cofr0" (all-ivc2-isas) h-ccr-ivc2 4) -(dnop ivc2_cofr1 "ivc2_cofr1" (all-ivc2-isas) h-ccr-ivc2 5) -(dnop ivc2_cofa0 "ivc2_cofa0" (all-ivc2-isas) h-ccr-ivc2 6) -(dnop ivc2_cofa1 "ivc2_cofa1" (all-ivc2-isas) h-ccr-ivc2 7) - -(dnop ivc2_csar1 "ivc2_csar1" (all-ivc2-isas) h-ccr-ivc2 15) - -(dnop ivc2_acc0_0 "acc0_0" (all-ivc2-isas) h-ccr-ivc2 16) -(dnop ivc2_acc0_1 "acc0_1" (all-ivc2-isas) h-ccr-ivc2 17) -(dnop ivc2_acc0_2 "acc0_2" (all-ivc2-isas) h-ccr-ivc2 18) -(dnop ivc2_acc0_3 "acc0_3" (all-ivc2-isas) h-ccr-ivc2 19) -(dnop ivc2_acc0_4 "acc0_4" (all-ivc2-isas) h-ccr-ivc2 20) -(dnop ivc2_acc0_5 "acc0_5" (all-ivc2-isas) h-ccr-ivc2 21) -(dnop ivc2_acc0_6 "acc0_6" (all-ivc2-isas) h-ccr-ivc2 22) -(dnop ivc2_acc0_7 "acc0_7" (all-ivc2-isas) h-ccr-ivc2 23) - -(dnop ivc2_acc1_0 "acc1_0" (all-ivc2-isas) h-ccr-ivc2 24) -(dnop ivc2_acc1_1 "acc1_1" (all-ivc2-isas) h-ccr-ivc2 25) -(dnop ivc2_acc1_2 "acc1_2" (all-ivc2-isas) h-ccr-ivc2 26) -(dnop ivc2_acc1_3 "acc1_3" (all-ivc2-isas) h-ccr-ivc2 27) -(dnop ivc2_acc1_4 "acc1_4" (all-ivc2-isas) h-ccr-ivc2 28) -(dnop ivc2_acc1_5 "acc1_5" (all-ivc2-isas) h-ccr-ivc2 29) -(dnop ivc2_acc1_6 "acc1_6" (all-ivc2-isas) h-ccr-ivc2 30) -(dnop ivc2_acc1_7 "acc1_7" (all-ivc2-isas) h-ccr-ivc2 31) - -(dnop croc "$CRo C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u7) -(dnop crqc "$CRq C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u21) -(dnop crpc "$CRp C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u26) - -(dnop ivc-x-6-1 "filler" (all-mep-isas) h-uint f-ivc2-1u6) -(dnop ivc-x-6-2 "filler" (all-mep-isas) h-uint f-ivc2-2u6) -(dnop ivc-x-6-3 "filler" (all-mep-isas) h-uint f-ivc2-3u6) - - -(dnop imm3p4 "Imm3p4" (all-mep-isas) h-uint f-ivc2-3u4) -(dnop imm3p9 "Imm3p9" (all-mep-isas) h-uint f-ivc2-3u9) -(dnop imm4p8 "Imm4p8" (all-mep-isas) h-uint f-ivc2-4u8) -(dnop imm5p7 "Imm5p7" (all-mep-isas) h-uint f-ivc2-5u7) -(dnop imm6p6 "Imm6p6" (all-mep-isas) h-uint f-ivc2-6u6) -(dnop imm8p4 "Imm8p4" (all-mep-isas) h-uint f-ivc2-8u4) -(dnop simm8p4 "sImm8p4" (all-mep-isas) h-sint f-ivc2-8s4) - -(dnop imm3p5 "Imm3p5" (all-mep-isas) h-uint f-ivc2-3u5) -(dnop imm3p12 "Imm3p12" (all-mep-isas) h-uint f-ivc2-3u12) -(dnop imm4p4 "Imm4p4" (all-mep-isas) h-uint f-ivc2-4u4) -(dnop imm4p10 "Imm4p10" (all-mep-isas) h-uint f-ivc2-4u10) -(dnop imm5p8 "Imm5p8" (all-mep-isas) h-uint f-ivc2-5u8) -(dnop imm5p3 "Imm5p3" (all-mep-isas) h-uint f-ivc2-5u3) -(dnop imm6p2 "Imm6p2" (all-mep-isas) h-uint f-ivc2-6u2) -(dnop imm5p23 "Imm5p23" (all-mep-isas) h-uint f-ivc2-5u23) -(dnop imm3p25 "Imm3p25" (all-mep-isas) h-uint f-ivc2-3u25) -(dnop imm8p0 "Imm8p0" (all-mep-isas) h-uint f-ivc2-8u0) -(dnop simm8p0 "sImm8p0" (all-mep-isas) h-sint f-ivc2-8s0) -(dnop simm8p20 "sImm8p20" (all-mep-isas) h-sint f-ivc2-8s20) -(dnop imm8p20 "Imm8p20" (all-mep-isas) h-uint f-ivc2-8u20) - -(dnop crop "$CRo Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u23) -(dnop crqp "$CRq Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u13) -(dnop crpp "$CRp Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u18) - -(dnop ivc-x-0-2 "filler" (all-mep-isas) h-uint f-ivc2-2u0) -(dnop ivc-x-0-3 "filler" (all-mep-isas) h-uint f-ivc2-3u0) -(dnop ivc-x-0-4 "filler" (all-mep-isas) h-uint f-ivc2-4u0) -(dnop ivc-x-0-5 "filler" (all-mep-isas) h-uint f-ivc2-5u0) - -(dpop imm16p0 "Imm16p0" (all-mep-isas) h-uint f-ivc2-imm16p0 "unsigned16_range") -(dpop simm16p0 "sImm16p0" (all-mep-isas) h-sint f-ivc2-simm16p0 "signed16_range") - - -(df f-ivc2-ccrn-c3hi "ccrn hi 2u28" (all-mep-isas) 28 2 UINT #f #f) -(df f-ivc2-ccrn-c3lo "ccrn lo 4u4" (all-mep-isas) 4 4 UINT #f #f) - -(df f-ivc2-crn "ivc2 crn" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-crm "ivc2 crm" (all-mep-isas) 4 4 UINT #f #f) -(df f-ivc2-ccrn-h1 "ccrx hi 1u20" (all-mep-isas) 20 1 UINT #f #f) -(df f-ivc2-ccrn-h2 "ccrx hi 2u20" (all-mep-isas) 20 2 UINT #f #f) -(df f-ivc2-ccrn-lo "ccrx lo 4u0" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-cmov1 "ivc2 cmov op1" (all-mep-isas) 8 12 UINT #f #f) -(df f-ivc2-cmov2 "ivc2 cmov op2" (all-mep-isas) 22 6 UINT #f #f) -(df f-ivc2-cmov3 "ivc2 cmov op2" (all-mep-isas) 28 4 UINT #f #f) - -(define-multi-ifield - (name f-ivc2-ccrn-c3) - (comment "Coprocessor register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-c3hi f-ivc2-ccrn-c3lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-c3hi) (and (srl (ifield f-ivc2-ccrn-c3) 4) #x3)) - (set (ifield f-ivc2-ccrn-c3lo) (and (ifield f-ivc2-ccrn-c3) #xf)))) - (extract (set (ifield f-ivc2-ccrn-c3) - (or (sll (ifield f-ivc2-ccrn-c3hi) 4) - (ifield f-ivc2-ccrn-c3lo)))) - ) - -(define-multi-ifield - (name f-ivc2-ccrn) - (comment "Coprocessor control register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h2 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h2) (and (srl (ifield f-ivc2-ccrn) 4) #x3)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-ccrn) #xf)))) - (extract (set (ifield f-ivc2-ccrn) - (or (sll (ifield f-ivc2-ccrn-h2) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(define-multi-ifield - (name f-ivc2-crnx) - (comment "Coprocessor register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h1 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h1) (and (srl (ifield f-ivc2-crnx) 4) #x1)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-crnx) #xf)))) - (extract (set (ifield f-ivc2-crnx) - (or (sll (ifield f-ivc2-ccrn-h1) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(dnop ivc2rm "reg Rm" (all-mep-isas) h-gpr f-ivc2-crm) -(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-crnx) -(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn) -(dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn-c3) - -; [--][--] [--][--] [--][--] [--] -; 0----+-- --1----+ ----2--- -+-- -; 01234567 89012345 67890123 4567 - - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmov-crn-rm - "cmov CRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov1")) - "cmov $crnx64,$rm" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0)) - (set crnx64 (or (zext DI rm) (and DI crnx64 #xffffffff00000000))) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmov-rn-crm - "cmov Rm,CRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov2")) - "cmov $rm,$crnx64" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1)) - (set rm crnx64) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmovc-ccrn-rm - "cmovc CCRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc1")) - "cmovc $ivc2c3ccrn,$rm" - (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 0)) - (set ivc2c3ccrn rm) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmovc-rn-ccrm - "cmovc Rm,CCRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc2")) - "cmovc $rm,$ivc2c3ccrn" - (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 1)) - (set rm ivc2c3ccrn) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmovh-crn-rm - "cmovh CRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh1")) - "cmovh $crnx64,$rm" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0)) - (set crnx64 (or (sll (zext DI rm) 32) (and DI crnx64 #xffffffff))) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmovh-rn-crm - "cmovh Rm,CRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh2")) - "cmovh $rm,$crnx64" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1)) - (set rm (srl crnx64 32)) - () -) - -; nnnnmmmm 11110000 0000N000 0000 cmov =crn,rm -(dni cmov-crn-rm-p0 - "cmov CRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov1")) - "cmov $ivc2crn,$ivc2rm" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0)) - (set ivc2crn ivc2rm) - () -) - -; nnnnmmmm 11110000 0000N001 0000 cmov =rm,crn -(dni cmov-rn-crm-p0 - "cmov Rm,CRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov2")) - "cmov $ivc2rm,$ivc2crn" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0)) - (set ivc2rm ivc2crn) - () -) - -; nnnnmmmm 11110000 0000NN10 0000 cmovc =ccrn,rm -(dni cmovc-ccrn-rm-p0 - "cmovc CCRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc1")) - "cmovc $ivc2ccrn,$ivc2rm" - (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x20) (f-ivc2-cmov3 0)) - (set ivc2ccrn ivc2rm) - () -) - -; nnnnmmmm 11110000 0000NN11 0000 cmovc =rm,ccrn -(dni cmovc-rn-ccrm-p0 - "cmovc Rm,CCRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc2")) - "cmovc $ivc2rm,$ivc2ccrn" - (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x30) (f-ivc2-cmov3 0)) - (set ivc2rm ivc2ccrn) - () -) - -; nnnnmmmm 11110001 0000N000 0000 cmovh =crn,rm -(dni cmovh-crn-rm-p0 - "cmovh CRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh1")) - "cmovh $ivc2crn,$ivc2rm" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0)) - (set ivc2crn (or (sll (zext DI ivc2rm) 32) (and DI ivc2crn #xffffffff))) - () -) - -; nnnnmmmm 11110001 0000N001 0000 cmovh =rm,crn -(dni cmovh-rn-crm-p0 - "cmovh Rm,CRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh2")) - "cmovh $ivc2rm,$ivc2crn" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0)) - (set ivc2rm (srl ivc2crn 32)) - () -) - - -; 1111 000 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.b =croc,crqc,crpc (c3_1) -(dni cpadd3_b_C3 "cpadd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpadd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.h =croc,crqc,crpc (c3_1) -(dni cpadd3_h_C3 "cpadd3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpadd3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_h" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.w =croc,crqc,crpc (c3_1) -(dni cpadd3_w_C3 "cpadd3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpadd3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_w" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00000 qqqqq ppppp 0 cdadd3 =croc,crqc,crpc (c3_1) -(dni cdadd3_C3 "cdadd3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdadd3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdadd3" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.b =croc,crqc,crpc (c3_1) -(dni cpsub3_b_C3 "cpsub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.h =croc,crqc,crpc (c3_1) -(dni cpsub3_h_C3 "cpsub3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsub3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_h" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.w =croc,crqc,crpc (c3_1) -(dni cpsub3_w_C3 "cpsub3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsub3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_w" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00000 qqqqq ppppp 0 cdsub3 =croc,crqc,crpc (c3_1) -(dni cdsub3_C3 "cdsub3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsub3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsub3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00001 qqqqq ppppp 0 cpand3 =croc,crqc,crpc (c3_1) -(dni cpand3_C3 "cpand3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST)) - "cpand3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpand3" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00001 qqqqq ppppp 0 cpor3 =croc,crqc,crpc (c3_1) -(dni cpor3_C3 "cpor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST)) - "cpor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpor3" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00001 qqqqq ppppp 0 cpnor3 =croc,crqc,crpc (c3_1) -(dni cpnor3_C3 "cpnor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST)) - "cpnor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnor3" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00001 qqqqq ppppp 0 cpxor3 =croc,crqc,crpc (c3_1) -(dni cpxor3_C3 "cpxor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST)) - "cpxor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpxor3" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00001 qqqqq ppppp 0 cpsel =croc,crqc,crpc (c3_1) -(dni cpsel_C3 "cpsel $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpsel $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsel" pc crqc crpc)) ) - () - ) - -; 1111 iii ooooo 0111 11101 qqqqq ppppp 0 cpfsftbi =croc,crqc,crpc,imm3p4 (c3_1) -(dni cpfsftbi_C3 "cpfsftbi $croc,$crqc,$crpc,imm3p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpfsftbi $croc,$crqc,$crpc,$imm3p4" - (+ MAJ_15 imm3p4 croc (f-sub4 7) - (f-ivc2-5u16 #x1d) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbi" pc crqc crpc imm3p4)) ) - () - ) - -; 1111 110 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs0 =croc,crqc,crpc (c3_1) -(dni cpfsftbs0_C3 "cpfsftbs0 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs0 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbs0" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs1 =croc,crqc,crpc (c3_1) -(dni cpfsftbs1_C3 "cpfsftbs1 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs1 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbs1" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.b =croc,crqc,crpc (c3_1) -(dni cpunpacku_b_C3 "cpunpacku.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpunpacku.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.h =croc,crqc,crpc (c3_1) -(dni cpunpacku_h_C3 "cpunpacku.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpunpacku.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_h" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.w =croc,crqc,crpc (c3_1) -(dni cpunpacku_w_C3 "cpunpacku.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST)) - "cpunpacku.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.b =croc,crqc,crpc (c3_1) -(dni cpunpackl_b_C3 "cpunpackl.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpunpackl.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.h =croc,crqc,crpc (c3_1) -(dni cpunpackl_h_C3 "cpunpackl.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpunpackl.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_h" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.w =croc,crqc,crpc (c3_1) -(dni cpunpackl_w_C3 "cpunpackl.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST)) - "cpunpackl.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00011 qqqqq ppppp 0 cppacku.b =croc,crqc,crpc (c3_1) -(dni cppacku_b_C3 "cppacku.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cppacku.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacku_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00011 qqqqq ppppp 0 cppack.b =croc,crqc,crpc (c3_1) -(dni cppack_b_C3 "cppack.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST)) - "cppack.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppack_b" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00011 qqqqq ppppp 0 cppack.h =croc,crqc,crpc (c3_1) -(dni cppack_h_C3 "cppack.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST)) - "cppack.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppack_h" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.b =croc,crqc,crpc (c3_1) -(dni cpsrl3_b_C3 "cpsrl3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrl3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.b =croc,crqc,crpc (c3_1) -(dni cpssrl3_b_C3 "cpssrl3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssrl3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.h =croc,crqc,crpc (c3_1) -(dni cpsrl3_h_C3 "cpsrl3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrl3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.h =croc,crqc,crpc (c3_1) -(dni cpssrl3_h_C3 "cpssrl3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssrl3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.w =croc,crqc,crpc (c3_1) -(dni cpsrl3_w_C3 "cpsrl3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrl3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.w =croc,crqc,crpc (c3_1) -(dni cpssrl3_w_C3 "cpssrl3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssrl3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00100 qqqqq ppppp 0 cdsrl3 =croc,crqc,crpc (c3_1) -(dni cdsrl3_C3 "cdsrl3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrl3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsrl3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.b =croc,crqc,crpc (c3_1) -(dni cpsra3_b_C3 "cpsra3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsra3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.b =croc,crqc,crpc (c3_1) -(dni cpssra3_b_C3 "cpssra3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssra3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.h =croc,crqc,crpc (c3_1) -(dni cpsra3_h_C3 "cpsra3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsra3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.h =croc,crqc,crpc (c3_1) -(dni cpssra3_h_C3 "cpssra3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssra3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.w =croc,crqc,crpc (c3_1) -(dni cpsra3_w_C3 "cpsra3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsra3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.w =croc,crqc,crpc (c3_1) -(dni cpssra3_w_C3 "cpssra3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssra3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00101 qqqqq ppppp 0 cdsra3 =croc,crqc,crpc (c3_1) -(dni cdsra3_C3 "cdsra3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsra3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsra3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.b =croc,crqc,crpc (c3_1) -(dni cpsll3_b_C3 "cpsll3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsll3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.b =croc,crqc,crpc (c3_1) -(dni cpssll3_b_C3 "cpssll3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssll3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.h =croc,crqc,crpc (c3_1) -(dni cpsll3_h_C3 "cpsll3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsll3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.h =croc,crqc,crpc (c3_1) -(dni cpssll3_h_C3 "cpssll3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssll3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.w =croc,crqc,crpc (c3_1) -(dni cpsll3_w_C3 "cpsll3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsll3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.w =croc,crqc,crpc (c3_1) -(dni cpssll3_w_C3 "cpssll3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssll3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00110 qqqqq ppppp 0 cdsll3 =croc,crqc,crpc (c3_1) -(dni cdsll3_C3 "cdsll3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsll3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsll3" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.h =croc,crqc,crpc (c3_1) -(dni cpsla3_h_C3 "cpsla3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsla3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsla3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.w =croc,crqc,crpc (c3_1) -(dni cpsla3_w_C3 "cpsla3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsla3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsla3_w" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.h =croc,crqc,crpc (c3_1) -(dni cpsadd3_h_C3 "cpsadd3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsadd3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsadd3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.w =croc,crqc,crpc (c3_1) -(dni cpsadd3_w_C3 "cpsadd3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsadd3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsadd3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.h =croc,crqc,crpc (c3_1) -(dni cpssub3_h_C3 "cpssub3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpssub3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set croc (c-call DI "ivc2_cpssub3_h" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.w =croc,crqc,crpc (c3_1) -(dni cpssub3_w_C3 "cpssub3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpssub3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set croc (c-call DI "ivc2_cpssub3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01001 qqqqq ppppp 0 cpextuaddu3.b =croc,crqc,crpc (c3_1) -(dni cpextuaddu3_b_C3 "cpextuaddu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuaddu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuaddu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01001 qqqqq ppppp 0 cpextuadd3.b =croc,crqc,crpc (c3_1) -(dni cpextuadd3_b_C3 "cpextuadd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuadd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuadd3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01001 qqqqq ppppp 0 cpextladdu3.b =croc,crqc,crpc (c3_1) -(dni cpextladdu3_b_C3 "cpextladdu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladdu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextladdu3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01001 qqqqq ppppp 0 cpextladd3.b =croc,crqc,crpc (c3_1) -(dni cpextladd3_b_C3 "cpextladd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextladd3_b" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01001 qqqqq ppppp 0 cpextusubu3.b =croc,crqc,crpc (c3_1) -(dni cpextusubu3_b_C3 "cpextusubu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusubu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextusubu3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01001 qqqqq ppppp 0 cpextusub3.b =croc,crqc,crpc (c3_1) -(dni cpextusub3_b_C3 "cpextusub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextusub3_b" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01001 qqqqq ppppp 0 cpextlsubu3.b =croc,crqc,crpc (c3_1) -(dni cpextlsubu3_b_C3 "cpextlsubu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsubu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlsubu3_b" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01001 qqqqq ppppp 0 cpextlsub3.b =croc,crqc,crpc (c3_1) -(dni cpextlsub3_b_C3 "cpextlsub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlsub3_b" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01010 qqqqq ppppp 0 cpaveu3.b =croc,crqc,crpc (c3_1) -(dni cpaveu3_b_C3 "cpaveu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaveu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaveu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01010 qqqqq ppppp 0 cpave3.b =croc,crqc,crpc (c3_1) -(dni cpave3_b_C3 "cpave3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpave3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01010 qqqqq ppppp 0 cpave3.h =croc,crqc,crpc (c3_1) -(dni cpave3_h_C3 "cpave3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpave3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01010 qqqqq ppppp 0 cpave3.w =croc,crqc,crpc (c3_1) -(dni cpave3_w_C3 "cpave3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpave3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01010 qqqqq ppppp 0 cpaddsru3.b =croc,crqc,crpc (c3_1) -(dni cpaddsru3_b_C3 "cpaddsru3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsru3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsru3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.b =croc,crqc,crpc (c3_1) -(dni cpaddsr3_b_C3 "cpaddsr3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsr3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_b" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.h =croc,crqc,crpc (c3_1) -(dni cpaddsr3_h_C3 "cpaddsr3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpaddsr3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_h" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.w =croc,crqc,crpc (c3_1) -(dni cpaddsr3_w_C3 "cpaddsr3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpaddsr3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01011 qqqqq ppppp 0 cpabsu3.b =croc,crqc,crpc (c3_1) -(dni cpabsu3_b_C3 "cpabsu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.b =croc,crqc,crpc (c3_1) -(dni cpabs3_b_C3 "cpabs3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabs3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabs3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.h =croc,crqc,crpc (c3_1) -(dni cpabs3_h_C3 "cpabs3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabs3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabs3_h" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.b =croc,crqc,crpc (c3_1) -(dni cpmaxu3_b_C3 "cpmaxu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmaxu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmaxu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.b =croc,crqc,crpc (c3_1) -(dni cpmax3_b_C3 "cpmax3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmax3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.h =croc,crqc,crpc (c3_1) -(dni cpmax3_h_C3 "cpmax3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmax3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.w =croc,crqc,crpc (c3_1) -(dni cpmaxu3_w_C3 "cpmaxu3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmaxu3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmaxu3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.w =croc,crqc,crpc (c3_1) -(dni cpmax3_w_C3 "cpmax3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmax3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.b =croc,crqc,crpc (c3_1) -(dni cpminu3_b_C3 "cpminu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpminu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpminu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.b =croc,crqc,crpc (c3_1) -(dni cpmin3_b_C3 "cpmin3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmin3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.h =croc,crqc,crpc (c3_1) -(dni cpmin3_h_C3 "cpmin3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmin3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.w =croc,crqc,crpc (c3_1) -(dni cpminu3_w_C3 "cpminu3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpminu3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpminu3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.w =croc,crqc,crpc (c3_1) -(dni cpmin3_w_C3 "cpmin3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmin3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 00000 0 cpmovfrcsar0 =croc (c3_1) -(dni cpmovfrcsar0_C3 "cpmovfrcsar0 $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar0 $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcsar0" pc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 01111 0 cpmovfrcsar1 =croc (c3_1) -(dni cpmovfrcsar1_C3 "cpmovfrcsar1 $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar1 $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcsar1" pc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 00001 0 cpmovfrcc =croc (c3_1) -(dni cpmovfrcc_C3 "cpmovfrcc $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcc $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcc" pc)) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 10000 0 cpmovtocsar0 crqc (c3_1) -(dni cpmovtocsar0_C3 "cpmovtocsar0 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0") VOLATILE) - "cpmovtocsar0 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar0 0) - (c-call "ivc2_cpmovtocsar0" pc crqc) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 11111 0 cpmovtocsar1 crqc (c3_1) -(dni cpmovtocsar1_C3 "cpmovtocsar1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1") VOLATILE) - "cpmovtocsar1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar1 0) - (c-call "ivc2_cpmovtocsar1" pc crqc) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 10001 0 cpmovtocc crqc (c3_1) -(dni cpmovtocc_C3 "cpmovtocc $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc") VOLATILE) - "cpmovtocc $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpmovtocc" pc crqc) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00000 0 cpmov =croc,crqc (c3_1) -(dni cpmov_C3 "cpmov $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpmov $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmov" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00001 0 cpabsz.b =croc,crqc (c3_1) -(dni cpabsz_b_C3 "cpabsz.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsz.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00010 0 cpabsz.h =croc,crqc (c3_1) -(dni cpabsz_h_C3 "cpabsz.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabsz.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00011 0 cpabsz.w =croc,crqc (c3_1) -(dni cpabsz_w_C3 "cpabsz.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpabsz.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00100 0 cpldz.h =croc,crqc (c3_1) -(dni cpldz_h_C3 "cpldz.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpldz.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpldz_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00101 0 cpldz.w =croc,crqc (c3_1) -(dni cpldz_w_C3 "cpldz.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpldz.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpldz_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00110 0 cpnorm.h =croc,crqc (c3_1) -(dni cpnorm_h_C3 "cpnorm.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST)) - "cpnorm.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnorm_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00111 0 cpnorm.w =croc,crqc (c3_1) -(dni cpnorm_w_C3 "cpnorm.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST)) - "cpnorm.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnorm_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01000 0 cphaddu.b =croc,crqc (c3_1) -(dni cphaddu_b_C3 "cphaddu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cphaddu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x8) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphaddu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01001 0 cphadd.b =croc,crqc (c3_1) -(dni cphadd_b_C3 "cphadd.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST)) - "cphadd.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x9) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01010 0 cphadd.h =croc,crqc (c3_1) -(dni cphadd_h_C3 "cphadd.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST)) - "cphadd.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xa) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01011 0 cphadd.w =croc,crqc (c3_1) -(dni cphadd_w_C3 "cphadd.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST)) - "cphadd.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xb) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01100 0 cpccadd.b +crqc (c3_1) -(dni cpccadd_b_C3 "cpccadd.b $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY) VOLATILE) - "cpccadd.b $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xc) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpccadd_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01101 0 cpbcast.b =croc,crqc (c3_1) -(dni cpbcast_b_C3 "cpbcast.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST)) - "cpbcast.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xd) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01110 0 cpbcast.h =croc,crqc (c3_1) -(dni cpbcast_h_C3 "cpbcast.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST)) - "cpbcast.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xe) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01111 0 cpbcast.w =croc,crqc (c3_1) -(dni cpbcast_w_C3 "cpbcast.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST)) - "cpbcast.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10000 0 cpextuu.b =croc,crqc (c3_1) -(dni cpextuu_b_C3 "cpextuu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextuu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10001 0 cpextu.b =croc,crqc (c3_1) -(dni cpextu_b_C3 "cpextu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10010 0 cpextuu.h =croc,crqc (c3_1) -(dni cpextuu_h_C3 "cpextuu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextuu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10011 0 cpextu.h =croc,crqc (c3_1) -(dni cpextu_h_C3 "cpextu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10100 0 cpextlu.b =croc,crqc (c3_1) -(dni cpextlu_b_C3 "cpextlu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextlu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10101 0 cpextl.b =croc,crqc (c3_1) -(dni cpextl_b_C3 "cpextl.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextl.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextl_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10110 0 cpextlu.h =croc,crqc (c3_1) -(dni cpextlu_h_C3 "cpextlu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextlu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10111 0 cpextl.h =croc,crqc (c3_1) -(dni cpextl_h_C3 "cpextl.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpextl.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextl_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11000 0 cpcastub.h =croc,crqc (c3_1) -(dni cpcastub_h_C3 "cpcastub.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastub.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x18) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastub_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11001 0 cpcastb.h =croc,crqc (c3_1) -(dni cpcastb_h_C3 "cpcastb.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastb.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x19) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastb_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11100 0 cpcastub.w =croc,crqc (c3_1) -(dni cpcastub_w_C3 "cpcastub.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastub.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1c) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastub_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11101 0 cpcastb.w =croc,crqc (c3_1) -(dni cpcastb_w_C3 "cpcastb.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastb.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1d) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastb_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11110 0 cpcastuh.w =croc,crqc (c3_1) -(dni cpcastuh_w_C3 "cpcastuh.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastuh.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1e) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastuh_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11111 0 cpcasth.w =croc,crqc (c3_1) -(dni cpcasth_w_C3 "cpcasth.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcasth.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcasth_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11010 0 cdcastuw =croc,crqc (c3_1) -(dni cdcastuw_C3 "cdcastuw $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastuw $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1a) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdcastuw" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11011 0 cdcastw =croc,crqc (c3_1) -(dni cdcastw_C3 "cdcastw $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastw $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1b) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdcastw" pc crqc)) ) - () - ) - -; 1111 0000 0000 0111 10010 qqqqq ppppp 0 cpcmpeqz.b crqc,crpc (c3_1) -(dni cpcmpeqz_b_C3 "cpcmpeqz.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeqz.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeqz_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 10010 qqqqq ppppp 0 cpcmpeq.b crqc,crpc (c3_1) -(dni cpcmpeq_b_C3 "cpcmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0011 0111 10010 qqqqq ppppp 0 cpcmpeq.h crqc,crpc (c3_1) -(dni cpcmpeq_h_C3 "cpcmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE) - "cpcmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 10010 qqqqq ppppp 0 cpcmpeq.w crqc,crpc (c3_1) -(dni cpcmpeq_w_C3 "cpcmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE) - "cpcmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 10010 qqqqq ppppp 0 cpcmpne.b crqc,crpc (c3_1) -(dni cpcmpne_b_C3 "cpcmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE) - "cpcmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 10010 qqqqq ppppp 0 cpcmpne.h crqc,crpc (c3_1) -(dni cpcmpne_h_C3 "cpcmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE) - "cpcmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 10010 qqqqq ppppp 0 cpcmpne.w crqc,crpc (c3_1) -(dni cpcmpne_w_C3 "cpcmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE) - "cpcmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 10010 qqqqq ppppp 0 cpcmpgtu.b crqc,crpc (c3_1) -(dni cpcmpgtu_b_C3 "cpcmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 10010 qqqqq ppppp 0 cpcmpgt.b crqc,crpc (c3_1) -(dni cpcmpgt_b_C3 "cpcmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE) - "cpcmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 10010 qqqqq ppppp 0 cpcmpgt.h crqc,crpc (c3_1) -(dni cpcmpgt_h_C3 "cpcmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE) - "cpcmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 10010 qqqqq ppppp 0 cpcmpgtu.w crqc,crpc (c3_1) -(dni cpcmpgtu_w_C3 "cpcmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 10010 qqqqq ppppp 0 cpcmpgt.w crqc,crpc (c3_1) -(dni cpcmpgt_w_C3 "cpcmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE) - "cpcmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1000 0111 10010 qqqqq ppppp 0 cpcmpgeu.b crqc,crpc (c3_1) -(dni cpcmpgeu_b_C3 "cpcmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0001 1001 0111 10010 qqqqq ppppp 0 cpcmpge.b crqc,crpc (c3_1) -(dni cpcmpge_b_C3 "cpcmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE) - "cpcmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0001 1011 0111 10010 qqqqq ppppp 0 cpcmpge.h crqc,crpc (c3_1) -(dni cpcmpge_h_C3 "cpcmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE) - "cpcmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1100 0111 10010 qqqqq ppppp 0 cpcmpgeu.w crqc,crpc (c3_1) -(dni cpcmpgeu_w_C3 "cpcmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1101 0111 10010 qqqqq ppppp 0 cpcmpge.w crqc,crpc (c3_1) -(dni cpcmpge_w_C3 "cpcmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE) - "cpcmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_w" pc crqc crpc) ) - () - ) - -; 1111 0010 0001 0111 10010 qqqqq ppppp 0 cpacmpeq.b crqc,crpc (c3_1) -(dni cpacmpeq_b_C3 "cpacmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI)) - "cpacmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0010 0011 0111 10010 qqqqq ppppp 0 cpacmpeq.h crqc,crpc (c3_1) -(dni cpacmpeq_h_C3 "cpacmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI)) - "cpacmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0101 0111 10010 qqqqq ppppp 0 cpacmpeq.w crqc,crpc (c3_1) -(dni cpacmpeq_w_C3 "cpacmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI)) - "cpacmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0010 1001 0111 10010 qqqqq ppppp 0 cpacmpne.b crqc,crpc (c3_1) -(dni cpacmpne_b_C3 "cpacmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI)) - "cpacmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0010 1011 0111 10010 qqqqq ppppp 0 cpacmpne.h crqc,crpc (c3_1) -(dni cpacmpne_h_C3 "cpacmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI)) - "cpacmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0010 1101 0111 10010 qqqqq ppppp 0 cpacmpne.w crqc,crpc (c3_1) -(dni cpacmpne_w_C3 "cpacmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI)) - "cpacmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0000 0111 10010 qqqqq ppppp 0 cpacmpgtu.b crqc,crpc (c3_1) -(dni cpacmpgtu_b_C3 "cpacmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI)) - "cpacmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0011 0001 0111 10010 qqqqq ppppp 0 cpacmpgt.b crqc,crpc (c3_1) -(dni cpacmpgt_b_C3 "cpacmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI)) - "cpacmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0011 0011 0111 10010 qqqqq ppppp 0 cpacmpgt.h crqc,crpc (c3_1) -(dni cpacmpgt_h_C3 "cpacmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI)) - "cpacmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0100 0111 10010 qqqqq ppppp 0 cpacmpgtu.w crqc,crpc (c3_1) -(dni cpacmpgtu_w_C3 "cpacmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI)) - "cpacmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0101 0111 10010 qqqqq ppppp 0 cpacmpgt.w crqc,crpc (c3_1) -(dni cpacmpgt_w_C3 "cpacmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI)) - "cpacmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1000 0111 10010 qqqqq ppppp 0 cpacmpgeu.b crqc,crpc (c3_1) -(dni cpacmpgeu_b_C3 "cpacmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI)) - "cpacmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0011 1001 0111 10010 qqqqq ppppp 0 cpacmpge.b crqc,crpc (c3_1) -(dni cpacmpge_b_C3 "cpacmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI)) - "cpacmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0011 1011 0111 10010 qqqqq ppppp 0 cpacmpge.h crqc,crpc (c3_1) -(dni cpacmpge_h_C3 "cpacmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI)) - "cpacmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1100 0111 10010 qqqqq ppppp 0 cpacmpgeu.w crqc,crpc (c3_1) -(dni cpacmpgeu_w_C3 "cpacmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI)) - "cpacmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1101 0111 10010 qqqqq ppppp 0 cpacmpge.w crqc,crpc (c3_1) -(dni cpacmpge_w_C3 "cpacmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI)) - "cpacmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_w" pc crqc crpc) ) - () - ) - -; 1111 0100 0001 0111 10010 qqqqq ppppp 0 cpocmpeq.b crqc,crpc (c3_1) -(dni cpocmpeq_b_C3 "cpocmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI)) - "cpocmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0100 0011 0111 10010 qqqqq ppppp 0 cpocmpeq.h crqc,crpc (c3_1) -(dni cpocmpeq_h_C3 "cpocmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI)) - "cpocmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0100 0101 0111 10010 qqqqq ppppp 0 cpocmpeq.w crqc,crpc (c3_1) -(dni cpocmpeq_w_C3 "cpocmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI)) - "cpocmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1001 0111 10010 qqqqq ppppp 0 cpocmpne.b crqc,crpc (c3_1) -(dni cpocmpne_b_C3 "cpocmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI)) - "cpocmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0100 1011 0111 10010 qqqqq ppppp 0 cpocmpne.h crqc,crpc (c3_1) -(dni cpocmpne_h_C3 "cpocmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI)) - "cpocmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1101 0111 10010 qqqqq ppppp 0 cpocmpne.w crqc,crpc (c3_1) -(dni cpocmpne_w_C3 "cpocmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI)) - "cpocmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0101 0000 0111 10010 qqqqq ppppp 0 cpocmpgtu.b crqc,crpc (c3_1) -(dni cpocmpgtu_b_C3 "cpocmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI)) - "cpocmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0101 0001 0111 10010 qqqqq ppppp 0 cpocmpgt.b crqc,crpc (c3_1) -(dni cpocmpgt_b_C3 "cpocmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI)) - "cpocmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0101 0011 0111 10010 qqqqq ppppp 0 cpocmpgt.h crqc,crpc (c3_1) -(dni cpocmpgt_h_C3 "cpocmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI)) - "cpocmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0101 0100 0111 10010 qqqqq ppppp 0 cpocmpgtu.w crqc,crpc (c3_1) -(dni cpocmpgtu_w_C3 "cpocmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI)) - "cpocmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0101 0101 0111 10010 qqqqq ppppp 0 cpocmpgt.w crqc,crpc (c3_1) -(dni cpocmpgt_w_C3 "cpocmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI)) - "cpocmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0101 1000 0111 10010 qqqqq ppppp 0 cpocmpgeu.b crqc,crpc (c3_1) -(dni cpocmpgeu_b_C3 "cpocmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI)) - "cpocmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0101 1001 0111 10010 qqqqq ppppp 0 cpocmpge.b crqc,crpc (c3_1) -(dni cpocmpge_b_C3 "cpocmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI)) - "cpocmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0101 1011 0111 10010 qqqqq ppppp 0 cpocmpge.h crqc,crpc (c3_1) -(dni cpocmpge_h_C3 "cpocmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI)) - "cpocmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0101 1100 0111 10010 qqqqq ppppp 0 cpocmpgeu.w crqc,crpc (c3_1) -(dni cpocmpgeu_w_C3 "cpocmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI)) - "cpocmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0101 1101 0111 10010 qqqqq ppppp 0 cpocmpge.w crqc,crpc (c3_1) -(dni cpocmpge_w_C3 "cpocmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI)) - "cpocmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_w" pc crqc crpc) ) - () - ) - -; 1111 00xx xiii 0111 10100 qqqqq ppppp 0 cpsrli3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpsrli3_b_C3 "cpsrli3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrli3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10100 qqqqq ppppp 0 cpsrli3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpsrli3_h_C3 "cpsrli3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrli3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10100 qqqqq ppppp 0 cpsrli3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpsrli3_w_C3 "cpsrli3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrli3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10100 qqqqq ppppp 0 cdsrli3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdsrli3_C3 "cdsrli3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrli3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdsrli3" pc crpc imm6p6)) ) - () - ) - -; 1111 00xx xiii 0111 10101 qqqqq ppppp 0 cpsrai3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpsrai3_b_C3 "cpsrai3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrai3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10101 qqqqq ppppp 0 cpsrai3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpsrai3_h_C3 "cpsrai3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrai3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10101 qqqqq ppppp 0 cpsrai3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpsrai3_w_C3 "cpsrai3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrai3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10101 qqqqq ppppp 0 cdsrai3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdsrai3_C3 "cdsrai3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrai3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdsrai3" pc crpc imm6p6)) ) - () - ) - -; 1111 00xx xiii 0111 10110 qqqqq ppppp 0 cpslli3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpslli3_b_C3 "cpslli3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpslli3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10110 qqqqq ppppp 0 cpslli3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpslli3_h_C3 "cpslli3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpslli3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10110 qqqqq ppppp 0 cpslli3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpslli3_w_C3 "cpslli3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpslli3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10110 qqqqq ppppp 0 cdslli3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdslli3_C3 "cdslli3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdslli3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdslli3" pc crpc imm6p6)) ) - () - ) - -; 1111 01xx iiii 0111 10111 qqqqq ppppp 0 cpslai3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpslai3_h_C3 "cpslai3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpslai3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslai3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10111 qqqqq ppppp 0 cpslai3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpslai3_w_C3 "cpslai3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpslai3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslai3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 00xi iiii 0111 11000 qqqqq ppppp 0 cpclipiu3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpclipiu3_w_C3 "cpclipiu3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipiu3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpclipiu3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 01xi iiii 0111 11000 qqqqq ppppp 0 cpclipi3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpclipi3_w_C3 "cpclipi3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipi3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpclipi3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 10ii iiii 0111 11000 qqqqq ppppp 0 cdclipiu3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdclipiu3_C3 "cdclipiu3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipiu3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x2) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdclipiu3" pc crpc imm6p6)) ) - () - ) - -; 1111 11ii iiii 0111 11000 qqqqq ppppp 0 cdclipi3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdclipi3_C3 "cdclipi3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipi3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdclipi3" pc crpc imm6p6)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00000 0 cpmovi.b =crqc,simm8p4 (c3_imm) -(dni cpmovi_b_C3 "cpmovi.b $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmovi.b $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_b" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00010 0 cpmoviu.h =crqc,imm8p4 (c3_imm) -(dni cpmoviu_h_C3 "cpmoviu.h $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpmoviu.h $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmoviu_h" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00011 0 cpmovi.h =crqc,simm8p4 (c3_imm) -(dni cpmovi_h_C3 "cpmovi.h $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmovi.h $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_h" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00100 0 cpmoviu.w =crqc,imm8p4 (c3_imm) -(dni cpmoviu_w_C3 "cpmoviu.w $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST)) - "cpmoviu.w $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmoviu_w" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00101 0 cpmovi.w =crqc,simm8p4 (c3_imm) -(dni cpmovi_w_C3 "cpmovi.w $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmovi.w $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_w" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00110 0 cdmoviu =crqc,imm8p4 (c3_imm) -(dni cdmoviu_C3 "cdmoviu $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmoviu $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdmoviu" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00111 0 cdmovi =crqc,simm8p4 (c3_imm) -(dni cdmovi_C3 "cdmovi $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmovi $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdmovi" pc simm8p4)) ) - () - ) - -; 1111 0000 0000 0111 00000 qqqqq ppppp 1 cpadda1u.b crqc,crpc (c3_1) -(dni cpadda1u_b_C3 "cpadda1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 00000 qqqqq ppppp 1 cpadda1.b crqc,crpc (c3_1) -(dni cpadda1_b_C3 "cpadda1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE) - "cpadda1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0010 0111 00000 qqqqq ppppp 1 cpaddua1.h crqc,crpc (c3_1) -(dni cpaddua1_h_C3 "cpaddua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaddua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0011 0111 00000 qqqqq ppppp 1 cpaddla1.h crqc,crpc (c3_1) -(dni cpaddla1_h_C3 "cpaddla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpaddla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0100 0111 00000 qqqqq ppppp 1 cpaddaca1u.b crqc,crpc (c3_1) -(dni cpaddaca1u_b_C3 "cpaddaca1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 00000 qqqqq ppppp 1 cpaddaca1.b crqc,crpc (c3_1) -(dni cpaddaca1_b_C3 "cpaddaca1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0110 0111 00000 qqqqq ppppp 1 cpaddacua1.h crqc,crpc (c3_1) -(dni cpaddacua1_h_C3 "cpaddacua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x6) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0111 0111 00000 qqqqq ppppp 1 cpaddacla1.h crqc,crpc (c3_1) -(dni cpaddacla1_h_C3 "cpaddacla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x7) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1000 0111 00000 qqqqq ppppp 1 cpsuba1u.b crqc,crpc (c3_1) -(dni cpsuba1u_b_C3 "cpsuba1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 00000 qqqqq ppppp 1 cpsuba1.b crqc,crpc (c3_1) -(dni cpsuba1_b_C3 "cpsuba1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE) - "cpsuba1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1010 0111 00000 qqqqq ppppp 1 cpsubua1.h crqc,crpc (c3_1) -(dni cpsubua1_h_C3 "cpsubua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsubua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 00000 qqqqq ppppp 1 cpsubla1.h crqc,crpc (c3_1) -(dni cpsubla1_h_C3 "cpsubla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsubla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1100 0111 00000 qqqqq ppppp 1 cpsubaca1u.b crqc,crpc (c3_1) -(dni cpsubaca1u_b_C3 "cpsubaca1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 00000 qqqqq ppppp 1 cpsubaca1.b crqc,crpc (c3_1) -(dni cpsubaca1_b_C3 "cpsubaca1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1110 0111 00000 qqqqq ppppp 1 cpsubacua1.h crqc,crpc (c3_1) -(dni cpsubacua1_h_C3 "cpsubacua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1111 0111 00000 qqqqq ppppp 1 cpsubacla1.h crqc,crpc (c3_1) -(dni cpsubacla1_h_C3 "cpsubacla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 00000 qqqqq ppppp 1 cpabsa1u.b crqc,crpc (c3_1) -(dni cpabsa1u_b_C3 "cpabsa1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 00000 qqqqq ppppp 1 cpabsa1.b crqc,crpc (c3_1) -(dni cpabsa1_b_C3 "cpabsa1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE) - "cpabsa1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0010 0111 00000 qqqqq ppppp 1 cpabsua1.h crqc,crpc (c3_1) -(dni cpabsua1_h_C3 "cpabsua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE) - "cpabsua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 00000 qqqqq ppppp 1 cpabsla1.h crqc,crpc (c3_1) -(dni cpabsla1_h_C3 "cpabsla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE) - "cpabsla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpabsla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 00000 qqqqq ppppp 1 cpsada1u.b crqc,crpc (c3_1) -(dni cpsada1u_b_C3 "cpsada1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 00000 qqqqq ppppp 1 cpsada1.b crqc,crpc (c3_1) -(dni cpsada1_b_C3 "cpsada1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE) - "cpsada1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0110 0111 00000 qqqqq ppppp 1 cpsadua1.h crqc,crpc (c3_1) -(dni cpsadua1_h_C3 "cpsadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0111 0111 00000 qqqqq ppppp 1 cpsadla1.h crqc,crpc (c3_1) -(dni cpsadla1_h_C3 "cpsadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0000 0111 00000 qqqqq ppppp 1 cpseta1.h crqc,crpc (c3_1) -(dni cpseta1_h_C3 "cpseta1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE) - "cpseta1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpseta1_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0010 0111 00000 qqqqq ppppp 1 cpsetua1.w crqc,crpc (c3_1) -(dni cpsetua1_w_C3 "cpsetua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE) - "cpsetua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsetua1_w" pc crqc crpc) ) - () - ) - -; 1111 0010 0011 0111 00000 qqqqq ppppp 1 cpsetla1.w crqc,crpc (c3_1) -(dni cpsetla1_w_C3 "cpsetla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE) - "cpsetla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsetla1_w" pc crqc crpc) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00000 1 cpmova1.b =croc (c3_1) -(dni cpmova1_b_C3 "cpmova1.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova1.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmova1_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00010 1 cpmovua1.h =croc (c3_1) -(dni cpmovua1_h_C3 "cpmovua1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovua1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00011 1 cpmovla1.h =croc (c3_1) -(dni cpmovla1_h_C3 "cpmovla1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovla1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00100 1 cpmovuua1.w =croc (c3_1) -(dni cpmovuua1_w_C3 "cpmovuua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovuua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00101 1 cpmovula1.w =croc (c3_1) -(dni cpmovula1_w_C3 "cpmovula1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovula1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00110 1 cpmovlua1.w =croc (c3_1) -(dni cpmovlua1_w_C3 "cpmovlua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovlua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00111 1 cpmovlla1.w =croc (c3_1) -(dni cpmovlla1_w_C3 "cpmovlla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovlla1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10000 1 cppacka1u.b =croc (c3_1) -(dni cppacka1u_b_C3 "cppacka1u.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka1u.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacka1u_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10001 1 cppacka1.b =croc (c3_1) -(dni cppacka1_b_C3 "cppacka1.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka1.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacka1_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10010 1 cppackua1.h =croc (c3_1) -(dni cppackua1_h_C3 "cppackua1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackua1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10011 1 cppackla1.h =croc (c3_1) -(dni cppackla1_h_C3 "cppackla1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackla1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10100 1 cppackua1.w =croc (c3_1) -(dni cppackua1_w_C3 "cppackua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10101 1 cppackla1.w =croc (c3_1) -(dni cppackla1_w_C3 "cppackla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackla1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10110 1 cpmovhua1.w =croc (c3_1) -(dni cpmovhua1_w_C3 "cpmovhua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovhua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10111 1 cpmovhla1.w =croc (c3_1) -(dni cpmovhla1_w_C3 "cpmovhla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovhla1_w" pc)) ) - () - ) - -; 1111 0000 0000 0111 00010 qqqqq 00000 1 cpsrla1 crqc (c3_1) -(dni cpsrla1_C3 "cpsrla1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrla1") VOLATILE) - "cpsrla1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrla1" pc crqc) ) - () - ) - -; 1111 0000 0001 0111 00010 qqqqq 00000 1 cpsraa1 crqc (c3_1) -(dni cpsraa1_C3 "cpsraa1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraa1") VOLATILE) - "cpsraa1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraa1" pc crqc) ) - () - ) - -; 1111 0000 0010 0111 00010 qqqqq 00000 1 cpslla1 crqc (c3_1) -(dni cpslla1_C3 "cpslla1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslla1") VOLATILE) - "cpslla1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpslla1" pc crqc) ) - () - ) - -; 1111 00xi iiii 0111 00011 00000 00000 1 cpsrlia1 imm5p7 (c3_imm) -(dni cpsrlia1_P1 "cpsrlia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrlia1") VOLATILE) - "cpsrlia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrlia1" pc imm5p7) ) - () - ) - -; 1111 01xi iiii 0111 00011 00000 00000 1 cpsraia1 imm5p7 (c3_imm) -(dni cpsraia1_P1 "cpsraia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraia1") VOLATILE) - "cpsraia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraia1" pc imm5p7) ) - () - ) - -; 1111 10xi iiii 0111 00011 00000 00000 1 cpsllia1 imm5p7 (c3_imm) -(dni cpsllia1_P1 "cpsllia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsllia1") VOLATILE) - "cpsllia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsllia1" pc imm5p7) ) - () - ) - -; 1111 0000 0000 0111 00001 qqqqq ppppp 1 cpssqa1u.b crqc,crpc (c3_1) -(dni cpssqa1u_b_C3 "cpssqa1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssqa1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 00001 qqqqq ppppp 1 cpssqa1.b crqc,crpc (c3_1) -(dni cpssqa1_b_C3 "cpssqa1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE) - "cpssqa1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0100 0111 00001 qqqqq ppppp 1 cpssda1u.b crqc,crpc (c3_1) -(dni cpssda1u_b_C3 "cpssda1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssda1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpssda1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 00001 qqqqq ppppp 1 cpssda1.b crqc,crpc (c3_1) -(dni cpssda1_b_C3 "cpssda1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE) - "cpssda1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpssda1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1000 0111 00001 qqqqq ppppp 1 cpmula1u.b crqc,crpc (c3_1) -(dni cpmula1u_b_C3 "cpmula1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmula1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 00001 qqqqq ppppp 1 cpmula1.b crqc,crpc (c3_1) -(dni cpmula1_b_C3 "cpmula1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE) - "cpmula1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1010 0111 00001 qqqqq ppppp 1 cpmulua1.h crqc,crpc (c3_1) -(dni cpmulua1_h_C3 "cpmulua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 00001 qqqqq ppppp 1 cpmulla1.h crqc,crpc (c3_1) -(dni cpmulla1_h_C3 "cpmulla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1100 0111 00001 qqqqq ppppp 1 cpmulua1u.w crqc,crpc (c3_1) -(dni cpmulua1u_w_C3 "cpmulua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 00001 qqqqq ppppp 1 cpmulla1u.w crqc,crpc (c3_1) -(dni cpmulla1u_w_C3 "cpmulla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1110 0111 00001 qqqqq ppppp 1 cpmulua1.w crqc,crpc (c3_1) -(dni cpmulua1_w_C3 "cpmulua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1111 0111 00001 qqqqq ppppp 1 cpmulla1.w crqc,crpc (c3_1) -(dni cpmulla1_w_C3 "cpmulla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 00001 qqqqq ppppp 1 cpmada1u.b crqc,crpc (c3_1) -(dni cpmada1u_b_C3 "cpmada1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmada1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 00001 qqqqq ppppp 1 cpmada1.b crqc,crpc (c3_1) -(dni cpmada1_b_C3 "cpmada1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE) - "cpmada1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0010 0111 00001 qqqqq ppppp 1 cpmadua1.h crqc,crpc (c3_1) -(dni cpmadua1_h_C3 "cpmadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpmadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 00001 qqqqq ppppp 1 cpmadla1.h crqc,crpc (c3_1) -(dni cpmadla1_h_C3 "cpmadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpmadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 00001 qqqqq ppppp 1 cpmadua1u.w crqc,crpc (c3_1) -(dni cpmadua1u_w_C3 "cpmadua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 00001 qqqqq ppppp 1 cpmadla1u.w crqc,crpc (c3_1) -(dni cpmadla1u_w_C3 "cpmadla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0110 0111 00001 qqqqq ppppp 1 cpmadua1.w crqc,crpc (c3_1) -(dni cpmadua1_w_C3 "cpmadua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpmadua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0111 0111 00001 qqqqq ppppp 1 cpmadla1.w crqc,crpc (c3_1) -(dni cpmadla1_w_C3 "cpmadla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpmadla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1010 0111 00001 qqqqq ppppp 1 cpmsbua1.h crqc,crpc (c3_1) -(dni cpmsbua1_h_C3 "cpmsbua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1011 0111 00001 qqqqq ppppp 1 cpmsbla1.h crqc,crpc (c3_1) -(dni cpmsbla1_h_C3 "cpmsbla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1100 0111 00001 qqqqq ppppp 1 cpmsbua1u.w crqc,crpc (c3_1) -(dni cpmsbua1u_w_C3 "cpmsbua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1101 0111 00001 qqqqq ppppp 1 cpmsbla1u.w crqc,crpc (c3_1) -(dni cpmsbla1u_w_C3 "cpmsbla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1110 0111 00001 qqqqq ppppp 1 cpmsbua1.w crqc,crpc (c3_1) -(dni cpmsbua1_w_C3 "cpmsbua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1111 0111 00001 qqqqq ppppp 1 cpmsbla1.w crqc,crpc (c3_1) -(dni cpmsbla1_w_C3 "cpmsbla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0010 0111 00001 qqqqq ppppp 1 cpsmadua1.h crqc,crpc (c3_1) -(dni cpsmadua1_h_C3 "cpsmadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0011 0111 00001 qqqqq ppppp 1 cpsmadla1.h crqc,crpc (c3_1) -(dni cpsmadla1_h_C3 "cpsmadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0110 0111 00001 qqqqq ppppp 1 cpsmadua1.w crqc,crpc (c3_1) -(dni cpsmadua1_w_C3 "cpsmadua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0111 0111 00001 qqqqq ppppp 1 cpsmadla1.w crqc,crpc (c3_1) -(dni cpsmadla1_w_C3 "cpsmadla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1010 0111 00001 qqqqq ppppp 1 cpsmsbua1.h crqc,crpc (c3_1) -(dni cpsmsbua1_h_C3 "cpsmsbua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1011 0111 00001 qqqqq ppppp 1 cpsmsbla1.h crqc,crpc (c3_1) -(dni cpsmsbla1_h_C3 "cpsmsbla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1110 0111 00001 qqqqq ppppp 1 cpsmsbua1.w crqc,crpc (c3_1) -(dni cpsmsbua1_w_C3 "cpsmsbua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1111 0111 00001 qqqqq ppppp 1 cpsmsbla1.w crqc,crpc (c3_1) -(dni cpsmsbla1_w_C3 "cpsmsbla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1010 0111 00001 qqqqq ppppp 1 cpmulslua1.h crqc,crpc (c3_1) -(dni cpmulslua1_h_C3 "cpmulslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1011 0111 00001 qqqqq ppppp 1 cpmulslla1.h crqc,crpc (c3_1) -(dni cpmulslla1_h_C3 "cpmulslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1110 0111 00001 qqqqq ppppp 1 cpmulslua1.w crqc,crpc (c3_1) -(dni cpmulslua1_w_C3 "cpmulslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1111 0111 00001 qqqqq ppppp 1 cpmulslla1.w crqc,crpc (c3_1) -(dni cpmulslla1_w_C3 "cpmulslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 0010 0111 00001 qqqqq ppppp 1 cpsmadslua1.h crqc,crpc (c3_1) -(dni cpsmadslua1_h_C3 "cpsmadslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 0011 0111 00001 qqqqq ppppp 1 cpsmadslla1.h crqc,crpc (c3_1) -(dni cpsmadslla1_h_C3 "cpsmadslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 0110 0111 00001 qqqqq ppppp 1 cpsmadslua1.w crqc,crpc (c3_1) -(dni cpsmadslua1_w_C3 "cpsmadslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 0111 0111 00001 qqqqq ppppp 1 cpsmadslla1.w crqc,crpc (c3_1) -(dni cpsmadslla1_w_C3 "cpsmadslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 1010 0111 00001 qqqqq ppppp 1 cpsmsbslua1.h crqc,crpc (c3_1) -(dni cpsmsbslua1_h_C3 "cpsmsbslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 1011 0111 00001 qqqqq ppppp 1 cpsmsbslla1.h crqc,crpc (c3_1) -(dni cpsmsbslla1_h_C3 "cpsmsbslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 1110 0111 00001 qqqqq ppppp 1 cpsmsbslua1.w crqc,crpc (c3_1) -(dni cpsmsbslua1_w_C3 "cpsmsbslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 1111 0111 00001 qqqqq ppppp 1 cpsmsbslla1.w crqc,crpc (c3_1) -(dni cpsmsbslla1_w_C3 "cpsmsbslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_w" pc crqc crpc) ) - () - ) - -; 00000 00000 00000 00000 c0nop (p0_1) -(dni c0nop_P0_P0S "c0nop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p0-isa (SLOTS P0,P0S) (INTRINSIC "c0nop")) - "c0nop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_c0nop" pc) ) - () - ) - -; 00001 qqqqq ppppp ooooo cpadd3.b =crop,crqp,crpp (p0_1) -(dni cpadd3_b_P0S_P1 "cpadd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpadd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_b" pc crqp crpp)) ) - () - ) - -; 00010 qqqqq ppppp ooooo cpadd3.h =crop,crqp,crpp (p0_1) -(dni cpadd3_h_P0S_P1 "cpadd3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpadd3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x2) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_h" pc crqp crpp)) ) - () - ) - -; 00011 qqqqq ppppp ooooo cpadd3.w =crop,crqp,crpp (p0_1) -(dni cpadd3_w_P0S_P1 "cpadd3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpadd3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x3) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_w" pc crqp crpp)) ) - () - ) - -; 00101 qqqqq ppppp ooooo cpunpacku.b =crop,crqp,crpp (p0_1) -(dni cpunpacku_b_P0S_P1 "cpunpacku.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpunpacku.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x5) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_b" pc crqp crpp)) ) - () - ) - -; 00110 qqqqq ppppp ooooo cpunpacku.h =crop,crqp,crpp (p0_1) -(dni cpunpacku_h_P0S_P1 "cpunpacku.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpunpacku.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x6) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_h" pc crqp crpp)) ) - () - ) - -; 00111 qqqqq ppppp ooooo cpunpacku.w =crop,crqp,crpp (p0_1) -(dni cpunpacku_w_P0S_P1 "cpunpacku.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST)) - "cpunpacku.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x7) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_w" pc crqp crpp)) ) - () - ) - -; 01001 qqqqq ppppp ooooo cpunpackl.b =crop,crqp,crpp (p0_1) -(dni cpunpackl_b_P0S_P1 "cpunpackl.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpunpackl.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x9) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_b" pc crqp crpp)) ) - () - ) - -; 01010 qqqqq ppppp ooooo cpunpackl.h =crop,crqp,crpp (p0_1) -(dni cpunpackl_h_P0S_P1 "cpunpackl.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpunpackl.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xa) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_h" pc crqp crpp)) ) - () - ) - -; 01011 qqqqq ppppp ooooo cpunpackl.w =crop,crqp,crpp (p0_1) -(dni cpunpackl_w_P0S_P1 "cpunpackl.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST)) - "cpunpackl.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xb) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_w" pc crqp crpp)) ) - () - ) - -; 00100 qqqqq ppppp ooooo cpsel =crop,crqp,crpp (p0_1) -(dni cpsel_P0S_P1 "cpsel $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpsel $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x4) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsel" pc crqp crpp)) ) - () - ) - -; 01100 qqqqq ppppp ooooo cpfsftbs0 =crop,crqp,crpp (p0_1) -(dni cpfsftbs0_P0S_P1 "cpfsftbs0 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs0 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xc) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbs0" pc crqp crpp)) ) - () - ) - -; 01101 qqqqq ppppp ooooo cpfsftbs1 =crop,crqp,crpp (p0_1) -(dni cpfsftbs1_P0S_P1 "cpfsftbs1 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs1 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xd) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbs1" pc crqp crpp)) ) - () - ) - -; 10000 qqqqq 00000 ooooo cpmov =crop,crqp (p0_1) -(dni cpmov_P0S_P1 "cpmov $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpmov $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmov" pc crqp)) ) - () - ) - -; 10000 qqqqq 00001 ooooo cpabsz.b =crop,crqp (p0_1) -(dni cpabsz_b_P0S_P1 "cpabsz.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsz.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 00010 ooooo cpabsz.h =crop,crqp (p0_1) -(dni cpabsz_h_P0S_P1 "cpabsz.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabsz.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00011 ooooo cpabsz.w =crop,crqp (p0_1) -(dni cpabsz_w_P0S_P1 "cpabsz.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpabsz.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 00100 ooooo cpldz.h =crop,crqp (p0_1) -(dni cpldz_h_P0S_P1 "cpldz.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpldz.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpldz_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00101 ooooo cpldz.w =crop,crqp (p0_1) -(dni cpldz_w_P0S_P1 "cpldz.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpldz.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpldz_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 00110 ooooo cpnorm.h =crop,crqp (p0_1) -(dni cpnorm_h_P0S_P1 "cpnorm.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST)) - "cpnorm.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnorm_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00111 ooooo cpnorm.w =crop,crqp (p0_1) -(dni cpnorm_w_P0S_P1 "cpnorm.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST)) - "cpnorm.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnorm_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 01000 ooooo cphaddu.b =crop,crqp (p0_1) -(dni cphaddu_b_P0S_P1 "cphaddu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cphaddu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphaddu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01001 ooooo cphadd.b =crop,crqp (p0_1) -(dni cphadd_b_P0S_P1 "cphadd.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST)) - "cphadd.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01010 ooooo cphadd.h =crop,crqp (p0_1) -(dni cphadd_h_P0S_P1 "cphadd.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST)) - "cphadd.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 01011 ooooo cphadd.w =crop,crqp (p0_1) -(dni cphadd_w_P0S_P1 "cphadd.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST)) - "cphadd.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 01100 00000 cpccadd.b +crqp (p0_1) -(dni cpccadd_b_P0S_P1 "cpccadd.b $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY) VOLATILE) - "cpccadd.b $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xc) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpccadd_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01101 ooooo cpbcast.b =crop,crqp (p0_1) -(dni cpbcast_b_P0S_P1 "cpbcast.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST)) - "cpbcast.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01110 ooooo cpbcast.h =crop,crqp (p0_1) -(dni cpbcast_h_P0S_P1 "cpbcast.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST)) - "cpbcast.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 01111 ooooo cpbcast.w =crop,crqp (p0_1) -(dni cpbcast_w_P0S_P1 "cpbcast.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST)) - "cpbcast.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 10000 ooooo cpextuu.b =crop,crqp (p0_1) -(dni cpextuu_b_P0S_P1 "cpextuu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextuu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10001 ooooo cpextu.b =crop,crqp (p0_1) -(dni cpextu_b_P0S_P1 "cpextu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10010 ooooo cpextuu.h =crop,crqp (p0_1) -(dni cpextuu_h_P0S_P1 "cpextuu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextuu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10011 ooooo cpextu.h =crop,crqp (p0_1) -(dni cpextu_h_P0S_P1 "cpextu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10100 ooooo cpextlu.b =crop,crqp (p0_1) -(dni cpextlu_b_P0S_P1 "cpextlu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextlu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x14) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10101 ooooo cpextl.b =crop,crqp (p0_1) -(dni cpextl_b_P0S_P1 "cpextl.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextl.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x15) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextl_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10110 ooooo cpextlu.h =crop,crqp (p0_1) -(dni cpextlu_h_P0S_P1 "cpextlu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextlu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x16) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10111 ooooo cpextl.h =crop,crqp (p0_1) -(dni cpextl_h_P0S_P1 "cpextl.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpextl.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x17) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextl_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11000 ooooo cpcastub.h =crop,crqp (p0_1) -(dni cpcastub_h_P0S_P1 "cpcastub.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastub.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x18) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastub_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11001 ooooo cpcastb.h =crop,crqp (p0_1) -(dni cpcastb_h_P0S_P1 "cpcastb.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastb.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x19) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastb_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11100 ooooo cpcastub.w =crop,crqp (p0_1) -(dni cpcastub_w_P0S_P1 "cpcastub.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastub.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1c) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastub_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11101 ooooo cpcastb.w =crop,crqp (p0_1) -(dni cpcastb_w_P0S_P1 "cpcastb.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastb.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1d) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastb_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11110 ooooo cpcastuh.w =crop,crqp (p0_1) -(dni cpcastuh_w_P0S_P1 "cpcastuh.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastuh.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1e) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastuh_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11111 ooooo cpcasth.w =crop,crqp (p0_1) -(dni cpcasth_w_P0S_P1 "cpcasth.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcasth.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1f) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcasth_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11010 ooooo cdcastuw =crop,crqp (p0_1) -(dni cdcastuw_P0S_P1 "cdcastuw $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastuw $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1a) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdcastuw" pc crqp)) ) - () - ) - -; 10000 qqqqq 11011 ooooo cdcastw =crop,crqp (p0_1) -(dni cdcastw_P0S_P1 "cdcastw $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastw $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1b) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdcastw" pc crqp)) ) - () - ) - -; 10001 00000 00000 ooooo cpmovfrcsar0 =crop (p0_1) -(dni cpmovfrcsar0_P0S_P1 "cpmovfrcsar0 $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar0 $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcsar0" pc)) ) - () - ) - -; 10001 00000 01111 ooooo cpmovfrcsar1 =crop (p0_1) -(dni cpmovfrcsar1_P0S_P1 "cpmovfrcsar1 $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar1 $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcsar1" pc)) ) - () - ) - -; 10001 00000 00001 ooooo cpmovfrcc =crop (p0_1) -(dni cpmovfrcc_P0S_P1 "cpmovfrcc $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcc $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcc" pc)) ) - () - ) - -; 10001 qqqqq 10000 00000 cpmovtocsar0 crqp (p0_1) -(dni cpmovtocsar0_P0S_P1 "cpmovtocsar0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0") VOLATILE) - "cpmovtocsar0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar0 0) - (c-call "ivc2_cpmovtocsar0" pc crqp) ) - () - ) - -; 10001 qqqqq 11111 00000 cpmovtocsar1 crqp (p0_1) -(dni cpmovtocsar1_P0S_P1 "cpmovtocsar1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1") VOLATILE) - "cpmovtocsar1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x1f) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar1 0) - (c-call "ivc2_cpmovtocsar1" pc crqp) ) - () - ) - -; 10001 qqqqq 10001 00000 cpmovtocc crqp (p0_1) -(dni cpmovtocc_P0S_P1 "cpmovtocc $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc") VOLATILE) - "cpmovtocc $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpmovtocc" pc crqp) ) - () - ) - -; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1) -(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeqz.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeqz_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00001 cpcmpeq.b crqp,crpp (p0_1) -(dni cpcmpeq_b_P0S_P1 "cpcmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00011 cpcmpeq.h crqp,crpp (p0_1) -(dni cpcmpeq_h_P0S_P1 "cpcmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE) - "cpcmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00101 cpcmpeq.w crqp,crpp (p0_1) -(dni cpcmpeq_w_P0S_P1 "cpcmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE) - "cpcmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01001 cpcmpne.b crqp,crpp (p0_1) -(dni cpcmpne_b_P0S_P1 "cpcmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE) - "cpcmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01011 cpcmpne.h crqp,crpp (p0_1) -(dni cpcmpne_h_P0S_P1 "cpcmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE) - "cpcmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01101 cpcmpne.w crqp,crpp (p0_1) -(dni cpcmpne_w_P0S_P1 "cpcmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE) - "cpcmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10000 cpcmpgtu.b crqp,crpp (p0_1) -(dni cpcmpgtu_b_P0S_P1 "cpcmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10001 cpcmpgt.b crqp,crpp (p0_1) -(dni cpcmpgt_b_P0S_P1 "cpcmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE) - "cpcmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10011 cpcmpgt.h crqp,crpp (p0_1) -(dni cpcmpgt_h_P0S_P1 "cpcmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE) - "cpcmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10100 cpcmpgtu.w crqp,crpp (p0_1) -(dni cpcmpgtu_w_P0S_P1 "cpcmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10101 cpcmpgt.w crqp,crpp (p0_1) -(dni cpcmpgt_w_P0S_P1 "cpcmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE) - "cpcmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11000 cpcmpgeu.b crqp,crpp (p0_1) -(dni cpcmpgeu_b_P0S_P1 "cpcmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11001 cpcmpge.b crqp,crpp (p0_1) -(dni cpcmpge_b_P0S_P1 "cpcmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE) - "cpcmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11011 cpcmpge.h crqp,crpp (p0_1) -(dni cpcmpge_h_P0S_P1 "cpcmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE) - "cpcmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11100 cpcmpgeu.w crqp,crpp (p0_1) -(dni cpcmpgeu_w_P0S_P1 "cpcmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11101 cpcmpge.w crqp,crpp (p0_1) -(dni cpcmpge_w_P0S_P1 "cpcmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE) - "cpcmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_w" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00000 cpadda0u.b crqp,crpp (p0_1) -(dni cpadda0u_b_P0S "cpadda0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpadda0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00001 cpadda0.b crqp,crpp (p0_1) -(dni cpadda0_b_P0S "cpadda0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI) VOLATILE) - "cpadda0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpadda0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00010 cpaddua0.h crqp,crpp (p0_1) -(dni cpaddua0_h_P0S "cpaddua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI) VOLATILE) - "cpaddua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpaddua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00011 cpaddla0.h crqp,crpp (p0_1) -(dni cpaddla0_h_P0S "cpaddla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI) VOLATILE) - "cpaddla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpaddla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00100 cpaddaca0u.b crqp,crpp (p0_1) -(dni cpaddaca0u_b_P0S "cpaddaca0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddaca0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00101 cpaddaca0.b crqp,crpp (p0_1) -(dni cpaddaca0_b_P0S "cpaddaca0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddaca0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00110 cpaddacua0.h crqp,crpp (p0_1) -(dni cpaddacua0_h_P0S "cpaddacua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddacua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00111 cpaddacla0.h crqp,crpp (p0_1) -(dni cpaddacla0_h_P0S "cpaddacla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddacla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01000 cpsuba0u.b crqp,crpp (p0_1) -(dni cpsuba0u_b_P0S "cpsuba0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsuba0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01001 cpsuba0.b crqp,crpp (p0_1) -(dni cpsuba0_b_P0S "cpsuba0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI) VOLATILE) - "cpsuba0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsuba0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01010 cpsubua0.h crqp,crpp (p0_1) -(dni cpsubua0_h_P0S "cpsubua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI) VOLATILE) - "cpsubua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsubua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01011 cpsubla0.h crqp,crpp (p0_1) -(dni cpsubla0_h_P0S "cpsubla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI) VOLATILE) - "cpsubla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpsubla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01100 cpsubaca0u.b crqp,crpp (p0_1) -(dni cpsubaca0u_b_P0S "cpsubaca0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubaca0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01101 cpsubaca0.b crqp,crpp (p0_1) -(dni cpsubaca0_b_P0S "cpsubaca0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubaca0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01110 cpsubacua0.h crqp,crpp (p0_1) -(dni cpsubacua0_h_P0S "cpsubacua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubacua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01111 cpsubacla0.h crqp,crpp (p0_1) -(dni cpsubacla0_h_P0S "cpsubacla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubacla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10000 cpabsa0u.b crqp,crpp (p0_1) -(dni cpabsa0u_b_P0S "cpabsa0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsa0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10001 cpabsa0.b crqp,crpp (p0_1) -(dni cpabsa0_b_P0S "cpabsa0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI) VOLATILE) - "cpabsa0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsa0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10010 cpabsua0.h crqp,crpp (p0_1) -(dni cpabsua0_h_P0S "cpabsua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI) VOLATILE) - "cpabsua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10011 cpabsla0.h crqp,crpp (p0_1) -(dni cpabsla0_h_P0S "cpabsla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI) VOLATILE) - "cpabsla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpabsla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10100 cpsada0u.b crqp,crpp (p0_1) -(dni cpsada0u_b_P0S "cpsada0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsada0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10101 cpsada0.b crqp,crpp (p0_1) -(dni cpsada0_b_P0S "cpsada0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI) VOLATILE) - "cpsada0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsada0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10110 cpsadua0.h crqp,crpp (p0_1) -(dni cpsadua0_h_P0S "cpsadua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI) VOLATILE) - "cpsadua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsadua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10111 cpsadla0.h crqp,crpp (p0_1) -(dni cpsadla0_h_P0S "cpsadla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI) VOLATILE) - "cpsadla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsadla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11011 cpseta0.h crqp,crpp (p0_1) -(dni cpseta0_h_P0S "cpseta0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI) VOLATILE) - "cpseta0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpseta0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11100 cpsetua0.w crqp,crpp (p0_1) -(dni cpsetua0_w_P0S "cpsetua0.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI) VOLATILE) - "cpsetua0.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsetua0_w" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11101 cpsetla0.w crqp,crpp (p0_1) -(dni cpsetla0_w_P0S "cpsetla0.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI) VOLATILE) - "cpsetla0.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpsetla0_w" pc crqp crpp) ) - () - ) - -; 11001 00000 00001 ooooo cpmova0.b =crop (p0_1) -(dni cpmova0_b_P0S "cpmova0.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmova0_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova0.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmova0_b" pc)) ) - () - ) - -; 11001 00000 00010 ooooo cpmovua0.h =crop (p0_1) -(dni cpmovua0_h_P0S "cpmovua0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovua0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovua0_h" pc)) ) - () - ) - -; 11001 00000 00011 ooooo cpmovla0.h =crop (p0_1) -(dni cpmovla0_h_P0S "cpmovla0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovla0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovla0_h" pc)) ) - () - ) - -; 11001 00000 00100 ooooo cpmovuua0.w =crop (p0_1) -(dni cpmovuua0_w_P0S "cpmovuua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovuua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovuua0_w" pc)) ) - () - ) - -; 11001 00000 00101 ooooo cpmovula0.w =crop (p0_1) -(dni cpmovula0_w_P0S "cpmovula0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovula0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovula0_w" pc)) ) - () - ) - -; 11001 00000 00110 ooooo cpmovlua0.w =crop (p0_1) -(dni cpmovlua0_w_P0S "cpmovlua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlua0_w" pc)) ) - () - ) - -; 11001 00000 00111 ooooo cpmovlla0.w =crop (p0_1) -(dni cpmovlla0_w_P0S "cpmovlla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlla0_w" pc)) ) - () - ) - -; 11001 00000 01000 ooooo cppacka0u.b =crop (p0_1) -(dni cppacka0u_b_P0S "cppacka0u.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka0u.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka0u_b" pc)) ) - () - ) - -; 11001 00000 01001 ooooo cppacka0.b =crop (p0_1) -(dni cppacka0_b_P0S "cppacka0.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka0.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka0_b" pc)) ) - () - ) - -; 11001 00000 01010 ooooo cppackua0.h =crop (p0_1) -(dni cppackua0_h_P0S "cppackua0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua0_h" pc)) ) - () - ) - -; 11001 00000 01011 ooooo cppackla0.h =crop (p0_1) -(dni cppackla0_h_P0S "cppackla0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla0_h" pc)) ) - () - ) - -; 11001 00000 01100 ooooo cppackua0.w =crop (p0_1) -(dni cppackua0_w_P0S "cppackua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua0_w" pc)) ) - () - ) - -; 11001 00000 01101 ooooo cppackla0.w =crop (p0_1) -(dni cppackla0_w_P0S "cppackla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla0_w" pc)) ) - () - ) - -; 11001 00000 01110 ooooo cpmovhua0.w =crop (p0_1) -(dni cpmovhua0_w_P0S "cpmovhua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhua0_w" pc)) ) - () - ) - -; 11001 00000 01111 ooooo cpmovhla0.w =crop (p0_1) -(dni cpmovhla0_w_P0S "cpmovhla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhla0_w" pc)) ) - () - ) - -; 11001 00000 10000 00000 cpacsuma0 (p0_1) -(dni cpacsuma0_P0S "cpacsuma0 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpacsuma0") VOLATILE) - "cpacsuma0" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpacsuma0" pc) ) - () - ) - -; 11001 00000 10001 00000 cpaccpa0 (p0_1) -(dni cpaccpa0_P0S "cpaccpa0 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaccpa0") VOLATILE) - "cpaccpa0" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpaccpa0" pc) ) - () - ) - -; 11001 qqqqq 11000 00000 cpsrla0 crqp (p0_1) -(dni cpsrla0_P0S "cpsrla0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrla0") VOLATILE) - "cpsrla0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsrla0" pc crqp) ) - () - ) - -; 11001 qqqqq 11001 00000 cpsraa0 crqp (p0_1) -(dni cpsraa0_P0S "cpsraa0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraa0") VOLATILE) - "cpsraa0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsraa0" pc crqp) ) - () - ) - -; 11001 qqqqq 11010 00000 cpslla0 crqp (p0_1) -(dni cpslla0_P0S "cpslla0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpslla0") VOLATILE) - "cpslla0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpslla0" pc crqp) ) - () - ) - -; 11001 00000 11100 iiiii cpsrlia0 imm5p23 (p0_1) -(dni cpsrlia0_P0S "cpsrlia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrlia0") VOLATILE) - "cpsrlia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsrlia0" pc imm5p23) ) - () - ) - -; 11001 00000 11101 iiiii cpsraia0 imm5p23 (p0_1) -(dni cpsraia0_P0S "cpsraia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraia0") VOLATILE) - "cpsraia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsraia0" pc imm5p23) ) - () - ) - -; 11001 00000 11110 iiiii cpsllia0 imm5p23 (p0_1) -(dni cpsllia0_P0S "cpsllia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsllia0") VOLATILE) - "cpsllia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsllia0" pc imm5p23) ) - () - ) - -; 11111 qqqqq ppppp 00000 cpfsftba0s0u.b crqp,crpp (p0_1) -(dni cpfsftba0s0u_b_P0S "cpfsftba0s0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfsftba0s0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s0u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00001 cpfsftba0s0.b crqp,crpp (p0_1) -(dni cpfsftba0s0_b_P0S "cpfsftba0s0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI) VOLATILE) - "cpfsftba0s0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s0_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00010 cpfsftbua0s0.h crqp,crpp (p0_1) -(dni cpfsftbua0s0_h_P0S "cpfsftbua0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbua0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftbua0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00011 cpfsftbla0s0.h crqp,crpp (p0_1) -(dni cpfsftbla0s0_h_P0S "cpfsftbla0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbla0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpfsftbla0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00100 cpfaca0s0u.b crqp,crpp (p0_1) -(dni cpfaca0s0u_b_P0S "cpfaca0s0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfaca0s0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s0u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00101 cpfaca0s0.b crqp,crpp (p0_1) -(dni cpfaca0s0_b_P0S "cpfaca0s0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI) VOLATILE) - "cpfaca0s0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s0_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00110 cpfacua0s0.h crqp,crpp (p0_1) -(dni cpfacua0s0_h_P0S "cpfacua0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfacua0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacua0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00111 cpfacla0s0.h crqp,crpp (p0_1) -(dni cpfacla0s0_h_P0S "cpfacla0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfacla0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacla0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01000 cpfsftba0s1u.b crqp,crpp (p0_1) -(dni cpfsftba0s1u_b_P0S "cpfsftba0s1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfsftba0s1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s1u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01001 cpfsftba0s1.b crqp,crpp (p0_1) -(dni cpfsftba0s1_b_P0S "cpfsftba0s1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI) VOLATILE) - "cpfsftba0s1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s1_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01010 cpfsftbua0s1.h crqp,crpp (p0_1) -(dni cpfsftbua0s1_h_P0S "cpfsftbua0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbua0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftbua0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01011 cpfsftbla0s1.h crqp,crpp (p0_1) -(dni cpfsftbla0s1_h_P0S "cpfsftbla0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbla0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpfsftbla0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01100 cpfaca0s1u.b crqp,crpp (p0_1) -(dni cpfaca0s1u_b_P0S "cpfaca0s1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfaca0s1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s1u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01101 cpfaca0s1.b crqp,crpp (p0_1) -(dni cpfaca0s1_b_P0S "cpfaca0s1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI) VOLATILE) - "cpfaca0s1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s1_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01110 cpfacua0s1.h crqp,crpp (p0_1) -(dni cpfacua0s1_h_P0S "cpfacua0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfacua0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacua0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01111 cpfacla0s1.h crqp,crpp (p0_1) -(dni cpfacla0s1_h_P0S "cpfacla0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfacla0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacla0s1_h" pc crqp crpp) ) - () - ) - -; xxxxxiii 01000 qqqqq ppppp ooooo cpfsftbi =crop,crqp,crpp,imm3p5 (p0_1) -(dni cpfsftbi_P0_P1 "cpfsftbi $crop,$crqp,$crpp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpfsftbi $crop,$crqp,$crpp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x8) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbi" pc crqp crpp imm3p5)) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00001 cpacmpeq.b crqp,crpp (p0_1) -(dni cpacmpeq_b_P0_P1 "cpacmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI)) - "cpacmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00011 cpacmpeq.h crqp,crpp (p0_1) -(dni cpacmpeq_h_P0_P1 "cpacmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI)) - "cpacmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00101 cpacmpeq.w crqp,crpp (p0_1) -(dni cpacmpeq_w_P0_P1 "cpacmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI)) - "cpacmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01001 cpacmpne.b crqp,crpp (p0_1) -(dni cpacmpne_b_P0_P1 "cpacmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI)) - "cpacmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01011 cpacmpne.h crqp,crpp (p0_1) -(dni cpacmpne_h_P0_P1 "cpacmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI)) - "cpacmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01101 cpacmpne.w crqp,crpp (p0_1) -(dni cpacmpne_w_P0_P1 "cpacmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI)) - "cpacmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10000 cpacmpgtu.b crqp,crpp (p0_1) -(dni cpacmpgtu_b_P0_P1 "cpacmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI)) - "cpacmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgtu_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10001 cpacmpgt.b crqp,crpp (p0_1) -(dni cpacmpgt_b_P0_P1 "cpacmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI)) - "cpacmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10011 cpacmpgt.h crqp,crpp (p0_1) -(dni cpacmpgt_h_P0_P1 "cpacmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI)) - "cpacmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10100 cpacmpgtu.w crqp,crpp (p0_1) -(dni cpacmpgtu_w_P0_P1 "cpacmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI)) - "cpacmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgtu_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10101 cpacmpgt.w crqp,crpp (p0_1) -(dni cpacmpgt_w_P0_P1 "cpacmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI)) - "cpacmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11000 cpacmpgeu.b crqp,crpp (p0_1) -(dni cpacmpgeu_b_P0_P1 "cpacmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI)) - "cpacmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgeu_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11001 cpacmpge.b crqp,crpp (p0_1) -(dni cpacmpge_b_P0_P1 "cpacmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI)) - "cpacmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11011 cpacmpge.h crqp,crpp (p0_1) -(dni cpacmpge_h_P0_P1 "cpacmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI)) - "cpacmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11100 cpacmpgeu.w crqp,crpp (p0_1) -(dni cpacmpgeu_w_P0_P1 "cpacmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI)) - "cpacmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgeu_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11101 cpacmpge.w crqp,crpp (p0_1) -(dni cpacmpge_w_P0_P1 "cpacmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI)) - "cpacmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00001 cpocmpeq.b crqp,crpp (p0_1) -(dni cpocmpeq_b_P0_P1 "cpocmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI)) - "cpocmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00011 cpocmpeq.h crqp,crpp (p0_1) -(dni cpocmpeq_h_P0_P1 "cpocmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI)) - "cpocmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00101 cpocmpeq.w crqp,crpp (p0_1) -(dni cpocmpeq_w_P0_P1 "cpocmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI)) - "cpocmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01001 cpocmpne.b crqp,crpp (p0_1) -(dni cpocmpne_b_P0_P1 "cpocmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI)) - "cpocmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01011 cpocmpne.h crqp,crpp (p0_1) -(dni cpocmpne_h_P0_P1 "cpocmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI)) - "cpocmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01101 cpocmpne.w crqp,crpp (p0_1) -(dni cpocmpne_w_P0_P1 "cpocmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI)) - "cpocmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10000 cpocmpgtu.b crqp,crpp (p0_1) -(dni cpocmpgtu_b_P0_P1 "cpocmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI)) - "cpocmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgtu_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10001 cpocmpgt.b crqp,crpp (p0_1) -(dni cpocmpgt_b_P0_P1 "cpocmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI)) - "cpocmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10011 cpocmpgt.h crqp,crpp (p0_1) -(dni cpocmpgt_h_P0_P1 "cpocmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI)) - "cpocmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10100 cpocmpgtu.w crqp,crpp (p0_1) -(dni cpocmpgtu_w_P0_P1 "cpocmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI)) - "cpocmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgtu_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10101 cpocmpgt.w crqp,crpp (p0_1) -(dni cpocmpgt_w_P0_P1 "cpocmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI)) - "cpocmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11000 cpocmpgeu.b crqp,crpp (p0_1) -(dni cpocmpgeu_b_P0_P1 "cpocmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI)) - "cpocmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgeu_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11001 cpocmpge.b crqp,crpp (p0_1) -(dni cpocmpge_b_P0_P1 "cpocmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI)) - "cpocmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11011 cpocmpge.h crqp,crpp (p0_1) -(dni cpocmpge_h_P0_P1 "cpocmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI)) - "cpocmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11100 cpocmpgeu.w crqp,crpp (p0_1) -(dni cpocmpgeu_w_P0_P1 "cpocmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI)) - "cpocmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgeu_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11101 cpocmpge.w crqp,crpp (p0_1) -(dni cpocmpge_w_P0_P1 "cpocmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI)) - "cpocmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_w" pc crqp crpp) ) - () - ) - -; 00000011 10100 qqqqq ppppp ooooo cdadd3 =crop,crqp,crpp (p0_1) -(dni cdadd3_P0_P1 "cdadd3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdadd3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdadd3" pc crqp crpp)) ) - () - ) - -; 00000100 10100 qqqqq ppppp ooooo cpsub3.b =crop,crqp,crpp (p0_1) -(dni cpsub3_b_P0_P1 "cpsub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_b" pc crqp crpp)) ) - () - ) - -; 00000101 10100 qqqqq ppppp ooooo cpsub3.h =crop,crqp,crpp (p0_1) -(dni cpsub3_h_P0_P1 "cpsub3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsub3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_h" pc crqp crpp)) ) - () - ) - -; 00000110 10100 qqqqq ppppp ooooo cpsub3.w =crop,crqp,crpp (p0_1) -(dni cpsub3_w_P0_P1 "cpsub3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsub3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x6) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_w" pc crqp crpp)) ) - () - ) - -; 00000111 10100 qqqqq ppppp ooooo cdsub3 =crop,crqp,crpp (p0_1) -(dni cdsub3_P0_P1 "cdsub3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsub3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x7) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsub3" pc crqp crpp)) ) - () - ) - -; 00001010 10100 qqqqq ppppp ooooo cpsadd3.h =crop,crqp,crpp (p0_1) -(dni cpsadd3_h_P0_P1 "cpsadd3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsadd3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xa) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsadd3_h" pc crqp crpp)) ) - () - ) - -; 00001011 10100 qqqqq ppppp ooooo cpsadd3.w =crop,crqp,crpp (p0_1) -(dni cpsadd3_w_P0_P1 "cpsadd3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsadd3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xb) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsadd3_w" pc crqp crpp)) ) - () - ) - -; 00001110 10100 qqqqq ppppp ooooo cpssub3.h =crop,crqp,crpp (p0_1) -(dni cpssub3_h_P0_P1 "cpssub3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpssub3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xe) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set crop (c-call DI "ivc2_cpssub3_h" pc crqp crpp)) ) - () - ) - -; 00001111 10100 qqqqq ppppp ooooo cpssub3.w =crop,crqp,crpp (p0_1) -(dni cpssub3_w_P0_P1 "cpssub3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpssub3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xf) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set crop (c-call DI "ivc2_cpssub3_w" pc crqp crpp)) ) - () - ) - -; 00010000 10100 qqqqq ppppp ooooo cpextuaddu3.b =crop,crqp,crpp (p0_1) -(dni cpextuaddu3_b_P0_P1 "cpextuaddu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuaddu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x10) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuaddu3_b" pc crqp crpp)) ) - () - ) - -; 00010001 10100 qqqqq ppppp ooooo cpextuadd3.b =crop,crqp,crpp (p0_1) -(dni cpextuadd3_b_P0_P1 "cpextuadd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuadd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x11) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuadd3_b" pc crqp crpp)) ) - () - ) - -; 00010010 10100 qqqqq ppppp ooooo cpextladdu3.b =crop,crqp,crpp (p0_1) -(dni cpextladdu3_b_P0_P1 "cpextladdu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladdu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x12) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextladdu3_b" pc crqp crpp)) ) - () - ) - -; 00010011 10100 qqqqq ppppp ooooo cpextladd3.b =crop,crqp,crpp (p0_1) -(dni cpextladd3_b_P0_P1 "cpextladd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x13) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextladd3_b" pc crqp crpp)) ) - () - ) - -; 00010100 10100 qqqqq ppppp ooooo cpextusubu3.b =crop,crqp,crpp (p0_1) -(dni cpextusubu3_b_P0_P1 "cpextusubu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusubu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x14) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextusubu3_b" pc crqp crpp)) ) - () - ) - -; 00010101 10100 qqqqq ppppp ooooo cpextusub3.b =crop,crqp,crpp (p0_1) -(dni cpextusub3_b_P0_P1 "cpextusub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x15) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextusub3_b" pc crqp crpp)) ) - () - ) - -; 00010110 10100 qqqqq ppppp ooooo cpextlsubu3.b =crop,crqp,crpp (p0_1) -(dni cpextlsubu3_b_P0_P1 "cpextlsubu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsubu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x16) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlsubu3_b" pc crqp crpp)) ) - () - ) - -; 00010111 10100 qqqqq ppppp ooooo cpextlsub3.b =crop,crqp,crpp (p0_1) -(dni cpextlsub3_b_P0_P1 "cpextlsub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x17) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlsub3_b" pc crqp crpp)) ) - () - ) - -; 00011000 10100 qqqqq ppppp ooooo cpaveu3.b =crop,crqp,crpp (p0_1) -(dni cpaveu3_b_P0_P1 "cpaveu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaveu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x18) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaveu3_b" pc crqp crpp)) ) - () - ) - -; 00011001 10100 qqqqq ppppp ooooo cpave3.b =crop,crqp,crpp (p0_1) -(dni cpave3_b_P0_P1 "cpave3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpave3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x19) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_b" pc crqp crpp)) ) - () - ) - -; 00011010 10100 qqqqq ppppp ooooo cpave3.h =crop,crqp,crpp (p0_1) -(dni cpave3_h_P0_P1 "cpave3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpave3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_h" pc crqp crpp)) ) - () - ) - -; 00011011 10100 qqqqq ppppp ooooo cpave3.w =crop,crqp,crpp (p0_1) -(dni cpave3_w_P0_P1 "cpave3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpave3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_w" pc crqp crpp)) ) - () - ) - -; 00011100 10100 qqqqq ppppp ooooo cpaddsru3.b =crop,crqp,crpp (p0_1) -(dni cpaddsru3_b_P0_P1 "cpaddsru3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsru3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsru3_b" pc crqp crpp)) ) - () - ) - -; 00011101 10100 qqqqq ppppp ooooo cpaddsr3.b =crop,crqp,crpp (p0_1) -(dni cpaddsr3_b_P0_P1 "cpaddsr3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsr3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_b" pc crqp crpp)) ) - () - ) - -; 00011110 10100 qqqqq ppppp ooooo cpaddsr3.h =crop,crqp,crpp (p0_1) -(dni cpaddsr3_h_P0_P1 "cpaddsr3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpaddsr3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_h" pc crqp crpp)) ) - () - ) - -; 00011111 10100 qqqqq ppppp ooooo cpaddsr3.w =crop,crqp,crpp (p0_1) -(dni cpaddsr3_w_P0_P1 "cpaddsr3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpaddsr3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_w" pc crqp crpp)) ) - () - ) - -; 00100000 10100 qqqqq ppppp ooooo cpabsu3.b =crop,crqp,crpp (p0_1) -(dni cpabsu3_b_P0_P1 "cpabsu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x20) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsu3_b" pc crqp crpp)) ) - () - ) - -; 00100001 10100 qqqqq ppppp ooooo cpabs3.b =crop,crqp,crpp (p0_1) -(dni cpabs3_b_P0_P1 "cpabs3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabs3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x21) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabs3_b" pc crqp crpp)) ) - () - ) - -; 00100010 10100 qqqqq ppppp ooooo cpabs3.h =crop,crqp,crpp (p0_1) -(dni cpabs3_h_P0_P1 "cpabs3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabs3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x22) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabs3_h" pc crqp crpp)) ) - () - ) - -; 00100100 10100 qqqqq ppppp ooooo cpand3 =crop,crqp,crpp (p0_1) -(dni cpand3_P0_P1 "cpand3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST)) - "cpand3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x24) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpand3" pc crqp crpp)) ) - () - ) - -; 00100101 10100 qqqqq ppppp ooooo cpor3 =crop,crqp,crpp (p0_1) -(dni cpor3_P0_P1 "cpor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST)) - "cpor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x25) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpor3" pc crqp crpp)) ) - () - ) - -; 00100110 10100 qqqqq ppppp ooooo cpnor3 =crop,crqp,crpp (p0_1) -(dni cpnor3_P0_P1 "cpnor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST)) - "cpnor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x26) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnor3" pc crqp crpp)) ) - () - ) - -; 00100111 10100 qqqqq ppppp ooooo cpxor3 =crop,crqp,crpp (p0_1) -(dni cpxor3_P0_P1 "cpxor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST)) - "cpxor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x27) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpxor3" pc crqp crpp)) ) - () - ) - -; 00101100 10100 qqqqq ppppp ooooo cppacku.b =crop,crqp,crpp (p0_1) -(dni cppacku_b_P0_P1 "cppacku.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cppacku.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacku_b" pc crqp crpp)) ) - () - ) - -; 00101101 10100 qqqqq ppppp ooooo cppack.b =crop,crqp,crpp (p0_1) -(dni cppack_b_P0_P1 "cppack.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST)) - "cppack.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppack_b" pc crqp crpp)) ) - () - ) - -; 00101111 10100 qqqqq ppppp ooooo cppack.h =crop,crqp,crpp (p0_1) -(dni cppack_h_P0_P1 "cppack.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST)) - "cppack.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppack_h" pc crqp crpp)) ) - () - ) - -; 00110000 10100 qqqqq ppppp ooooo cpmaxu3.b =crop,crqp,crpp (p0_1) -(dni cpmaxu3_b_P0_P1 "cpmaxu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmaxu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x30) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmaxu3_b" pc crqp crpp)) ) - () - ) - -; 00110001 10100 qqqqq ppppp ooooo cpmax3.b =crop,crqp,crpp (p0_1) -(dni cpmax3_b_P0_P1 "cpmax3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmax3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x31) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_b" pc crqp crpp)) ) - () - ) - -; 00110011 10100 qqqqq ppppp ooooo cpmax3.h =crop,crqp,crpp (p0_1) -(dni cpmax3_h_P0_P1 "cpmax3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmax3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x33) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_h" pc crqp crpp)) ) - () - ) - -; 00110100 10100 qqqqq ppppp ooooo cpmaxu3.w =crop,crqp,crpp (p0_1) -(dni cpmaxu3_w_P0_P1 "cpmaxu3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmaxu3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x34) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmaxu3_w" pc crqp crpp)) ) - () - ) - -; 00110101 10100 qqqqq ppppp ooooo cpmax3.w =crop,crqp,crpp (p0_1) -(dni cpmax3_w_P0_P1 "cpmax3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmax3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x35) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_w" pc crqp crpp)) ) - () - ) - -; 00111000 10100 qqqqq ppppp ooooo cpminu3.b =crop,crqp,crpp (p0_1) -(dni cpminu3_b_P0_P1 "cpminu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpminu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x38) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpminu3_b" pc crqp crpp)) ) - () - ) - -; 00111001 10100 qqqqq ppppp ooooo cpmin3.b =crop,crqp,crpp (p0_1) -(dni cpmin3_b_P0_P1 "cpmin3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmin3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x39) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_b" pc crqp crpp)) ) - () - ) - -; 00111011 10100 qqqqq ppppp ooooo cpmin3.h =crop,crqp,crpp (p0_1) -(dni cpmin3_h_P0_P1 "cpmin3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmin3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_h" pc crqp crpp)) ) - () - ) - -; 00111100 10100 qqqqq ppppp ooooo cpminu3.w =crop,crqp,crpp (p0_1) -(dni cpminu3_w_P0_P1 "cpminu3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpminu3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpminu3_w" pc crqp crpp)) ) - () - ) - -; 00111101 10100 qqqqq ppppp ooooo cpmin3.w =crop,crqp,crpp (p0_1) -(dni cpmin3_w_P0_P1 "cpmin3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmin3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_w" pc crqp crpp)) ) - () - ) - -; 01000000 10100 qqqqq ppppp ooooo cpsrl3.b =crop,crqp,crpp (p0_1) -(dni cpsrl3_b_P0_P1 "cpsrl3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrl3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x40) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_b" pc crqp crpp)) ) - () - ) - -; 01000001 10100 qqqqq ppppp ooooo cpssrl3.b =crop,crqp,crpp (p0_1) -(dni cpssrl3_b_P0_P1 "cpssrl3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssrl3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x41) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_b" pc crqp crpp)) ) - () - ) - -; 01000010 10100 qqqqq ppppp ooooo cpsrl3.h =crop,crqp,crpp (p0_1) -(dni cpsrl3_h_P0_P1 "cpsrl3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrl3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x42) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_h" pc crqp crpp)) ) - () - ) - -; 01000011 10100 qqqqq ppppp ooooo cpssrl3.h =crop,crqp,crpp (p0_1) -(dni cpssrl3_h_P0_P1 "cpssrl3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssrl3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x43) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_h" pc crqp crpp)) ) - () - ) - -; 01000100 10100 qqqqq ppppp ooooo cpsrl3.w =crop,crqp,crpp (p0_1) -(dni cpsrl3_w_P0_P1 "cpsrl3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrl3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x44) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_w" pc crqp crpp)) ) - () - ) - -; 01000101 10100 qqqqq ppppp ooooo cpssrl3.w =crop,crqp,crpp (p0_1) -(dni cpssrl3_w_P0_P1 "cpssrl3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssrl3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x45) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_w" pc crqp crpp)) ) - () - ) - -; 01000110 10100 qqqqq ppppp ooooo cdsrl3 =crop,crqp,crpp (p0_1) -(dni cdsrl3_P0_P1 "cdsrl3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrl3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x46) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrl3" pc crqp crpp)) ) - () - ) - -; 01001000 10100 qqqqq ppppp ooooo cpsra3.b =crop,crqp,crpp (p0_1) -(dni cpsra3_b_P0_P1 "cpsra3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsra3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x48) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_b" pc crqp crpp)) ) - () - ) - -; 01001001 10100 qqqqq ppppp ooooo cpssra3.b =crop,crqp,crpp (p0_1) -(dni cpssra3_b_P0_P1 "cpssra3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssra3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x49) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_b" pc crqp crpp)) ) - () - ) - -; 01001010 10100 qqqqq ppppp ooooo cpsra3.h =crop,crqp,crpp (p0_1) -(dni cpsra3_h_P0_P1 "cpsra3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsra3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_h" pc crqp crpp)) ) - () - ) - -; 01001011 10100 qqqqq ppppp ooooo cpssra3.h =crop,crqp,crpp (p0_1) -(dni cpssra3_h_P0_P1 "cpssra3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssra3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_h" pc crqp crpp)) ) - () - ) - -; 01001100 10100 qqqqq ppppp ooooo cpsra3.w =crop,crqp,crpp (p0_1) -(dni cpsra3_w_P0_P1 "cpsra3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsra3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_w" pc crqp crpp)) ) - () - ) - -; 01001101 10100 qqqqq ppppp ooooo cpssra3.w =crop,crqp,crpp (p0_1) -(dni cpssra3_w_P0_P1 "cpssra3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssra3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_w" pc crqp crpp)) ) - () - ) - -; 01001110 10100 qqqqq ppppp ooooo cdsra3 =crop,crqp,crpp (p0_1) -(dni cdsra3_P0_P1 "cdsra3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsra3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsra3" pc crqp crpp)) ) - () - ) - -; 01010000 10100 qqqqq ppppp ooooo cpsll3.b =crop,crqp,crpp (p0_1) -(dni cpsll3_b_P0_P1 "cpsll3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsll3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x50) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_b" pc crqp crpp)) ) - () - ) - -; 01010001 10100 qqqqq ppppp ooooo cpssll3.b =crop,crqp,crpp (p0_1) -(dni cpssll3_b_P0_P1 "cpssll3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssll3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x51) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_b" pc crqp crpp)) ) - () - ) - -; 01010010 10100 qqqqq ppppp ooooo cpsll3.h =crop,crqp,crpp (p0_1) -(dni cpsll3_h_P0_P1 "cpsll3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsll3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x52) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_h" pc crqp crpp)) ) - () - ) - -; 01010011 10100 qqqqq ppppp ooooo cpssll3.h =crop,crqp,crpp (p0_1) -(dni cpssll3_h_P0_P1 "cpssll3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssll3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x53) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_h" pc crqp crpp)) ) - () - ) - -; 01010100 10100 qqqqq ppppp ooooo cpsll3.w =crop,crqp,crpp (p0_1) -(dni cpsll3_w_P0_P1 "cpsll3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsll3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x54) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_w" pc crqp crpp)) ) - () - ) - -; 01010101 10100 qqqqq ppppp ooooo cpssll3.w =crop,crqp,crpp (p0_1) -(dni cpssll3_w_P0_P1 "cpssll3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssll3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x55) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_w" pc crqp crpp)) ) - () - ) - -; 01010110 10100 qqqqq ppppp ooooo cdsll3 =crop,crqp,crpp (p0_1) -(dni cdsll3_P0_P1 "cdsll3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsll3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x56) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsll3" pc crqp crpp)) ) - () - ) - -; 01011010 10100 qqqqq ppppp ooooo cpsla3.h =crop,crqp,crpp (p0_1) -(dni cpsla3_h_P0_P1 "cpsla3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsla3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsla3_h" pc crqp crpp)) ) - () - ) - -; 01011100 10100 qqqqq ppppp ooooo cpsla3.w =crop,crqp,crpp (p0_1) -(dni cpsla3_w_P0_P1 "cpsla3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsla3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsla3_w" pc crqp crpp)) ) - () - ) - -; xxxxxiii 10101 qqqqq 00000 ooooo cpsrli3.b =crop,crqp,imm3p5 (p0_1) -(dni cpsrli3_b_P0_P1 "cpsrli3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrli3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 00001 ooooo cpsrli3.h =crop,crqp,imm4p4 (p0_1) -(dni cpsrli3_h_P0_P1 "cpsrli3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrli3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 00010 ooooo cpsrli3.w =crop,crqp,imm5p3 (p0_1) -(dni cpsrli3_w_P0_P1 "cpsrli3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrli3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 00011 ooooo cdsrli3 =crop,crqp,imm6p2 (p0_1) -(dni cdsrli3_P0_P1 "cdsrli3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrli3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrli3" pc crqp imm6p2)) ) - () - ) - -; xxxxxiii 10101 qqqqq 00100 ooooo cpsrai3.b =crop,crqp,imm3p5 (p0_1) -(dni cpsrai3_b_P0_P1 "cpsrai3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrai3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 00101 ooooo cpsrai3.h =crop,crqp,imm4p4 (p0_1) -(dni cpsrai3_h_P0_P1 "cpsrai3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrai3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 00110 ooooo cpsrai3.w =crop,crqp,imm5p3 (p0_1) -(dni cpsrai3_w_P0_P1 "cpsrai3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrai3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 00111 ooooo cdsrai3 =crop,crqp,imm6p2 (p0_1) -(dni cdsrai3_P0_P1 "cdsrai3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrai3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrai3" pc crqp imm6p2)) ) - () - ) - -; xxxxxiii 10101 qqqqq 01000 ooooo cpslli3.b =crop,crqp,imm3p5 (p0_1) -(dni cpslli3_b_P0_P1 "cpslli3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpslli3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 01001 ooooo cpslli3.h =crop,crqp,imm4p4 (p0_1) -(dni cpslli3_h_P0_P1 "cpslli3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpslli3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 01010 ooooo cpslli3.w =crop,crqp,imm5p3 (p0_1) -(dni cpslli3_w_P0_P1 "cpslli3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpslli3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 01011 ooooo cdslli3 =crop,crqp,imm6p2 (p0_1) -(dni cdslli3_P0_P1 "cdslli3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdslli3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdslli3" pc crqp imm6p2)) ) - () - ) - -; xxxxiiii 10101 qqqqq 01101 ooooo cpslai3.h =crop,crqp,imm4p4 (p0_1) -(dni cpslai3_h_P0_P1 "cpslai3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpslai3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslai3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 01110 ooooo cpslai3.w =crop,crqp,imm5p3 (p0_1) -(dni cpslai3_w_P0_P1 "cpslai3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpslai3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslai3_w" pc crqp imm5p3)) ) - () - ) - -; xxxiiiii 10101 qqqqq 10000 ooooo cpclipiu3.w =crop,crqp,imm5p3 (p0_1) -(dni cpclipiu3_w_P0_P1 "cpclipiu3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipiu3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpclipiu3_w" pc crqp imm5p3)) ) - () - ) - -; xxxiiiii 10101 qqqqq 10001 ooooo cpclipi3.w =crop,crqp,imm5p3 (p0_1) -(dni cpclipi3_w_P0_P1 "cpclipi3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipi3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpclipi3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 10010 ooooo cdclipiu3 =crop,crqp,imm6p2 (p0_1) -(dni cdclipiu3_P0_P1 "cdclipiu3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipiu3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdclipiu3" pc crqp imm6p2)) ) - () - ) - -; xxiiiiii 10101 qqqqq 10011 ooooo cdclipi3 =crop,crqp,imm6p2 (p0_1) -(dni cdclipi3_P0_P1 "cdclipi3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipi3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdclipi3" pc crqp imm6p2)) ) - () - ) - -; iiiiiiii 10110 qqqqq 01iii iiiii cpmovi.h =crqp,simm16p0 (p0_i) -(dni cpmovi_h_P0_P1 "cpmovi.h $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmovi.h $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_h16" pc simm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 00iii iiiii cpmoviu.w =crqp,imm16p0 (p0_i) -(dni cpmoviu_w_P0_P1 "cpmoviu.w $crqp,imm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST)) - "cpmoviu.w $crqp,$imm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x0) imm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmoviu_w16" pc imm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 01iii iiiii cpmovi.w =crqp,simm16p0 (p0_i) -(dni cpmovi_w_P0_P1 "cpmovi.w $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmovi.w $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_w16" pc simm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 10iii iiiii cdmoviu =crqp,imm16p0 (p0_i) -(dni cdmoviu_P0_P1 "cdmoviu $crqp,imm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmoviu $crqp,$imm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x2) imm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cdmoviu16" pc imm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 11iii iiiii cdmovi =crqp,simm16p0 (p0_i) -(dni cdmovi_P0_P1 "cdmovi $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmovi $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x3) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cdmovi16" pc simm16p0)) ) - () - ) - -; 00000000 00000 00000 00000 00000 c1nop (p0_1) -(dni c1nop_P1 "c1nop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "c1nop")) - "c1nop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_c1nop" pc) ) - () - ) - -; 00000000 10110 qqqqq 00iii iiiii cpmovi.b =crqp,simm8p20 (p0_i) -(dni cpmovi_b_P0S_P1 "cpmovi.b $crqp,simm8p20 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmovi.b $crqp,$simm8p20" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x0) imm8p20(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_b" pc simm8p20)) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1) -(dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00001 cpadda1.b crqp,crpp (p0_1) -(dni cpadda1_b_P1 "cpadda1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE) - "cpadda1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00010 cpaddua1.h crqp,crpp (p0_1) -(dni cpaddua1_h_P1 "cpaddua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaddua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00011 cpaddla1.h crqp,crpp (p0_1) -(dni cpaddla1_h_P1 "cpaddla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpaddla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00100 cpaddaca1u.b crqp,crpp (p0_1) -(dni cpaddaca1u_b_P1 "cpaddaca1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00101 cpaddaca1.b crqp,crpp (p0_1) -(dni cpaddaca1_b_P1 "cpaddaca1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00110 cpaddacua1.h crqp,crpp (p0_1) -(dni cpaddacua1_h_P1 "cpaddacua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00111 cpaddacla1.h crqp,crpp (p0_1) -(dni cpaddacla1_h_P1 "cpaddacla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01000 cpsuba1u.b crqp,crpp (p0_1) -(dni cpsuba1u_b_P1 "cpsuba1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01001 cpsuba1.b crqp,crpp (p0_1) -(dni cpsuba1_b_P1 "cpsuba1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE) - "cpsuba1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01010 cpsubua1.h crqp,crpp (p0_1) -(dni cpsubua1_h_P1 "cpsubua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsubua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01011 cpsubla1.h crqp,crpp (p0_1) -(dni cpsubla1_h_P1 "cpsubla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsubla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01100 cpsubaca1u.b crqp,crpp (p0_1) -(dni cpsubaca1u_b_P1 "cpsubaca1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01101 cpsubaca1.b crqp,crpp (p0_1) -(dni cpsubaca1_b_P1 "cpsubaca1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01110 cpsubacua1.h crqp,crpp (p0_1) -(dni cpsubacua1_h_P1 "cpsubacua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01111 cpsubacla1.h crqp,crpp (p0_1) -(dni cpsubacla1_h_P1 "cpsubacla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10000 cpabsa1u.b crqp,crpp (p0_1) -(dni cpabsa1u_b_P1 "cpabsa1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10001 cpabsa1.b crqp,crpp (p0_1) -(dni cpabsa1_b_P1 "cpabsa1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE) - "cpabsa1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10010 cpabsua1.h crqp,crpp (p0_1) -(dni cpabsua1_h_P1 "cpabsua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE) - "cpabsua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10011 cpabsla1.h crqp,crpp (p0_1) -(dni cpabsla1_h_P1 "cpabsla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE) - "cpabsla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpabsla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10100 cpsada1u.b crqp,crpp (p0_1) -(dni cpsada1u_b_P1 "cpsada1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10101 cpsada1.b crqp,crpp (p0_1) -(dni cpsada1_b_P1 "cpsada1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE) - "cpsada1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10110 cpsadua1.h crqp,crpp (p0_1) -(dni cpsadua1_h_P1 "cpsadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10111 cpsadla1.h crqp,crpp (p0_1) -(dni cpsadla1_h_P1 "cpsadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11011 cpseta1.h crqp,crpp (p0_1) -(dni cpseta1_h_P1 "cpseta1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE) - "cpseta1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpseta1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11100 cpsetua1.w crqp,crpp (p0_1) -(dni cpsetua1_w_P1 "cpsetua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE) - "cpsetua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsetua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11101 cpsetla1.w crqp,crpp (p0_1) -(dni cpsetla1_w_P1 "cpsetla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE) - "cpsetla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsetla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11001 00000 00001 ooooo cpmova1.b =crop (p0_1) -(dni cpmova1_b_P1 "cpmova1.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova1.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmova1_b" pc)) ) - () - ) - -; 00000000 11001 00000 00010 ooooo cpmovua1.h =crop (p0_1) -(dni cpmovua1_h_P1 "cpmovua1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovua1_h" pc)) ) - () - ) - -; 00000000 11001 00000 00011 ooooo cpmovla1.h =crop (p0_1) -(dni cpmovla1_h_P1 "cpmovla1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovla1_h" pc)) ) - () - ) - -; 00000000 11001 00000 00100 ooooo cpmovuua1.w =crop (p0_1) -(dni cpmovuua1_w_P1 "cpmovuua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovuua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00101 ooooo cpmovula1.w =crop (p0_1) -(dni cpmovula1_w_P1 "cpmovula1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovula1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00110 ooooo cpmovlua1.w =crop (p0_1) -(dni cpmovlua1_w_P1 "cpmovlua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00111 ooooo cpmovlla1.w =crop (p0_1) -(dni cpmovlla1_w_P1 "cpmovlla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01000 ooooo cppacka1u.b =crop (p0_1) -(dni cppacka1u_b_P1 "cppacka1u.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka1u.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka1u_b" pc)) ) - () - ) - -; 00000000 11001 00000 01001 ooooo cppacka1.b =crop (p0_1) -(dni cppacka1_b_P1 "cppacka1.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka1.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka1_b" pc)) ) - () - ) - -; 00000000 11001 00000 01010 ooooo cppackua1.h =crop (p0_1) -(dni cppackua1_h_P1 "cppackua1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua1_h" pc)) ) - () - ) - -; 00000000 11001 00000 01011 ooooo cppackla1.h =crop (p0_1) -(dni cppackla1_h_P1 "cppackla1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla1_h" pc)) ) - () - ) - -; 00000000 11001 00000 01100 ooooo cppackua1.w =crop (p0_1) -(dni cppackua1_w_P1 "cppackua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01101 ooooo cppackla1.w =crop (p0_1) -(dni cppackla1_w_P1 "cppackla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01110 ooooo cpmovhua1.w =crop (p0_1) -(dni cpmovhua1_w_P1 "cpmovhua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01111 ooooo cpmovhla1.w =crop (p0_1) -(dni cpmovhla1_w_P1 "cpmovhla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 10000 00000 cpacsuma1 (p0_1) -(dni cpacsuma1_P1 "cpacsuma1 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacsuma1") VOLATILE) - "cpacsuma1" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpacsuma1" pc) ) - () - ) - -; 00000000 11001 00000 10001 00000 cpaccpa1 (p0_1) -(dni cpaccpa1_P1 "cpaccpa1 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaccpa1") VOLATILE) - "cpaccpa1" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaccpa1" pc) ) - () - ) - -; 00000000 11001 00000 10010 00000 cpacswp (p0_1) -(dni cpacswp_P1 "cpacswp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacswp") VOLATILE) - "cpacswp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x12) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpacswp" pc) ) - () - ) - -; 00000000 11001 qqqqq 11000 00000 cpsrla1 crqp (p0_1) -(dni cpsrla1_P1 "cpsrla1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrla1") VOLATILE) - "cpsrla1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrla1" pc crqp) ) - () - ) - -; 00000000 11001 qqqqq 11001 00000 cpsraa1 crqp (p0_1) -(dni cpsraa1_P1 "cpsraa1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraa1") VOLATILE) - "cpsraa1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraa1" pc crqp) ) - () - ) - -; 00000000 11001 qqqqq 11010 00000 cpslla1 crqp (p0_1) -(dni cpslla1_P1 "cpslla1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpslla1") VOLATILE) - "cpslla1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpslla1" pc crqp) ) - () - ) - -; 00000000 11001 00000 11100 iiiii cpsrlia1 imm5p23 (p0_1) -(dni cpsrlia1_1_p1 "cpsrlia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrlia1") VOLATILE) - "cpsrlia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrlia1" pc imm5p23) ) - () - ) - -; 00000000 11001 00000 11101 iiiii cpsraia1 imm5p23 (p0_1) -(dni cpsraia1_1_p1 "cpsraia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraia1") VOLATILE) - "cpsraia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraia1" pc imm5p23) ) - () - ) - -; 00000000 11001 00000 11110 iiiii cpsllia1 imm5p23 (p0_1) -(dni cpsllia1_1_p1 "cpsllia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsllia1") VOLATILE) - "cpsllia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsllia1" pc imm5p23) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00000 cpfmulia1s0u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s0u_b_P1 "cpfmulia1s0u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1s0u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s0u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00001 cpfmulia1s0.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s0_b_P1 "cpfmulia1s0.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1s0.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s0_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00010 cpfmuliua1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmuliua1s0_h_P1 "cpfmuliua1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00011 cpfmulila1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmulila1s0_h_P1 "cpfmulila1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00100 cpfmadia1s0u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s0u_b_P1 "cpfmadia1s0u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1s0u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s0u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00101 cpfmadia1s0.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s0_b_P1 "cpfmadia1s0.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1s0.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s0_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00110 cpfmadiua1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadiua1s0_h_P1 "cpfmadiua1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00111 cpfmadila1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadila1s0_h_P1 "cpfmadila1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01000 cpfmulia1s1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s1u_b_P1 "cpfmulia1s1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1s1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01001 cpfmulia1s1.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s1_b_P1 "cpfmulia1s1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1s1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01010 cpfmuliua1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmuliua1s1_h_P1 "cpfmuliua1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01011 cpfmulila1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmulila1s1_h_P1 "cpfmulila1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01100 cpfmadia1s1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s1u_b_P1 "cpfmadia1s1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1s1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01101 cpfmadia1s1.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s1_b_P1 "cpfmadia1s1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1s1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01110 cpfmadiua1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadiua1s1_h_P1 "cpfmadiua1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01111 cpfmadila1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadila1s1_h_P1 "cpfmadila1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10000 cpamulia1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpamulia1u_b_P1 "cpamulia1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpamulia1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamulia1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10001 cpamulia1.b crqp,crpp,simm8p0 (p0_1) -(dni cpamulia1_b_P1 "cpamulia1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI) VOLATILE) - "cpamulia1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamulia1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10010 cpamuliua1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamuliua1_h_P1 "cpamuliua1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI) VOLATILE) - "cpamuliua1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamuliua1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10011 cpamulila1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamulila1_h_P1 "cpamulila1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI) VOLATILE) - "cpamulila1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpamulila1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10100 cpamadia1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpamadia1u_b_P1 "cpamadia1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpamadia1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadia1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10101 cpamadia1.b crqp,crpp,simm8p0 (p0_1) -(dni cpamadia1_b_P1 "cpamadia1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI) VOLATILE) - "cpamadia1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadia1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10110 cpamadiua1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamadiua1_h_P1 "cpamadiua1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI) VOLATILE) - "cpamadiua1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadiua1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10111 cpamadila1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamadila1_h_P1 "cpamadila1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI) VOLATILE) - "cpamadila1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadila1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 00 III cpfmulia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulia1u_b_P1 "cpfmulia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1u_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 01 III cpfmulia1.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulia1_b_P1 "cpfmulia1.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 10 III cpfmuliua1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmuliua1_h_P1 "cpfmuliua1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 11 III cpfmulila1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulila1_h_P1 "cpfmulila1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 00 III cpfmadia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadia1u_b_P1 "cpfmadia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1u_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 01 III cpfmadia1.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadia1_b_P1 "cpfmadia1.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 10 III cpfmadiua1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadiua1_h_P1 "cpfmadiua1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 11 III cpfmadila1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadila1_h_P1 "cpfmadila1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00000 cpssqa1u.b crqp,crpp (p0_1) -(dni cpssqa1u_b_P1 "cpssqa1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssqa1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00001 cpssqa1.b crqp,crpp (p0_1) -(dni cpssqa1_b_P1 "cpssqa1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE) - "cpssqa1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00100 cpssda1u.b crqp,crpp (p0_1) -(dni cpssda1u_b_P1 "cpssda1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssda1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssda1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00101 cpssda1.b crqp,crpp (p0_1) -(dni cpssda1_b_P1 "cpssda1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE) - "cpssda1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssda1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01000 cpmula1u.b crqp,crpp (p0_1) -(dni cpmula1u_b_P1 "cpmula1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmula1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01001 cpmula1.b crqp,crpp (p0_1) -(dni cpmula1_b_P1 "cpmula1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE) - "cpmula1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01010 cpmulua1.h crqp,crpp (p0_1) -(dni cpmulua1_h_P1 "cpmulua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01011 cpmulla1.h crqp,crpp (p0_1) -(dni cpmulla1_h_P1 "cpmulla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01100 cpmulua1u.w crqp,crpp (p0_1) -(dni cpmulua1u_w_P1 "cpmulua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01101 cpmulla1u.w crqp,crpp (p0_1) -(dni cpmulla1u_w_P1 "cpmulla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01110 cpmulua1.w crqp,crpp (p0_1) -(dni cpmulua1_w_P1 "cpmulua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01111 cpmulla1.w crqp,crpp (p0_1) -(dni cpmulla1_w_P1 "cpmulla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10000 cpmada1u.b crqp,crpp (p0_1) -(dni cpmada1u_b_P1 "cpmada1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmada1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10001 cpmada1.b crqp,crpp (p0_1) -(dni cpmada1_b_P1 "cpmada1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE) - "cpmada1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10010 cpmadua1.h crqp,crpp (p0_1) -(dni cpmadua1_h_P1 "cpmadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpmadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10011 cpmadla1.h crqp,crpp (p0_1) -(dni cpmadla1_h_P1 "cpmadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpmadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10100 cpmadua1u.w crqp,crpp (p0_1) -(dni cpmadua1u_w_P1 "cpmadua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10101 cpmadla1u.w crqp,crpp (p0_1) -(dni cpmadla1u_w_P1 "cpmadla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10110 cpmadua1.w crqp,crpp (p0_1) -(dni cpmadua1_w_P1 "cpmadua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpmadua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10111 cpmadla1.w crqp,crpp (p0_1) -(dni cpmadla1_w_P1 "cpmadla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpmadla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11010 cpmsbua1.h crqp,crpp (p0_1) -(dni cpmsbua1_h_P1 "cpmsbua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11011 cpmsbla1.h crqp,crpp (p0_1) -(dni cpmsbla1_h_P1 "cpmsbla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11100 cpmsbua1u.w crqp,crpp (p0_1) -(dni cpmsbua1u_w_P1 "cpmsbua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11101 cpmsbla1u.w crqp,crpp (p0_1) -(dni cpmsbla1u_w_P1 "cpmsbla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11110 cpmsbua1.w crqp,crpp (p0_1) -(dni cpmsbua1_w_P1 "cpmsbua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11111 cpmsbla1.w crqp,crpp (p0_1) -(dni cpmsbla1_w_P1 "cpmsbla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10010 cpsmadua1.h crqp,crpp (p0_1) -(dni cpsmadua1_h_P1 "cpsmadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10011 cpsmadla1.h crqp,crpp (p0_1) -(dni cpsmadla1_h_P1 "cpsmadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10110 cpsmadua1.w crqp,crpp (p0_1) -(dni cpsmadua1_w_P1 "cpsmadua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10111 cpsmadla1.w crqp,crpp (p0_1) -(dni cpsmadla1_w_P1 "cpsmadla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11010 cpsmsbua1.h crqp,crpp (p0_1) -(dni cpsmsbua1_h_P1 "cpsmsbua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11011 cpsmsbla1.h crqp,crpp (p0_1) -(dni cpsmsbla1_h_P1 "cpsmsbla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11110 cpsmsbua1.w crqp,crpp (p0_1) -(dni cpsmsbua1_w_P1 "cpsmsbua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11111 cpsmsbla1.w crqp,crpp (p0_1) -(dni cpsmsbla1_w_P1 "cpsmsbla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_w" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01010 cpmulslua1.h crqp,crpp (p0_1) -(dni cpmulslua1_h_P1 "cpmulslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_h" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01011 cpmulslla1.h crqp,crpp (p0_1) -(dni cpmulslla1_h_P1 "cpmulslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_h" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01110 cpmulslua1.w crqp,crpp (p0_1) -(dni cpmulslua1_w_P1 "cpmulslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_w" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01111 cpmulslla1.w crqp,crpp (p0_1) -(dni cpmulslla1_w_P1 "cpmulslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10010 cpsmadslua1.h crqp,crpp (p0_1) -(dni cpsmadslua1_h_P1 "cpsmadslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10011 cpsmadslla1.h crqp,crpp (p0_1) -(dni cpsmadslla1_h_P1 "cpsmadslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10110 cpsmadslua1.w crqp,crpp (p0_1) -(dni cpsmadslua1_w_P1 "cpsmadslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10111 cpsmadslla1.w crqp,crpp (p0_1) -(dni cpsmadslla1_w_P1 "cpsmadslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11010 cpsmsbslua1.h crqp,crpp (p0_1) -(dni cpsmsbslua1_h_P1 "cpsmsbslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11011 cpsmsbslla1.h crqp,crpp (p0_1) -(dni cpsmsbslla1_h_P1 "cpsmsbslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11110 cpsmsbslua1.w crqp,crpp (p0_1) -(dni cpsmsbslua1_w_P1 "cpsmsbslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11111 cpsmsbslla1.w crqp,crpp (p0_1) -(dni cpsmsbslla1_w_P1 "cpsmsbslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_w" pc crqp crpp) ) - () - ) - diff --git a/cpu/mep-rhcop.cpu b/cpu/mep-rhcop.cpu deleted file mode 100644 index 421561c..0000000 --- a/cpu/mep-rhcop.cpu +++ /dev/null @@ -1,321 +0,0 @@ -;; This coprocessor definition is being used to verify vliw mode behaviour. -;; This is a mock-up done by Red Hat and is in no way supposed to represent -;; a real coprocessor. The hardware is defined in mep-core.cpu. - -; Coprocessor registers -(define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) - -(define-hardware - (name h-cr64-rh-1) - (comment "64-bit coprocessor registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register DI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index newval)) - (get (index) (c-call DI "h_cr64_get" index)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) -) - -(define-hardware - (name h-cr-rh-1) - (comment "32-bit coprocessor registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 32))) -) - -(define-hardware - (name h-ccr-rh-1) - (comment "Coprocessor control registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call DI "h_ccr_get" index)) - (indices keyword "" (.map -ccr-reg-pair (.iota 64))) -) - -; ifields For 16-bit insns -(dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4) -(dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5) -(dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5) -(dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2) -(dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3) -(dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4) - -; ifields For 32-bit insns (some of the above are used too) -; Notes: -; -; f-alone: A value of 0111 means that the insn can run alone in -; one of the vliw modes. -; -; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit -; f-seg32-a: insns to be defined. -(dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3) -(dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4) -(dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3) -(dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8) -(dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5) - -; ifields for 48-bit insns -; Note: Part of f-uu12 can be broken off later to enumerate -; any 48-bit insns that may be added. -(dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12) -(dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16) -(dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16) - -; ifields for 64-bit insns -(dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8) -(dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8) -(dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8) -(dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16) -(dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5) -(dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4) -(dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23) -(dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4) -(dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4) -(dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24) - - -; Operands for 16-bit insns -(dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn) -(dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm) -(dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm) - -; Additional operands for 32-bit insns -(dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8) - -; Operands for 48-bit insns -(dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a) -(dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b) - -; Additional operands for 64-bit insns -(dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c) -(dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64) -(dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64) -(dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64) -(dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64) -(dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23) -(dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24) - - - -; 16- and 32-bit nops can be defined as normal instructions without -; any problems. nops take no operands, so nops longer than 32 -; bits cannot be defined as normal insns since that would result in -; decodable bits beyond cgen's 32-bit boundary. As a result, we -; have to use macros and other real insns to create 48- and 64-bit nops. -; -; In addition, since the names of the nops that will be created as part -; of future insn sets are not known at this time, the assembler needs a -; fixed set of nop names that it can use for automatic nop insertion. -; The idea is that no matter what those insns are called, we don't want -; to have to change the C code in the assemblers vliw grouping validation -; and nop insertion routines. We therefore have to create macros for -; all nops to map the macro names which are known to the assembler to the -; names of the real nop insns. -; -; These emitted insns in these macros will need to be modified when -; new nops are defined in new coprocessor insn sets. - -; A real 16-bit nop insn exists -(dnmi cpnop16 "cpnop16" - ((ISA ext_cop1_16)) - "cpnop16" - (emit cp16nop) -) - -; A real 32-bit nop insn exists -(dnmi cpnop32 "cpnop32" - ((ISA ext_cop1_32)) - "cpnop32" - (emit cp32nop) -) - -; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop. -(dnmi cpnop48 "cpnop48" - ((ISA ext_cop1_48)) - "cpnop48" - (emit cpf1nop (code16a 0) (code16b 0)) -) - -; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop. -(dnmi cpnop64 "cpnop64" - ((ISA ext_cop1_64)) - "cpnop64" - (emit cpf3nop (code16b 0) (code16c 0)) -) - - -(define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16)) -(define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32)) -(define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48)) -(define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64)) - -; 16-Bit Insns -(dncp116i movcp16 "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16 $cpcrn,$cpcrm" - (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm) - (set cpcrn cpcrm) - () -) - -(dncp116i movcp16a "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16a $cpcrn,$cprm" - (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm) - (set cpcrn (zext DI cprm)) - () -) - -(dncp116i movcp16b "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16b $cprm,$cpcrn" - (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm) - (set cprm (subword SI cpcrn 1)) - () -) - -(dncp116i cp16nop "16-bit coprocessor nop" - (VLIW64_NO_MATCHING_NOP) - "cp16nop" - (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0)) - (unimp "cp16nop") - () -) - -; 32-Bit Insns -(dncp132i cp32nop "32-bit coprocessor nop" - (VLIW64_NO_MATCHING_NOP) - "cp32nop" - (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) - (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0)) - (unimp "cpnop32") - () -) - -(dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests " - (VLIW64_NO_MATCHING_NOP) - "cpf2 $code8" - (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) - (f-cpcrm-32 0) (f-seg32-a 1) code8) - (unimp "cpf2") - () -) - -; 48-Bit Insns -(dncp148i cpf1 "48-bit coprocessor helper insn" - () - "cpf1 $code16a,$code16b" - (+ (f-cphigh4 4) (f-uu12 0) code16a code16b) - (sequence ((HI result)) - (if (eq code16a 0) - (set pc (c-call USI "cop_exception" pc)) - ; Set branch condition flags to value of code16a[0:3] - ; Branch condition flags do not exist yet. - (nop) - ) - ) - () -) - -(dncp148i cpf1nop "48-bit coprocessor nop insn" - () - "cpf1nop $code16a,$code16b" - (+ (f-cphigh4 5) (f-uu12 0) code16a code16b) - (sequence ((HI result)) - (set result (add code16a code16b)) - ) - () -) - -; 64-Bit Insns -(dncp164i cpf3 "64-bit coprocessor helper insn" - () - "cpf3 $code16b,$code16c" - (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 0) code16b code16c) - (sequence ((HI result)) - (set result (add code16b code16c)) - ) - () -) - -(dncp164i cpf3nop "64-bit coprocessor helper insn" - () - "cpf3nop $code16b,$code16c" - (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 7) code16b code16c) - (sequence ((HI result)) - (set result (add code16b code16c)) - ) - () -) - -(dncp164i cmov64a "64-bit cmov" - () - "cmov64a $cpcrn64,$cpcrm64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 1) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrn64 (zext DI cpcrm64))) - () -) - -(dncp164i cmov64b "64-bit cmov" - () - "cmov64b $cpcrm64,$cpcrn64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 2) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrm64 (subword SI cpcrn64 1))) - () -) - -(dncp164i cmovh64a "64-bit cmovh" - () - "cmovh64a $cpcrn64,$cpcrm64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 3) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1))))) - () -) - -(dncp164i cmovh64b "64-bit cmovh" - () - "cmovh64b $cpcrm64,$cpcrn64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 4) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrm64 (subword SI cpcrn64 0))) - () -) - -(dncp164i cmovc64a "64-bit cmovc" - () - "cmovc64a $cpccrn64,$cpccrm64,$cpcode24" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 5) cpccrn64 cpccrm64 cpcode24) - (sequence ((SI dummy)) - (set dummy cpcode24) - (set cpccrn64 cpccrm64)) - () -) - -(dncp164i cmovc64b "64-bit cmovc" - () - "cmovc64b $cpccrm64,$cpccrn64,$cpcode24" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 6) cpccrn64 cpccrm64 cpcode24) - (sequence ((SI dummy)) - (set dummy cpcode24) - (set cpccrm64 cpccrn64)) - () -) - diff --git a/cpu/mep-sample-ucidsp.cpu b/cpu/mep-sample-ucidsp.cpu deleted file mode 100644 index 8c5d0ed..0000000 --- a/cpu/mep-sample-ucidsp.cpu +++ /dev/null @@ -1,103 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2001, 2002 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -; This file provides sample definitions for the UCI and DSP -; instructions. It is incorporated into the overall description by -; including it from a top-level file that includes all of the required -; option files. - -; UCI option. - -(define-pmacro mep-ext1-isa () (ISA ext_core1)) - - -; uci instructions for ELFextension test - -; uci.elfext.1 $simm16 -; 1111_IIII_0000_0010 0001_iiii_iiii_iiii -; simm16 = I[4:7]||i[20:31] - -; uci.elfext.2 $uimm16 -; 1111_IIII_0000_0010 0010_iiii_iiii_iiii -; uimm16 = I[4:7]||i[20:31] - -; define simm16 -(df f-uci_elfext_1-hi "uci_elfext_1 simm16 hi 4s7" (mep-ext1-isa) 4 4 INT #f #f) -(df f-uci_elfext_1-lo "uci_elfext_1 simm16 lo 20s31" (mep-ext1-isa) 20 12 UINT #f #f) -(define-multi-ifield - (name f-uci_elfext_1) - (comment "16-bits uci_elfext_ signed constant") - (attrs mep-ext1-isa) - (mode INT) - (subfields f-uci_elfext_1-hi f-uci_elfext_1-lo) - (insert (sequence () - (set (ifield f-uci_elfext_1-hi) (srl (ifield f-uci_elfext_1) 12)) - (set (ifield f-uci_elfext_1-lo) (and (ifield f-uci_elfext_1) #xfff)))) - (extract (set (ifield f-uci_elfext_1) - (or (sll (ifield f-uci_elfext_1-hi) 12) - (ifield f-uci_elfext_1-lo)))) - ) -(dpop uci_elfext_1simm16 "signed imm (16 bits)" (mep-ext1-isa) h-sint f-uci_elfext_1 "signed16") - -; define uimm16 -(df f-uci_elfext_2-hi "uci_elfext_2 uimm16 hi 4u7" (mep-ext1-isa) 4 4 UINT #f #f) -(df f-uci_elfext_2-lo "uci_elfext_2 uimm16 lo 20u31" (mep-ext1-isa) 20 12 UINT #f #f) -(define-multi-ifield - (name f-uci_elfext_2) - (comment "16-bits uci_elfext_ unsigned constant") - (attrs mep-ext1-isa) - (mode UINT) - (subfields f-uci_elfext_2-hi f-uci_elfext_2-lo) - (insert (sequence () - (set (ifield f-uci_elfext_2-hi) (srl (ifield f-uci_elfext_2) 12)) - (set (ifield f-uci_elfext_2-lo) (and (ifield f-uci_elfext_2) #xfff)))) - (extract (set (ifield f-uci_elfext_2) - (or (sll (ifield f-uci_elfext_2-hi) 12) - (ifield f-uci_elfext_2-lo)))) - ) -(dpop uci_elfext_2uimm16 "unsigned imm (16 bits)" (mep-ext1-isa) h-uint f-uci_elfext_2 "unsigned16") - -; define sub-opcode -(df f-uci_elfext-sub "sub-opcode for uci_elfext instructions" (mep-ext1-isa) 16 4 UINT #f #f) - - -; define instruction -(dni uci.elfext.1 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa) - "uci.elfext.1 $uci_elfext_1simm16" - (+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 1) uci_elfext_1simm16) - (c-call "check_option_uci" pc) - () - ) - -; define instruction -(dni uci.elfext.2 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa) - "uci.elfext.2 $uci_elfext_2uimm16" - (+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 2) uci_elfext_2uimm16) - (c-call "check_option_uci" pc) - () - ) - - - -;; some general samples -; UCI option. - -(dni uci "user defined instruction" (OPTIONAL_UCI_INSN mep-ext1-isa) - "uci $rn,$rm,$code16" - (+ MAJ_15 rn rm (f-sub4 2) code16) - (sequence () - (c-call "check_option_uci" pc) - (unimp "uci")) - ()) - -; DSP option. - -(dni dsp "dsp instruction" (OPTIONAL_DSP_INSN mep-ext1-isa) - "dsp $rn,$rm,$code16" - (+ MAJ_15 rn rm (f-sub4 0) code16) - (sequence () - (c-call "check_option_dsp" pc) - (set pc (c-call USI "dsp_exception" pc))) - ()) diff --git a/cpu/mep.cpu b/cpu/mep.cpu deleted file mode 100644 index 374e5b1..0000000 --- a/cpu/mep.cpu +++ /dev/null @@ -1 +0,0 @@ -(include "mep-default.cpu") diff --git a/cpu/mep.opc b/cpu/mep.opc deleted file mode 100644 index cd9888c..0000000 --- a/cpu/mep.opc +++ /dev/null @@ -1,1653 +0,0 @@ -/* MeP opcode support. -*- C -*- - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2010 Red Hat, Inc. - This file is part of CGEN. - This file is copyrighted with the GNU General Public License. - See file COPYING for details. */ - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 1 - -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, insn) 0 - -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -typedef struct -{ - char * name; - int config_enum; - unsigned cpu_flag; - int big_endian; - int vliw_bits; - CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; - CGEN_ATTR_VALUE_BITSET_TYPE core_isa; - unsigned int option_mask; -} mep_config_map_struct; - -extern mep_config_map_struct mep_config_map[]; -extern int mep_config_index; - -extern void init_mep_all_core_isas_mask (void); -extern void init_mep_all_cop_isas_mask (void); -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); - -#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) -#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) -#define MEP_OMASK (mep_config_map[mep_config_index].option_mask) -#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) -#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) -#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) -#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) -#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) -#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) -#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) -#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) -#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) - -/* begin-cop-ip-supported-defines */ -#define MEP_IVC2_SUPPORTED 1 -/* end-cop-ip-supported-defines */ - -extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); - -/* A mask for all ISAs executed by the core. */ -#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; - -#define MEP_INSN_CORE_P(insn) ( \ - init_mep_all_core_isas_mask (), \ - mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ -) - -/* A mask for all ISAs executed by a VLIW coprocessor. */ -#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; - -#define MEP_INSN_COP_P(insn) ( \ - init_mep_all_cop_isas_mask (), \ - mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ -) - -extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); -extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); - -/* -- asm.c */ - -#include "elf/mep.h" - -#define CGEN_VALIDATE_INSN_SUPPORTED -#define mep_cgen_insn_supported mep_cgen_insn_supported_asm - - const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); - const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); -static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; -static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); -static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; -static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); -static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); -static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); - -const char * -parse_csrn (CGEN_CPU_DESC cd, const char **strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - unsigned long value; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (!err) - return NULL; - - err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); - if (err) - return err; - *field = value; - return NULL; -} - -/* begin-cop-ip-parse-handlers */ -static const char * -parse_ivc2_cr (CGEN_CPU_DESC, - const char **, - CGEN_KEYWORD *, - long *) ATTRIBUTE_UNUSED; -static const char * -parse_ivc2_cr (CGEN_CPU_DESC cd, - const char **strp, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long *field) -{ - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); -} -static const char * -parse_ivc2_ccr (CGEN_CPU_DESC, - const char **, - CGEN_KEYWORD *, - long *) ATTRIBUTE_UNUSED; -static const char * -parse_ivc2_ccr (CGEN_CPU_DESC cd, - const char **strp, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long *field) -{ - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); -} -/* end-cop-ip-parse-handlers */ - -const char * -parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (err) - return err; - if (*field != 13) - return _("Only $tp or $13 allowed for this opcode"); - return NULL; -} - -const char * -parse_spreg (CGEN_CPU_DESC cd, const char ** strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (err) - return err; - if (*field != 15) - return _("Only $sp or $15 allowed for this opcode"); - return NULL; -} - -const char * -parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, - enum cgen_operand_type type, long *field) -{ - long lsbs = 0; - const char *err; - - switch (type) - { - case MEP_OPERAND_PCREL8A2: - case MEP_OPERAND_PCREL12A2: - case MEP_OPERAND_PCREL17A2: - case MEP_OPERAND_PCREL24A2: - err = cgen_parse_signed_integer (cd, strp, type, field); - break; - case MEP_OPERAND_PCABS24A2: - case MEP_OPERAND_UDISP7: - case MEP_OPERAND_UDISP7A2: - case MEP_OPERAND_UDISP7A4: - case MEP_OPERAND_UIMM7A4: - case MEP_OPERAND_ADDR24A4: - err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); - break; - default: - abort(); - } - if (err) - return err; - switch (type) - { - case MEP_OPERAND_UDISP7: - lsbs = 0; - break; - case MEP_OPERAND_PCREL8A2: - case MEP_OPERAND_PCREL12A2: - case MEP_OPERAND_PCREL17A2: - case MEP_OPERAND_PCREL24A2: - case MEP_OPERAND_PCABS24A2: - case MEP_OPERAND_UDISP7A2: - lsbs = *field & 1; - break; - case MEP_OPERAND_UDISP7A4: - case MEP_OPERAND_UIMM7A4: - case MEP_OPERAND_ADDR24A4: - lsbs = *field & 3; - break; - lsbs = *field & 7; - break; - default: - /* Safe assumption? */ - abort (); - } - if (lsbs) - return "Value is not aligned enough"; - return NULL; -} - -const char * -parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, - enum cgen_operand_type type, unsigned long *field) -{ - return parse_mep_align (cd, strp, type, (long *) field); -} - - -/* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed - constants in a signed context. */ - -static const char * -parse_signed16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - return parse_lo16 (cd, strp, opindex, valuep, 1); -} - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep, - long signedp) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - if (signedp) - *valuep = (long)(short) value; - else - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%hi(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (value + 0x8000) >> 16; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%uhi(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = value >> 16; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%sdaoff(", 8) == 0) - { - *strp += 8; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, - NULL, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - *strp += 7; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, - NULL, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return _("invalid %function() here"); - - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_unsigned16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); -} - -static const char * -parse_signed16_range (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value < -32768 || value > 32767) - return _("Immediate is out of range -32768 to 32767"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned16_range (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 65535) - return _("Immediate is out of range 0 to 65535"); - - *valuep = value; - return 0; -} - -/* A special case of parse_signed16 which accepts only the value zero. */ - -static const char * -parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ - - /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. - It will fail and cause ry to be listed as an undefined symbol in the - listing. */ - if (strncmp (*strp, "($", 2) == 0) - return "not zero"; /* any string will do -- will never be seen. */ - - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%hi(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%uhi(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%sdaoff(", 8) == 0) - { - *strp += 8; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - *strp += 7; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return "invalid %function() here"; - - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, - &result_type, &value); - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - - return errmsg; -} - -static const char * -parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, - enum cgen_operand_type opindex, unsigned long *valuep) -{ - const char *errmsg; - bfd_vma value; - - /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - int reloc; - *strp += 7; - switch (opindex) - { - case MEP_OPERAND_UDISP7: - reloc = BFD_RELOC_MEP_TPREL7; - break; - case MEP_OPERAND_UDISP7A2: - reloc = BFD_RELOC_MEP_TPREL7A2; - break; - case MEP_OPERAND_UDISP7A4: - reloc = BFD_RELOC_MEP_TPREL7A4; - break; - default: - /* Safe assumption? */ - abort (); - } - errmsg = cgen_parse_address (cd, strp, opindex, reloc, - NULL, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return _("invalid %function() here"); - - return parse_mep_alignu (cd, strp, opindex, valuep); -} - -static ATTRIBUTE_UNUSED const char * -parse_cdisp10 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg = 0; - signed long value; - long have_zero = 0; - int wide = 0; - int alignment; - - switch (opindex) - { - case MEP_OPERAND_CDISP10A4: - alignment = 2; - break; - case MEP_OPERAND_CDISP10A2: - alignment = 1; - break; - case MEP_OPERAND_CDISP10: - default: - alignment = 0; - break; - } - - if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) - wide = 1; - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (wide) - { - if (value < -512 || value > 511) - return _("Immediate is out of range -512 to 511"); - } - else - { - if (value < -128 || value > 127) - return _("Immediate is out of range -128 to 127"); - } - - if (value & ((1<>16) & 0xffff)" }, */ -/*{ "lo", "(`1 & 0xffff)" }, */ -/*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ -/*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ - { 0,0 } -}; - -static char * expand_string (const char *, int); - -static const char * -mep_cgen_expand_macros_and_parse_operand - (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); - -static char * -str_append (char *dest, const char *input, int len) -{ - char *new_dest; - int oldlen; - - if (len == 0) - return dest; - /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ - oldlen = (dest ? strlen(dest) : 0); - new_dest = realloc (dest, oldlen + len + 1); - memset (new_dest + oldlen, 0, len + 1); - return strncat (new_dest, input, len); -} - -static macro * -lookup_macro (const char *name) -{ - macro *m; - - for (m = macros; m->name; ++m) - if (strncmp (m->name, name, strlen(m->name)) == 0) - return m; - - return 0; -} - -static char * -expand_macro (arg *args, int narg, macro *mac) -{ - char *result = 0, *rescanned_result = 0; - char *e = mac->expansion; - char *mark = e; - int mac_arg = 0; - - /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ - while (*e) - { - if (*e == '`' && - (*e+1) && - ((*(e + 1) - '1') <= MAXARGS) && - ((*(e + 1) - '1') <= narg)) - { - result = str_append (result, mark, e - mark); - mac_arg = (*(e + 1) - '1'); - /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ - result = str_append (result, args[mac_arg].start, args[mac_arg].len); - ++e; - mark = e+1; - } - ++e; - } - - if (mark != e) - result = str_append (result, mark, e - mark); - - if (result) - { - rescanned_result = expand_string (result, 0); - free (result); - return rescanned_result; - } - else - return result; -} - -#define IN_TEXT 0 -#define IN_ARGS 1 - -static char * -expand_string (const char *in, int first_only) -{ - int num_expansions = 0; - int depth = 0; - int narg = -1; - arg args[MAXARGS]; - int state = IN_TEXT; - const char *mark = in; - macro *pmacro = NULL; - char *expansion = 0; - char *result = 0; - - while (*in) - { - switch (state) - { - case IN_TEXT: - if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) - { - pmacro = lookup_macro (in + 1); - if (pmacro) - { - /* printf("entering state %d at '%s'...\n", state, in); */ - result = str_append (result, mark, in - mark); - mark = in; - in += 1 + strlen (pmacro->name); - while (*in == ' ') ++in; - if (*in != '(') - { - state = IN_TEXT; - pmacro = NULL; - } - else - { - state = IN_ARGS; - narg = 0; - args[narg].start = in + 1; - args[narg].len = 0; - mark = in + 1; - } - } - } - break; - case IN_ARGS: - if (depth == 0) - { - switch (*in) - { - case ',': - narg++; - args[narg].start = (in + 1); - args[narg].len = 0; - break; - case ')': - state = IN_TEXT; - /* printf("entering state %d at '%s'...\n", state, in); */ - if (pmacro) - { - expansion = 0; - expansion = expand_macro (args, narg, pmacro); - num_expansions++; - if (expansion) - { - result = str_append (result, expansion, strlen (expansion)); - free (expansion); - } - } - else - { - result = str_append (result, mark, in - mark); - } - pmacro = NULL; - mark = in + 1; - break; - case '(': - depth++; - default: - args[narg].len++; - break; - } - } - else - { - if (*in == ')') - depth--; - if (narg > -1) - args[narg].len++; - } - - } - ++in; - } - - if (mark != in) - result = str_append (result, mark, in - mark); - - return result; -} - -#undef IN_ARGS -#undef IN_TEXT -#undef MAXARGS - - -/* END LIGHTWEIGHT MACRO PROCESSOR. */ - -const char * mep_cgen_parse_operand - (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); - -const char * -mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, - const char ** strp_in, CGEN_FIELDS * fields) -{ - const char * errmsg = NULL; - char *str = 0, *hold = 0; - const char **strp = 0; - - /* Set up a new pointer to macro-expanded string. */ - str = expand_string (*strp_in, 1); - /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ - - hold = str; - strp = (const char **)(&str); - - errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); - - /* Now work out the advance. */ - if (strlen (str) == 0) - *strp_in += strlen (*strp_in); - - else - { - if (strstr (*strp_in, str)) - /* A macro-expansion was pulled off the front. */ - *strp_in = strstr (*strp_in, str); - else - /* A non-macro-expansion was pulled off the front. */ - *strp_in += (str - hold); - } - - if (hold) - free (hold); - - return errmsg; -} - -#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); - -/* -- dis.c */ - -#include "elf/mep.h" -#include "elf-bfd.h" - -#define CGEN_VALIDATE_INSN_SUPPORTED - -static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); -static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); - -static void -print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, - CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, - unsigned int flags ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$tp"); -} - -static void -print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, - CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, - unsigned int flags ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$sp"); -} - -/* begin-cop-ip-print-handlers */ -static void -print_ivc2_cr (CGEN_CPU_DESC, - void *, - CGEN_KEYWORD *, - long, - unsigned int) ATTRIBUTE_UNUSED; -static void -print_ivc2_cr (CGEN_CPU_DESC cd, - void *dis_info, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long value, - unsigned int attrs) -{ - print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); -} -static void -print_ivc2_ccr (CGEN_CPU_DESC, - void *, - CGEN_KEYWORD *, - long, - unsigned int) ATTRIBUTE_UNUSED; -static void -print_ivc2_ccr (CGEN_CPU_DESC cd, - void *dis_info, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long value, - unsigned int attrs) -{ - print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); -} -/* end-cop-ip-print-handlers */ - -/************************************************************\ -*********************** Experimental ************************* -\************************************************************/ - -#undef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN mep_print_insn - -static int -mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, - bfd_byte *buf, int corelength, int copro1length, - int copro2length ATTRIBUTE_UNUSED) -{ - int i; - int status = 0; - /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ - bfd_byte insnbuf[64]; - - /* If corelength > 0 then there is a core insn present. It - will be at the beginning of the buffer. After printing - the core insn, we need to print the + on the next line. */ - if (corelength > 0) - { - int my_status = 0; - - for (i = 0; i < corelength; i++ ) - insnbuf[i] = buf[i]; - cd->isas = & MEP_CORE_ISA; - - my_status = print_insn (cd, pc, info, insnbuf, corelength); - if (my_status != corelength) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = corelength; - } - status += my_status; - - /* Print the + to indicate that the following copro insn is */ - /* part of a vliw group. */ - if (copro1length > 0) - (*info->fprintf_func) (info->stream, " + "); - } - - /* Now all that is left to be processed is the coprocessor insns - In vliw mode, there will always be one. Its positioning will - be from byte corelength to byte corelength+copro1length -1. - No need to check for existence. Also, the first vliw insn, - will, as spec'd, always be at least as long as the core insn - so we don't need to flush the buffer. */ - if (copro1length > 0) - { - int my_status = 0; - - for (i = corelength; i < corelength + copro1length; i++ ) - insnbuf[i - corelength] = buf[i]; - - switch (copro1length) - { - case 0: - break; - case 2: - cd->isas = & MEP_COP16_ISA; - break; - case 4: - cd->isas = & MEP_COP32_ISA; - break; - case 6: - cd->isas = & MEP_COP48_ISA; - break; - case 8: - cd->isas = & MEP_COP64_ISA; - break; - default: - /* Shouldn't be anything but 16,32,48,64. */ - break; - } - - my_status = print_insn (cd, pc, info, insnbuf, copro1length); - - if (my_status != copro1length) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = copro1length; - } - status += my_status; - } - -#if 0 - /* Now we need to process the second copro insn if it exists. We - have no guarantee that the second copro insn will be longer - than the first, so we have to flush the buffer if we are have - a second copro insn to process. If present, this insn will - be in the position from byte corelength+copro1length to byte - corelength+copro1length+copro2length-1 (which better equal 8 - or else we're in big trouble. */ - if (copro2length > 0) - { - int my_status = 0; - - for (i = 0; i < 64 ; i++) - insnbuf[i] = 0; - - for (i = corelength + copro1length; i < 64; i++) - insnbuf[i - (corelength + copro1length)] = buf[i]; - - switch (copro2length) - { - case 2: - cd->isas = 1 << ISA_EXT_COP1_16; - break; - case 4: - cd->isas = 1 << ISA_EXT_COP1_32; - break; - case 6: - cd->isas = 1 << ISA_EXT_COP1_48; - break; - case 8: - cd->isas = 1 << ISA_EXT_COP1_64; - break; - default: - /* Shouldn't be anything but 16,32,48,64. */ - break; - } - - my_status = print_insn (cd, pc, info, insnbuf, copro2length); - - if (my_status != copro2length) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = copro2length; - } - - status += my_status; - } -#endif - - /* Status should now be the number of bytes that were printed - which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ - - if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) - return -1; - else - return status; -} - -/* The two functions mep_examine_vliw[32,64]_insns are used find out - which vliw combinaion (16 bit core with 48 bit copro, 32 bit core - with 32 bit copro, etc.) is present. Later on, when internally - parallel coprocessors are handled, only these functions should - need to be changed. - - At this time only the following combinations are supported: - - VLIW32 Mode: - 16 bit core insn (core) and 16 bit coprocessor insn (cop1) - 32 bit core insn (core) - 32 bit coprocessor insn (cop1) - Note: As of this time, I do not believe we have enough information - to distinguish a 32 bit core insn from a 32 bit cop insn. Also, - no 16 bit coprocessor insns have been specified. - - VLIW64 Mode: - 16 bit core insn (core) and 48 bit coprocessor insn (cop1) - 32 bit core insn (core) and 32 bit coprocessor insn (cop1) - 64 bit coprocessor insn (cop1) - - The framework for an internally parallel coprocessor is also - present (2nd coprocessor insn is cop2), but at this time it - is not used. This only appears to be valid in VLIW64 mode. */ - -static int -mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int buflength; - int corebuflength; - int cop1buflength; - int cop2buflength; - bfd_byte buf[CGEN_MAX_INSN_SIZE]; - char indicator16[1]; - char indicatorcop32[2]; - - /* At this time we're not supporting internally parallel coprocessors, - so cop2buflength will always be 0. */ - cop2buflength = 0; - - /* Read in 32 bits. */ - buflength = 4; /* VLIW insn spans 4 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* Put the big endian representation of the bytes to be examined - in the temporary buffers for examination. */ - - if (info->endian == BFD_ENDIAN_BIG) - { - indicator16[0] = buf[0]; - indicatorcop32[0] = buf[0]; - indicatorcop32[1] = buf[1]; - } - else - { - indicator16[0] = buf[1]; - indicatorcop32[0] = buf[1]; - indicatorcop32[1] = buf[0]; - } - - /* If the two high order bits are 00, 01 or 10, we have a 16 bit - core insn and a 48 bit copro insn. */ - - if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) - { - if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) - { - /* We have a 32 bit copro insn. */ - corebuflength = 0; - /* All 4 4ytes are one copro insn. */ - cop1buflength = 4; - } - else - { - /* We have a 32 bit core. */ - corebuflength = 4; - cop1buflength = 0; - } - } - else - { - /* We have a 16 bit core insn and a 16 bit copro insn. */ - corebuflength = 2; - cop1buflength = 2; - } - - /* Now we have the distrubution set. Print them out. */ - status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, - cop1buflength, cop2buflength); - - return status; -} - -static int -mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int buflength; - int corebuflength; - int cop1buflength; - int cop2buflength; - bfd_byte buf[CGEN_MAX_INSN_SIZE]; - char indicator16[1]; - char indicator64[4]; - - /* At this time we're not supporting internally parallel - coprocessors, so cop2buflength will always be 0. */ - cop2buflength = 0; - - /* Read in 64 bits. */ - buflength = 8; /* VLIW insn spans 8 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* We have all 64 bits in the buffer now. We have to figure out - what combination of instruction sizes are present. The two - high order bits will indicate whether or not we have a 16 bit - core insn or not. If not, then we have to look at the 7,8th - bytes to tell whether we have 64 bit copro insn or a 32 bit - core insn with a 32 bit copro insn. Endianness will make a - difference here. */ - - /* Put the big endian representation of the bytes to be examined - in the temporary buffers for examination. */ - - /* indicator16[0] = buf[0]; */ - if (info->endian == BFD_ENDIAN_BIG) - { - indicator16[0] = buf[0]; - indicator64[0] = buf[0]; - indicator64[1] = buf[1]; - indicator64[2] = buf[2]; - indicator64[3] = buf[3]; - } - else - { - indicator16[0] = buf[1]; - indicator64[0] = buf[1]; - indicator64[1] = buf[0]; - indicator64[2] = buf[3]; - indicator64[3] = buf[2]; - } - - /* If the two high order bits are 00, 01 or 10, we have a 16 bit - core insn and a 48 bit copro insn. */ - - if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) - { - if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 - && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) - { - /* We have a 64 bit copro insn. */ - corebuflength = 0; - /* All 8 bytes are one copro insn. */ - cop1buflength = 8; - } - else - { - /* We have a 32 bit core insn and a 32 bit copro insn. */ - corebuflength = 4; - cop1buflength = 4; - } - } - else - { - /* We have a 16 bit core insn and a 48 bit copro insn. */ - corebuflength = 2; - cop1buflength = 6; - } - - /* Now we have the distrubution set. Print them out. */ - status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, - cop1buflength, cop2buflength); - - return status; -} - -#ifdef MEP_IVC2_SUPPORTED - -static int -print_slot_insn (CGEN_CPU_DESC cd, - bfd_vma pc, - disassemble_info *info, - SLOTS_ATTR slot, - bfd_byte *buf) -{ - const CGEN_INSN_LIST *insn_list; - CGEN_INSN_INT insn_value; - CGEN_EXTRACT_INFO ex_info; - - insn_value = cgen_get_insn_value (cd, buf, 32); - - /* Fill in ex_info fields like read_insn would. Don't actually call - read_insn, since the incoming buffer is already read (and possibly - modified a la m32r). */ - ex_info.valid = (1 << 8) - 1; - ex_info.dis_info = info; - ex_info.insn_bytes = buf; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - - if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) - && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) - || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) - { - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - continue; - } - - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value, &fields, pc); - - /* Length < 0 -> error. */ - if (length < 0) - return length; - if (length > 0) - { - CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* Length is in bits, result is in bytes. */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - if (slot == SLOTS_P0S) - (*info->fprintf_func) (info->stream, "*unknown-p0s*"); - else if (slot == SLOTS_P0) - (*info->fprintf_func) (info->stream, "*unknown-p0*"); - else if (slot == SLOTS_P1) - (*info->fprintf_func) (info->stream, "*unknown-p1*"); - else if (slot == SLOTS_C3) - (*info->fprintf_func) (info->stream, "*unknown-c3*"); - return 0; -} - -static int -mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) -{ - int status; - int buflength; - bfd_byte buf[8]; - bfd_byte insn[8]; - int e; - - /* Read in 64 bits. */ - buflength = 8; /* VLIW insn spans 8 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_LITTLE) - e = 1; - else - e = 0; - - if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V1 [-----core-----][--------p0s-------][------------p1------------] */ - - print_insn (cd, pc, info, buf, 2); - - insn[0^e] = 0; - insn[1^e] = buf[2^e]; - insn[2^e] = buf[3^e]; - insn[3^e] = buf[4^e] & 0xf0; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P0S, insn); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ - /* 00000000111111112222222233333333 */ - - insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; - insn[1^e] = buf[2^e]; - insn[2^e] = buf[3^e]; - insn[3^e] = buf[4^e] & 0xf0; - print_slot_insn (cd, pc, info, SLOTS_P0, insn); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - else - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V2 [-------------core-------------]xxxx[------------p1------------] */ - print_insn (cd, pc, info, buf, 4); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - - return 8; -} - -#endif /* MEP_IVC2_SUPPORTED */ - -/* This is a hack. SID calls this to update the disassembler as the - CPU changes modes. */ -static int mep_ivc2_disassemble_p = 0; -static int mep_ivc2_vliw_disassemble_p = 0; - -void -mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); -void -mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) -{ - mep_ivc2_disassemble_p = ivc2_p; - mep_ivc2_vliw_disassemble_p = vliw_p; - mep_config_index = cfg_idx; -} - -static int -mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int cop_type; - int ivc2 = 0; - static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; - - if (ivc2_core_isa == NULL) - { - /* IVC2 has some core-only coprocessor instructions. We - use COP32 to flag those, and COP64 for the VLIW ones, - since they have the same names. */ - ivc2_core_isa = cgen_bitset_create (MAX_ISAS); - } - - /* Extract and adapt to configuration number, if available. */ - if (info->section && info->section->owner) - { - bfd *abfd = info->section->owner; - mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; - /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ - - cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; - if (cop_type == EF_MEP_COP_IVC2) - ivc2 = 1; - } - - /* Picking the right ISA bitmask for the current context is tricky. */ - if (info->section) - { - if (info->section->flags & SEC_MEP_VLIW) - { -#ifdef MEP_IVC2_SUPPORTED - if (ivc2) - { - /* ivc2 has its own way of selecting its functions. */ - cd->isas = & MEP_CORE_ISA; - status = mep_examine_ivc2_insns (cd, pc, info); - } - else -#endif - /* Are we in 32 or 64 bit vliw mode? */ - if (MEP_VLIW64) - status = mep_examine_vliw64_insns (cd, pc, info); - else - status = mep_examine_vliw32_insns (cd, pc, info); - /* Both the above branches set their own isa bitmasks. */ - } - else - { - if (ivc2) - { - cgen_bitset_clear (ivc2_core_isa); - cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); - cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); - cd->isas = ivc2_core_isa; - } - else - cd->isas = & MEP_CORE_ISA; - status = default_print_insn (cd, pc, info); - } - } - else /* sid or gdb */ - { -#ifdef MEP_IVC2_SUPPORTED - if (mep_ivc2_disassemble_p) - { - if (mep_ivc2_vliw_disassemble_p) - { - cd->isas = & MEP_CORE_ISA; - status = mep_examine_ivc2_insns (cd, pc, info); - return status; - } - else - { - if (ivc2) - cd->isas = ivc2_core_isa; - } - } -#endif - - status = default_print_insn (cd, pc, info); - } - - return status; -} - - -/* -- opc.c */ -#include "elf/mep.h" - -/* A mask for all ISAs executed by the core. */ -CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; - -void -init_mep_all_core_isas_mask (void) -{ - if (mep_all_core_isas_mask.length != 0) - return; - cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); - cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); - /* begin-all-core-isas */ - cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); - /* end-all-core-isas */ -} - -CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; - -void -init_mep_all_cop_isas_mask (void) -{ - if (mep_all_cop_isas_mask.length != 0) - return; - cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); - /* begin-all-cop-isas */ - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); - /* end-all-cop-isas */ -} - -int -mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) -{ - CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); - return cgen_bitset_intersect_p (& insn_isas, isa_mask); -} - -#define OPTION_MASK \ - ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) - - -mep_config_map_struct mep_config_map[] = -{ - /* config-map-start */ - /* Default entry: first module, with all options enabled. */ - { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, - { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, - 0 - | (1 << CGEN_INSN_OPTIONAL_CP_INSN) - | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) - | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) - | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) - | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) - | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) - | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) - | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) - | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) - | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) - | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, - /* config-map-end */ - { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } -}; - -int mep_config_index = 0; - -static int -check_configured_mach (int machs) -{ - /* All base insns are supported. */ - int mach = 1 << MACH_BASE; - switch (MEP_CPU & EF_MEP_CPU_MASK) - { - case EF_MEP_CPU_C2: - case EF_MEP_CPU_C3: - mach |= (1 << MACH_MEP); - break; - case EF_MEP_CPU_H1: - mach |= (1 << MACH_H1); - break; - case EF_MEP_CPU_C5: - mach |= (1 << MACH_MEP); - mach |= (1 << MACH_C5); - break; - default: - break; - } - return machs & mach; -} - -int -mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); - int ok1; - int ok2; - int ok3; - - /* If the insn has an option bit set that we don't want, - reject it. */ - if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) - return 0; - - /* If attributes are absent, assume no restriction. */ - if (machs == 0) - machs = ~0; - - ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); - /* If the insn is config-specific, make sure it matches. */ - ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); - /* Make sure the insn is supported by the configured mach */ - ok3 = check_configured_mach (machs); - - return (ok1 && ok2 && ok3); -} - -int -mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ -#ifdef MEP_IVC2_SUPPORTED - /* If we're assembling VLIW packets, ignore the 12-bit BSR as we - can't relax that. The 24-bit BSR is matched instead. */ - if (insn->base->num == MEP_INSN_BSR12 - && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) - return 0; -#endif - - return mep_cgen_insn_supported (cd, insn); -} diff --git a/cpu/openrisc.cpu b/cpu/openrisc.cpu deleted file mode 100644 index 4e59847..0000000 --- a/cpu/openrisc.cpu +++ /dev/null @@ -1,775 +0,0 @@ -; OpenRISC family. -*- Scheme -*- -; Copyright 2000, 2001 Free Software Foundation, Inc. -; Contributed by Johan Rydberg, jrydberg@opencores.org -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -; - -(include "simplify.inc") - -; OpenRISC 1000 is an architecture of a family of open source, -; synthesizeable RISC microprocessor cores. It is a 32-bit load -; and store RISC architecture designed with emphasis on speed, -; compact instruction set and scalability. OpenRISC 1000 targets -; wide range of embedded environments. - -(define-arch - (name openrisc) - (comment "OpenRISC 1000") - (insn-lsb0? #t) - (machs openrisc or1300) - (isas or32) -) - - -; Attributes - -; An attribute to describe if a model has insn and/or data caches. -(define-attr - (for model) - (type enum) - (name HAS-CACHE) - (comment "if this model has caches") - (values DATA-CACHE INSN-CACHE) -) - -; An attribute to describe if an insn can be in the delay slot or not. -(define-attr - (for insn) - (type boolean) - (name NOT-IN-DELAY-SLOT) - (comment "insn can't go in delay slot") -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (FPU - () "FPU") - (BR - () "Branch") - (PRIV - () "Priviledged") - (MISC - () "Miscellaneous") - ) -) - -; Enum for exception vectors. -(define-enum - (name e-exception) - (comment "exception vectors") - (attrs) - (prefix E_) - (values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -) - ("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -) - ("SYSCALL" -) ("BREAK" -) ("RESERVED" -))) -) - - -; Instruction set parameters. - -(define-isa - ; Name of the ISA. - (name or32) - - ; Base insturction length. The insns is always 32 bits wide. - (base-insn-bitsize 32) - - ; Address of insn in delay slot - (setup-semantics (set-quiet (reg h-delay-insn) (add pc 4))) -) - - -; CPU family definitions. - -(define-cpu - ; CPU names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name openriscbf) - (comment "OpenRISC base family") - (endian big) - (word-bitsize 32) -) - -; Generic machine -(define-mach - (name openrisc) - (comment "Generic OpenRISC cpu") - (cpu openriscbf) - (bfd-name "openrisc") -) - -; OpenRISC 1300 machine -(define-mach - (name or1300) - (comment "OpenRISC 1300") - (cpu openriscbf) - (bfd-name "openrisc:1300") -) - - -; Model descriptions - -; Generic OpenRISC model -(define-model - (name openrisc-1) (comment "OpenRISC generic model") (attrs) - (mach openrisc) - - ; Nothing special about this. - (unit u-exec "Execution Unit" () 1 1 () () () ()) -) - -; OpenRISC 1320 -(define-model - (name or1320-1) (comment "OpenRISC 1320 model") - - ; This model has both instruction and data cache - (attrs (HAS-CACHE INSN-CACHE,DATA-CACHE)) - (mach or1300) - - ; Nothing special about this. - (unit u-exec "Execution Unit" () 1 1 () () () ()) -) - - -; Instruction fields. - -; Attributes: -; . PCREL-ADDR pc relative value (for reloc and disassembly purposes) -; . ABS-ADDR absolute address (for reloc and disassembly purposes?) -; . RESERVED bits are not used to decode insn, must be all 0 - -; Instruction classes. -(dnf f-class "insn class" () 31 2) -(dnf f-sub "sub class" () 29 4) - -; Register fields. -(dnf f-r1 "r1" () 25 5) -(dnf f-r2 "r2" () 20 5) -(dnf f-r3 "r3" () 15 5) - -; Immediates. -(df f-simm16 "signed imm (16)" () 15 16 INT #f #f) -(dnf f-uimm16 "unsigned imm (16)" () 15 16) -(dnf f-uimm5 "unsigned imm (5)" () 4 5) -(df f-hi16 "high 16" () 15 16 INT #f #f) -(df f-lo16 "low 16" () 15 16 INT #f #f) - -; Sub fields -(dnf f-op1 "op1" () 31 2) -(dnf f-op2 "op2" () 29 4) -(dnf f-op3 "op3" () 25 2) -(dnf f-op4 "op4" () 23 3) -(dnf f-op5 "op3" () 25 5) -(dnf f-op6 "op4" () 7 3) -(dnf f-op7 "op5" () 3 4) - -(dnf f-i16-1 "uimm16-1" () 10 11) -(dnf f-i16-2 "uimm16-2" () 25 5) - -; PC relative, 26-bit (2 shifted to right) -(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT - ((value pc) (sra WI (sub WI value pc) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) pc))) - -; absolute, 26-bit (2 shifted to right) -(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT - ((value pc) (sra WI pc (const 2))) - ((value pc) (sll WI value (const 2)))) - -(define-multi-ifield - (name f-i16nc) - (comment "16 bit signed") - (attrs SIGN-OPT) - (mode HI) - (subfields f-i16-1 f-i16-2) - (insert (sequence () - (set (ifield f-i16-2) (and (sra (ifield f-i16nc) - (const 11)) - (const #x1f))) - (set (ifield f-i16-1) (and (ifield f-i16nc) - (const #x7ff))))) - (extract (sequence () - (set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit" - (or (sll (ifield f-i16-2) - (const 11)) - (ifield f-i16-1)))))) -) - - -; Enums. - -; insn-class: bits 31-30 -(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class - (.map .str (.iota 4)) -) - -(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub - (.map .str (.iota 16)) -) - -(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3 - (.map .str (.iota 4)) -) - -(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4 - (.map .str (.iota 8)) -) - -(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5 - (.map .str (.iota 32)) -) - -(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6 - (.map .str (.iota 8)) -) - -(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7 - (.map .str (.iota 16)) -) - - - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(define-hardware - (name h-gr) (comment "general registers") (attrs PROFILE) - (type register WI (32)) - (indices keyword "" - ((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) - (r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) - (r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26) - (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11) - (sp 1) (fp 2))) -) - -(define-hardware - (name h-sr) (comment "special registers") - (type register WI (#x20000)) - (get (index) (c-call SI "@arch@_h_sr_get_handler" index)) - (set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval)) -) - -(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ()) -(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ()) - -(dsh h-cbit "condition bit" () (register BI)) -(dsh h-delay-insn "delay insn addr" () (register SI)) - - -; Instruction operands. - -(dnop sr "special register" (SEM-ONLY) h-sr f-nil) -(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil) -(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16) -(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16) -(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26) -(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26) -(dnop uimm-5 "imm5" () h-uint f-uimm5) - -(dnop rD "destination register" () h-gr f-r1) -(dnop rA "source register A" () h-gr f-r2) -(dnop rB "source register B" () h-gr f-r3) - -(dnop op-f-23 "f-op23" () h-uint f-op4) -(dnop op-f-3 "f-op3" () h-uint f-op5) - -; For hi(foo). -(define-operand - (name hi16) (comment "high 16 bit immediate, sign optional") - (attrs SIGN-OPT) - (type h-hi16) - (index f-simm16) - (handlers (parse "hi16")) -) - -; For lo(foo) -(define-operand - (name lo16) (comment "low 16 bit immediate, sign optional") - (attrs SIGN-OPT) - (type h-lo16) - (index f-lo16) - (handlers (parse "lo16")) -) - -(define-operand - (name ui16nc) - (comment "16 bit immediate, sign optional") - (attrs) - (type h-lo16) - (index f-i16nc) - (handlers (parse "lo16")) -) - - -; Instructions. - -; Branch releated instructions - -(dni l-j "jump (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.j ${abs-26}" - (+ OP1_0 OP2_0 abs-26) - - ; We execute the delay slot before doin' the real branch - (delay 1 (set pc abs-26)) - () -) - -(dni l-jal "jump and link (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jal ${abs-26}" - (+ OP1_0 OP2_1 abs-26) - - ; We execute the delay slot before doin' the real branch - ; Set LR to (delay insn addr + 4) - (sequence () - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc abs-26))) - () -) - -(dni l-jr "jump register (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jr $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16) - - ; We execute the delay slot before doin' the real branch - (delay 1 (set pc rA)) - () -) - -(dni l-jalr "jump register and link (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jalr $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16) - - ; We save the value of rA in a temporary slot before setting - ; the link register. This because "l.jalr r11" would cause - ; a forever-and-ever loop otherwise. - ; - ; We execute the delay slot before doin' the real branch - (sequence ((WI tmp-slot)) - (set tmp-slot rA) - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc tmp-slot))) - () -) - -(dni l-bal "branch and link (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bal ${disp-26}" - (+ OP1_0 OP2_2 disp-26) - - ; We execute the delay slot before doin' the real branch - ; Set LR to (delay insn addr + 4) - (sequence () - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc disp-26))) - () -) - -(dni l-bnf "branch if condition bit not set (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bnf ${disp-26}" - (+ OP1_0 OP2_3 disp-26) - - ; We execute the delay slot before doin' the real branch - (if (eq cbit 0) - (sequence () - (delay 1 (set pc disp-26)))) - () -) - -(dni l-bf "branch if condition bit is set (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bf ${disp-26}" - (+ OP1_0 OP2_4 disp-26) - - ; We execute the delay slot before doin' the real branch - (if (eq cbit 1) - (sequence () - (delay 1 (set pc disp-26)))) - () -) - -(dni l-brk "break (exception)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.brk ${uimm-16}" - (+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16) - - ; FIXME should we do it like this ?? - (c-call VOID "@cpu@_cpu_brk" uimm-16) - () -) - -(dni l-rfe "return from exception" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.rfe $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16) - (sequence () - (delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA)))) - () -) - -(dni l-sys "syscall (exception)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.sys ${uimm-16}" - (+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16) - (sequence() - (delay 1 (set pc (c-call SI "@cpu@_except" pc - #xc00 uimm-16)))) - () -) - - -; Misc instructions - -(dni l-nop "nop" - () - "l.nop" - (+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16) - (nop) - () -) - -(dnmi l-ret "ret" () - "l.ret" - (emit l-jr (rA 11) (uimm-16 0)) -) - -(dni l-movhi "movhi" - (DELAY-SLOT) - "l.movhi $rD,$hi16" - (+ OP1_0 OP2_6 hi16 rD rA) - (set rD (sll WI hi16 (const 16))) - () -) - - -; System releated instructions - -(dni l-mfsr "mfsr" - (DELAY-SLOT) - "l.mfsr $rD,$rA" - (+ OP1_0 OP2_7 rD rA uimm-16) - (set rD (c-call SI "@cpu@_cpu_mfsr" rA)) - () -) - -(dni l-mtsr "mtsr" - (DELAY-SLOT) - "l.mtsr $rA,$rB" - (+ OP1_1 OP2_0 rA rB rD (f-i16-1 0)) - (c-call VOID "@cpu@_cpu_mtsr" rA rB) - () -) - - - -; Load instructions - -(dni l-lw "load word" - (DELAY-SLOT) - "l.lw $rD,${simm-16}($rA)" - (+ OP1_2 OP2_0 rD rA simm-16) - (set rD (mem SI (add rA simm-16))) - () -) - -(dni l-lbz "load byte (zero extend)" - (DELAY-SLOT) - "l.lbz $rD,${simm-16}($rA)" - (+ OP1_2 OP2_1 rD rA simm-16) - (set rD (zext SI (mem QI (add rA simm-16)))) - () -) - -(dni l-lbs "load byte (sign extend)" - (DELAY-SLOT) - "l.lbs $rD,${simm-16}($rA)" - (+ OP1_2 OP2_2 rD rA simm-16) - (set rD (ext SI (mem QI (add rA simm-16)))) - () -) - -(dni l-lhz "load halfword (zero extend)" - (DELAY-SLOT) - "l.lhz $rD,${simm-16}($rA)" - (+ OP1_2 OP2_3 rD simm-16 rA) - (set rD (zext SI (mem HI (add rA simm-16)))) - () -) - -(dni l-lhs "load halfword (sign extend)" - (DELAY-SLOT) - "l.lhs $rD,${simm-16}($rA)" - (+ OP1_2 OP2_4 rD rA simm-16) - (set rD (ext SI (mem HI (add rA simm-16)))) - () -) - - -; Store instructions -; -; We have to use a multi field since the integer is splited over 2 fields - -(define-pmacro (store-insn mnemonic op2-op mode-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " imm(reg)/reg") - (DELAY-SLOT) - (.str "l." mnemonic " ${ui16nc}($rA),$rB") - (+ OP1_3 op2-op rB rD ui16nc) - (set (mem mode-op (add rA ui16nc)) rB) - () - ) - ) -) - -(store-insn sw OP2_5 SI) -(store-insn sb OP2_6 QI) -(store-insn sh OP2_7 HI) - - - -; Shift and rotate instructions - -; Reserved fields. -(dnf f-f-15-8 "nop" (RESERVED) 15 8) -(dnf f-f-10-3 "nop" (RESERVED) 10 3) -(dnf f-f-4-1 "nop" (RESERVED) 4 1) -(dnf f-f-7-3 "nop" (RESERVED) 7 3) - -(define-pmacro (shift-insn mnemonic op4-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/imm") - () - (.str "l." mnemonic "i $rD,$rA,${uimm-5}") - (+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5) - (set rD (mnemonic rA uimm-5)) - () - ) - ) -) - -(shift-insn sll OP6_0) -(shift-insn srl OP6_1) -(shift-insn sra OP6_2) -(shift-insn ror OP6_4) - - -; Arethmetic insns - -; Reserved fields. -(dnf f-f-10-7 "nop" (RESERVED) 10 7) - -(define-pmacro (ar-insn-u mnemonic op2-op op5-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/lo16") - () - (.str "l." mnemonic "i $rD,$rA,$lo16") - (+ OP1_2 op2-op rD rA lo16) - (set rD (mnemonic rA (and lo16 #xffff))) - () - ) - ) -) - -(define-pmacro (ar-insn-s mnemonic op2-op op5-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/lo16") - () - (.str "l." mnemonic "i $rD,$rA,$lo16") - (+ OP1_2 op2-op rD rA lo16) - (set rD (mnemonic rA lo16)) - () - ) - ) -) - -(ar-insn-s add OP2_5 OP7_0) -;;(ar-op-s addc OP2_5 OP7_0) -(ar-insn-s sub OP2_7 OP7_2) -(ar-insn-u and OP2_8 OP7_3) -(ar-insn-u or OP2_9 OP7_4) -(ar-insn-u xor OP2_10 OP7_5) -(ar-insn-u mul OP2_11 OP7_6) -;;(ar-op-u mac OP2_12 OP7_7) - - -(dni l-div "divide (signed)" - (DELAY-SLOT) - "l.div $rD,$rA,$rB" - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9) - (if VOID (eq rB (const 0)) - (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) - (set rD (div rA rB))) - () -) - -(dni l-divu "divide (unsigned)" - (DELAY-SLOT) - "l.divu $rD,$rA,$rB" - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10) - (if VOID (eq rB (const 0)) - (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) - (set rD (udiv rA rB))) - () -) - - -; Compare instructions - -; Reserved fields. -(dnf f-f-10-11 "nop" (RESERVED) 10 11) - -; Register compare (both signed and unsigned) -(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op) - (begin - (dni (.sym l- "sf" (.sym sem-op "s")) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "s $rA,$rB") - (+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "u")) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "u $rA,$rB") - (+ op1-op op2-op op3-op rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - ) -) - -; Immediate compare (both signed and unsigned) -(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op) - (begin - (dni (.sym l- "sf" (.sym sem-op "si")) - (.str "l." mnemonic "si reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "si $rA,${simm-16}") - (+ op1-op op2-op op3-op-2 rA simm-16) - (set cbit (sem-op rA simm-16)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "ui")) - (.str "l." mnemonic "ui reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}") - (+ op1-op op2-op op3-op rA uimm-16) - (set cbit (sem-op rA uimm-16)) - () - ) - ) -) - -(define-pmacro (sf-insn op5-op sem-op) - (begin - (dni (.sym l- "sf" sem-op) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) " $rA,$rB") - (+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "i")) - (.str "l." mnemonic "i reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "i $rA,${simm-16}") - (+ OP1_2 OP2_14 op5-op rA simm-16) - (set cbit (sem-op rA simm-16)) - () - ) - ) -) - - -(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt) -(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge) -(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt) -(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le) - -(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt) -(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge) -(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt) -(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le) - -(sf-insn OP5_0 eq) -(sf-insn OP5_1 ne) diff --git a/cpu/openrisc.opc b/cpu/openrisc.opc deleted file mode 100644 index e9a3004..0000000 --- a/cpu/openrisc.opc +++ /dev/null @@ -1,147 +0,0 @@ -/* OpenRISC opcode support. -*- C -*- - Copyright (C) 2000, 2001, 2003, 2005 Free Software Foundation - Based upon work by Red Hat, Inc. - This file is part of CGEN. */ - -/* This file is an addendum to or32.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - -opc.h additions use: "-- opc.h" - -opc.c additions use: "-- opc.c" - -asm.c additions use: "-- asm.c" - -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 64 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) - -extern long openrisc_sign_extend_16bit (long); -/* -- */ - -/* -- opc.c */ -/* -- */ - -/* -- asm.c */ - -static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); - -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -long -openrisc_sign_extend_16bit (long value) -{ - return ((value & 0xffff) ^ 0x8000) - 0x8000; -} - -/* Handle hi(). */ - -static const char * -parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - unsigned long ret; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "hi(", 3) == 0) - { - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; - ret = value; - } - else - { - if (**strp == '-') - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); - ret = value; - } - else - { - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); - ret = value; - } - } - - *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; - return errmsg; -} - -/* Handle lo(). */ - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - unsigned long ret; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "lo(", 3) == 0) - { - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - ret = value; - } - else - { - if (**strp == '-') - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); - ret = value; - } - else - { - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); - ret = value; - } - } - - *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; - return errmsg; -} - -/* -- */ - -/* -- ibd.h */ -extern long openrisc_sign_extend_16bit (long); - -/* -- */ diff --git a/cpu/xstormy16.cpu b/cpu/xstormy16.cpu deleted file mode 100644 index a2eca97..0000000 --- a/cpu/xstormy16.cpu +++ /dev/null @@ -1,1948 +0,0 @@ -; xstormy16 CPU core description. -*- Scheme -*- -; Copyright (C) 2001, 2002, 2003, 2006, 2009 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -(define-arch - (name xstormy16) - (comment "Xstormy16 architecture") - (insn-lsb0? #f) - (machs xstormy16) - (isas xstormy16) -) - -(define-isa - (name xstormy16) - (comment "Xstormy16 instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - ; FIXME base-insn-bitsize should be 16 too, but at present CGEN has - ; no support for instruction sets with opcode bits past - ; base-insn-bitsize, so we must set it to at least 20. - (base-insn-bitsize 32) -) - -(define-cpu - (name xstormy16) - (comment "Xstormy16 CPU core") - (endian little) - (insn-endian little) - (insn-chunk-bitsize 16) - (word-bitsize 32) -) - -(define-mach - (name xstormy16) - (comment "Xstormy16 CPU core") - (cpu xstormy16) - (isas xstormy16) -) - -(define-model - (name xstormy16) - (comment "Xstormy16 CPU core") - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () () () ()) -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (FPU - () "FPU") - (BR - () "Branch") - (PRIV - () "Priviledged") - (MISC - () "Miscellaneous") - ) -) - -; Hardware elements. - -(define-hardware - (name h-pc) - (comment "program counter") - (attrs PC) - (type pc) - (set (newval) (c-call "h_pc_set_handler" newval)) -) - -(define-keyword - (name gr-names) - (enum-prefix H-GR-) - (values (r0 0) (r1 1) (r2 2) (r3 3) - (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) - (r12 12) (r13 13) (r14 14) (r15 15) - (psw 14) (sp 15))) - -(define-keyword - (name gr-Rb-names) - (enum-prefix H-RBJ-) - (values (r8 0) (r9 1) (r10 2) (r11 3) - (r12 4) (r13 5) (r14 6) (r15 7) - (psw 6) (sp 7))) - -(define-hardware - (name h-gr) - (comment "registers") - (type register WI (16)) - (indices extern-keyword gr-names) - (get (index) (and #xFFFF (raw-reg h-gr index))) - (set (index newval) (c-call "h_gr_set_handler" index newval)) -) - -(define-hardware - (name h-Rb) - (comment "Rb registers") - (attrs VIRTUAL) - (type register SI(8)) - (indices extern-keyword gr-Rb-names) - (get (index) (reg h-gr (add index 8))) - (set (index newval) (set (reg h-gr (add index 8)) newval)) -) - -(define-hardware - (name h-Rbj) - (comment "Rbj registers") - (attrs VIRTUAL) - (type register SI(2)) - (indices extern-keyword gr-Rb-names) - (get (index) (reg h-gr (add index 8))) - (set (index newval) (set (reg h-gr (add index 8)) newval)) -) - -(define-hardware - (name h-Rpsw) - (comment "Register number field of the PSW") - (attrs VIRTUAL) - (type register WI) - (get () (and #xF (srl psw 12))) - (set (newval) (set psw (or (and psw #xFFF) - (sll HI newval 12))))) - -(define-pmacro (define-psw-field fnam hnam index) - (define-hardware - (name hnam) - (attrs VIRTUAL) - (type register SI) - (get () (and 1 (srl psw index))) - (set (newval) (set psw (or (and psw (inv (sll HI 1 index))) - (sll HI newval index))))) - ;(dnop fnam "" (SEM-ONLY) hnam f-nil) -) -(define-psw-field psw-z8 h-z8 0) -(dnop psw-z8 "" (SEM-ONLY) h-z8 f-nil) -(define-psw-field psw-z16 h-z16 1) -(dnop psw-z16 "" (SEM-ONLY) h-z16 f-nil) -(define-psw-field psw-cy h-cy 2) -(dnop psw-cy "" (SEM-ONLY) h-cy f-nil) -(define-psw-field psw-hc h-hc 3) -(dnop psw-hc "" (SEM-ONLY) h-hc f-nil) -(define-psw-field psw-ov h-ov 4) -(dnop psw-ov "" (SEM-ONLY) h-ov f-nil) -(define-psw-field psw-pt h-pt 5) -(dnop psw-pt "" (SEM-ONLY) h-pt f-nil) -(define-psw-field psw-s h-s 6) -(dnop psw-s "" (SEM-ONLY) h-s f-nil) - -(define-hardware - (name h-branchcond) - (comment "Condition of a branch instruction") - (type immediate (UINT 4)) - (values keyword "" - (("ge" 0) ("nc" 1) ("lt" 2) ("c" 3) - ("gt" 4) ("hi" 5) ("le" 6) ("ls" 7) - ("pl" 8) ("nv" 9) ("mi" 10) ("v" 11) - ("nz.b" 12) ("nz" 13) ("z.b" 14) ("z" 15))) -) - -(define-hardware - (name h-wordsize) - (comment "Data size") - (type immediate (UINT 1)) - (values keyword "" ((".b" 0) (".w" 1) ("" 1))) -) - - -; Instruction fields, and the corresponding operands. -; Register fields - -(dnf f-Rd "general register destination" () 12 4) -(dnop Rd "general register destination" () h-gr f-Rd) - -(dnf f-Rdm "general register destination" () 13 3) -(dnop Rdm "general register destination" () h-gr f-Rdm) - -(dnf f-Rm "general register for memory" () 4 3) -(dnop Rm "general register for memory" () h-gr f-Rm) - -(dnf f-Rs "general register source" () 8 4) -(dnop Rs "general register source" () h-gr f-Rs) - -(dnf f-Rb "base register" () 17 3) -(dnop Rb "base register" () h-Rb f-Rb) - -(dnf f-Rbj "base register for jump" () 11 1) -(dnop Rbj "base register for jump" () h-Rbj f-Rbj) - -; Main opcodes in 4 bit chunks - -(dnf f-op1 "opcode" () 0 4) -(define-normal-insn-enum insn-op1 "insn op enums" () OP1_ f-op1 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op2 "opcode" () 4 4) -(define-normal-insn-enum insn-op2 "insn op enums" () OP2_ f-op2 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) -(dnop bcond2 "branch condition opcode" () h-branchcond f-op2) - -(dnf f-op2a "opcode" () 4 3) -(define-normal-insn-enum insn-op2a "insn op enums" () OP2A_ f-op2a - ( "0" "2" "4" "6" "8" "A" "C" "E" )) - -(dnf f-op2m "opcode" () 7 1) -(define-normal-insn-enum insn-op2m "insn op enums" () OP2M_ f-op2m - ( "0" "1" )) -(dnop ws2 "word size opcode" () h-wordsize f-op2m) - -(dnf f-op3 "opcode" () 8 4) -(define-normal-insn-enum insn-op3 "insn op enums" () OP3_ f-op3 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op3a "opcode" () 8 2) -(define-normal-insn-enum insn-op3a "insn op enums" () OP3A_ f-op3a - ( "0" "1" "2" "3" )) - -(dnf f-op3b "opcode" () 8 3) -(define-normal-insn-enum insn-op3b "insn op enums" () OP3B_ f-op3b - ( "0" "2" "4" "6" "8" "A" "C" "E" )) - -(dnf f-op4 "opcode" () 12 4) -(define-normal-insn-enum insn-op4 "insn op enums" () OP4_ f-op4 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op4m "opcode" () 12 1) -(define-normal-insn-enum insn-op4m "insn op enums" () OP4M_ f-op4m - ( "0" "1" )) - -(dnf f-op4b "opcode" () 15 1) -(define-normal-insn-enum insn-op4b "insn op enums" () OP4B_ f-op4b - ( "0" "1" )) - -(dnf f-op5 "opcode" () 16 4) -(define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) -(dnop bcond5 "branch condition opcode" () h-branchcond f-op5) - -(dnf f-op5a "opcode" () 16 1) -(define-normal-insn-enum insn-op5a "insn op enums" () OP5A_ f-op5a - ( "0" "1" )) - -; The whole first word -(dnf f-op "opcode" () 0 16) - -; Immediate fields - -(dnf f-imm2 "2 bit unsigned" () 10 2) -(dnop imm2 "2 bit unsigned immediate" () h-uint f-imm2) - -(dnf f-imm3 "3 bit unsigned" () 4 3) -(dnop imm3 "3 bit unsigned immediate" () h-uint f-imm3) -(dnf f-imm3b "3 bit unsigned for bit tests" () 17 3) -(dnop imm3b "3 bit unsigned immediate for bit tests" () h-uint f-imm3b) - -(dnf f-imm4 "4 bit unsigned" () 8 4) -(define-operand - (name imm4) - (comment "4 bit unsigned immediate") - (attrs) - (type h-uint) - (index f-imm4) - (handlers (parse "small_immediate")) -) - -(dnf f-imm8 "8 bit unsigned" () 8 8) -(dnop imm8 "8 bit unsigned immediate" () h-uint f-imm8) -(define-operand - (name imm8small) - (comment "8 bit unsigned immediate") - (attrs) - (type h-uint) - (index f-imm8) - (handlers (parse "small_immediate")) -) - -(define-ifield - (name f-imm12) - (comment "12 bit signed") - (attrs) - (start 20) - (length 12) - (mode INT) -) -(dnop imm12 "12 bit signed immediate" () h-sint f-imm12) - -(dnf f-imm16 "16 bit" (SIGN-OPT) 16 16) -(define-operand - (name imm16) - (comment "16 bit immediate") - (attrs) - (type h-uint) - (index f-imm16) - (handlers (parse "immediate16")) -) - -(dnf f-lmem8 "8 bit unsigned low memory" (ABS-ADDR) 8 8) -(define-operand - (name lmem8) - (comment "8 bit unsigned immediate low memory") - (attrs) - (type h-uint) - (index f-lmem8) - (handlers (parse "mem8")) -) -(define-ifield - (name f-hmem8) - (comment "8 bit unsigned high memory") - (attrs ABS-ADDR) - (start 8) - (length 8) - (mode UINT) - (encode (value pc) (sub HI value #x7F00)) - (decode (value pc) (add HI value #x7F00)) -) -(define-operand - (name hmem8) - (comment "8 bit unsigned immediate high memory") - (attrs) - (type h-uint) - (index f-hmem8) - (handlers (parse "mem8")) -) - -(define-ifield - (name f-rel8-2) - (comment "8 bit relative address for 2-byte instruction") - (attrs PCREL-ADDR) - (start 8) - (length 8) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 2))) - (decode (value pc) (add SI value (add SI pc 2))) -) -(dnop rel8-2 "8 bit relative address" () h-uint f-rel8-2) - -(define-ifield - (name f-rel8-4) - (comment "8 bit relative address for 4-byte instruction") - (attrs PCREL-ADDR) - (start 8) - (length 8) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 4))) - (decode (value pc) (add SI value (add SI pc 4))) -) -(dnop rel8-4 "8 bit relative address" () h-uint f-rel8-4) - -(define-ifield - (name f-rel12) - (comment "12 bit relative address") - (attrs PCREL-ADDR) - (start 20) - (length 12) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 4))) - (decode (value pc) (add SI value (add SI pc 4))) -) -(dnop rel12 "12 bit relative address" () h-uint f-rel12) - -(define-ifield - (name f-rel12a) - (comment "12 bit relative address") - (attrs PCREL-ADDR) - (start 4) - (length 11) - (mode INT) - (encode (value pc) (sra SI (sub SI value (add SI pc 2)) 1)) - (decode (value pc) (add SI (sll value 1) (add SI pc 2))) -) -(dnop rel12a "12 bit relative address" () h-uint f-rel12a) - -(dnf f-abs24-1 "abs24 low part" () 8 8) -(dnf f-abs24-2 "abs24 high part" () 16 16) -(define-multi-ifield - (name f-abs24) - (comment "Absolute address for jmpf instruction") - (attrs ABS-ADDR) - (mode UINT) - (subfields f-abs24-1 f-abs24-2) - (insert (sequence () - (set (ifield f-abs24-1) (and (ifield f-abs24) #xFF)) - (set (ifield f-abs24-2) (srl (ifield f-abs24) 8)))) - (extract (set (ifield f-abs24) (or (sll (ifield f-abs24-2) 8) f-abs24-1))) -) -(dnop abs24 "24 bit absolute address" () h-uint f-abs24) - -; Names for registers -(dnop psw "program status word" (SEM-ONLY) h-gr 14) -(dnop Rpsw "N0-N3 of the program status word" (SEM-ONLY) h-Rpsw f-nil) -(dnop sp "stack pointer" (SEM-ONLY) h-gr 15) -(dnop R0 "R0" (SEM-ONLY) h-gr 0) -(dnop R1 "R1" (SEM-ONLY) h-gr 1) -(dnop R2 "R2" (SEM-ONLY) h-gr 2) -(dnop R8 "R8" (SEM-ONLY) h-gr 8) - -; Useful macros. - -; THe Z8, Z16, PT, and S flags of the PSW. -(define-pmacro (basic-psw value ws) - (or (or (zflag (and value #xFF)) - (sll HI (zflag HI value) 1)) - (or (sll HI (c-call BI "parity" value) 5) - (sll HI (nflag QI (srl value (mul ws 8))) 6)))) - - -; Update the PSW for destination register Rd, set Rd to value. -(define-pmacro (set-psw Rd index value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set (reg HI h-gr index) nvalue) - (set psw (or (and psw #x0F9C) - (or (sll index 12) - (basic-psw nvalue ws)))))) - -; Update the PSW for destination register Rd. -(define-pmacro (set-psw-nowrite index value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set psw (or (and psw #x0F9C) - (or (sll index 12) - (basic-psw nvalue ws)))))) - -; Update the PSW for destination non-register dest, set dest to value. -(define-pmacro (set-mem-psw dest value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set psw (or (and psw #xFF9C) - (basic-psw nvalue ws))) - (set dest nvalue))) - -; Update the PSW as with set-psw, but also set the carry flag. -(define-pmacro (set-psw-carry Rd index value carry ws) - (sequence ((HI nvalue) (HI newpsw)) - (set nvalue value) - (set newpsw (or (or (and psw #x0F98) - (sll (and carry #x1) 2)) - (or (sll index 12) - (basic-psw nvalue ws)))) - (set (reg HI h-gr index) nvalue) - (set psw newpsw) - )) - -; The all-purpose addition operation. -(define-pmacro (set-psw-add Rd index a b c) - (sequence ((HI value) (HI newpsw)) - (set value (addc a b c)) - (set newpsw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (add-oflag HI a b c) 4) - (sll HI (add-cflag HI a b c) 2)) - (or (and (srl HI (addc HI (and a #xF) (and b #xF) c) - 1) #x8) - (sll index 12))))) - (set (reg HI h-gr index) value) - (set psw newpsw) - )) - -; Set the PSW for a subtraction of a-b into Rd, but don't actually -; do the subtract. -(define-pmacro (set-psw-cmp Rd index a b) - (sequence ((HI value)) - (set value (sub a b)) - (set psw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (sub-oflag HI a b 0) 4) - (sll HI (sub-cflag HI a b 0) 2)) - (or (and (srl HI (sub HI (and a #xF) (and b #xF)) - 1) #x8) - (sll index 12))))))) - -; Likewise, for subtraction -; (this chip has a borrow for subtraction, rather than -; just using a carry for both). -(define-pmacro (set-psw-sub Rd index a b c) - (sequence ((HI value) (HI newpsw)) - (set value (subc a b c)) - (set newpsw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (sub-oflag HI a b c) 4) - (sll HI (sub-cflag HI a b c) 2)) - (or (and (srl HI (subc HI (and a #xF) (and b #xF) c) - 1) #x8) - (sll index 12))))) - (set (reg HI h-gr index) value) - (set psw newpsw) - )) - -; A 17-bit rotate-left operation -(define-pmacro (set-psw-rotate17 Rd index src c rot) - (sequence ((SI tmpfoo)) - (set tmpfoo (or (or (and (sll SI src 15) #x7FFE0000) - src) - (or (sll SI c 31) - (sll SI c 16)))) - (set tmpfoo (rol tmpfoo (and rot #x1F))) - (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1))) - -; A 17-bit rotate-right operation -(define-pmacro (set-psw-rrotate17 Rd index src c rot) - (sequence ((SI tmpfoo)) - (set tmpfoo (or (or (and (sll SI src 17) #xFFFE0000) - src) - (sll SI c 16))) - (set tmpfoo (ror tmpfoo (and rot #x0F))) - (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1))) - - -; Move Operations - -(define-pmacro (alignfix-mem where) - (mem HI (and where #xFFFE))) - -(define-pmacro (set-alignfix-mem where what) - (set (mem HI (and where #xFFFE)) what)) - -(define-pmacro (alignfix-mem-far where) - (mem HI (and where #xFFFFFFFE))) - -(define-pmacro (set-alignfix-mem-far where what) - (set (mem HI (and where #xFFFFFFFE)) what)) - -(dni movlmemimm - "Move immediate to low memory" - () - ("mov$ws2 $lmem8,#$imm16") - (+ OP1_7 OP2A_8 ws2 lmem8 imm16) - (if ws2 - (set-mem-psw (mem HI (and lmem8 #xFFFE)) imm16 ws2) - (set-mem-psw (mem QI lmem8) (and imm16 #xFF) ws2)) - () -) -(dni movhmemimm - "Move immediate to high memory" - () - ("mov$ws2 $hmem8,#$imm16") - (+ OP1_7 OP2A_A ws2 hmem8 imm16) - (if ws2 - (set-mem-psw (mem HI (and hmem8 #xFFFE)) imm16 ws2) - (set-mem-psw (mem QI hmem8) (and imm16 #xFF) ws2)) - () -) - -(dni movlgrmem - "Move low memory to register" - () - ("mov$ws2 $Rm,$lmem8") - (+ OP1_8 Rm ws2 lmem8) - (if ws2 - (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2) - (set-psw Rm (index-of Rm) (mem QI lmem8) ws2)) - () -) -(dni movhgrmem - "Move high memory to register" - () - ("mov$ws2 $Rm,$hmem8") - (+ OP1_A Rm ws2 hmem8) - (if ws2 - (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2) - (set-psw Rm (index-of Rm) (mem QI hmem8) ws2)) - () -) - -(dni movlmemgr - "Move low memory register to byte" - () - ("mov$ws2 $lmem8,$Rm") - (+ OP1_9 Rm ws2 lmem8) - (if ws2 - (set-mem-psw (mem HI (and lmem8 #xFFFE)) Rm ws2) - (set-mem-psw (mem QI lmem8) Rm ws2)) - () -) -(dni movhmemgr - "Move high memory register to byte" - () - ("mov$ws2 $hmem8,$Rm") - (+ OP1_B Rm ws2 hmem8) - (if ws2 - (set-mem-psw (mem HI (and hmem8 #xFFFE)) Rm ws2) - (set-mem-psw (mem QI hmem8) Rm ws2)) - () -) - -(dni movgrgri - "Move memory addressed by register to register" - () - ("mov$ws2 $Rdm,($Rs)") - (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2)) - () -) - -(dni movgrgripostinc - "Move memory addressed by postincrement register to register" - () - ("mov$ws2 $Rdm,($Rs++)") - (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2)) - (set Rs (add Rs (add 1 ws2)))) - () -) - -(dni movgrgripredec - "Move memory addressed by predecrement register to register" - () - ("mov$ws2 $Rdm,(--$Rs)") - (+ OP1_6 OP2A_8 ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add 1 ws2))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))) - () -) - -(dni movgrigr - "Move register to memory addressed by register" - () - ("mov$ws2 ($Rs),$Rdm") - (+ OP1_7 OP2A_2 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movgripostincgr - "Move register to memory addressed by postincrement register" - () - ("mov$ws2 ($Rs++),$Rdm") - (+ OP1_6 OP2A_2 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgripredecgr - "Move register to memory addressed by predecrement register" - () - ("mov$ws2 (--$Rs),$Rdm") - (+ OP1_6 OP2A_A ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm))) - () -) - -(dni movgrgrii - "Move memory addressed by indexed register to register" - () - ("mov$ws2 $Rdm,($Rs,$imm12)") - (+ OP1_7 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2)) - () -) - -(dni movgrgriipostinc - "Move memory addressed by indexed register postincrement to register" - () - ("mov$ws2 $Rdm,($Rs++,$imm12)") - (+ OP1_6 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2)) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgrgriipredec - "Move memory addressed by indexed register predecrement to register" - () - ("mov$ws2 $Rdm,(--$Rs,$imm12)") - (+ OP1_6 OP2A_8 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2))) - () -) - -(dni movgriigr - "Move register to memory addressed by indexed register" - () - ("mov$ws2 ($Rs,$imm12),$Rdm") - (+ OP1_7 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movgriipostincgr - "Move register to memory addressed by indexed register postincrement" - () - ("mov$ws2 ($Rs++,$imm12),$Rdm") - (+ OP1_6 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgriipredecgr - "Move register to memory addressed by indexed register predecrement" - () - ("mov$ws2 (--$Rs,$imm12),$Rdm") - (+ OP1_6 OP2A_A ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm))) - () -) - -(dni movgrgr - "Move general register to general register" - () - ("mov $Rd,$Rs") - (+ OP1_4 OP2_6 Rs Rd) - (set-psw Rd (index-of Rd) Rs 1) - () -) - -(dnmi movimm8 - "Move 8-bit immediate" - () - ("mov Rx,#$imm8") - (emit movwimm8 imm8) -) - -(dni movwimm8 - "Move 8-bit immediate" - () - ("mov.w Rx,#$imm8") - (+ OP1_4 OP2_7 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw imm8 1) - () -) - -(dnmi movgrimm8 - "Move 8-bit immediate to general register" - () - ("mov $Rm,#$imm8small") - (emit movwgrimm8 Rm imm8small) -) - -(dni movwgrimm8 - "Move 8-bit immediate to general register" - () - ("mov.w $Rm,#$imm8small") - (+ OP1_2 Rm OP2M_1 imm8small) - (set-psw Rm (index-of Rm) imm8small 1) - () -) - -(dnmi movgrimm16 - "Move 16-bit immediate to general register" - () - ("mov $Rd,#$imm16") - (emit movwgrimm16 Rd imm16) -) - -(dni movwgrimm16 - "Move 16-bit immediate to general register" - () - ("mov.w $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_3 Rd imm16) - (set-psw Rd (index-of Rd) imm16 1) - () -) - -(dni movlowgr - "Move 8 low bits to general register" - () - ("mov.b $Rd,RxL") - (+ OP1_3 OP2_0 OP3_C Rd) - (set-psw Rd (index-of Rd) (or (and Rd #xFF00) (and (reg HI h-gr Rpsw) #xFF)) 0) - () -) - -(dni movhighgr - "Move 8 high bits to general register" - () - ("mov.b $Rd,RxH") - (+ OP1_3 OP2_0 OP3_D Rd) - (set-psw Rd (index-of Rd) (or (and Rd #x00FF) (and (reg HI h-gr Rpsw) #xFF00)) 1) - () -) - -(dni movfgrgri - "Move far memory addressed by register to register" - () - ("movf$ws2 $Rdm,($Rs)") - (+ OP1_7 OP2A_4 ws2 Rs OP4M_0 Rdm) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (or (sll SI R8 16) Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (or (sll SI R8 16) Rs))) ws2)) - () -) - -(dni movfgrgripostinc - "Move far memory addressed by postincrement register to register" - () - ("movf$ws2 $Rdm,($Rs++)") - (+ OP1_6 OP2A_4 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2)) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movfgrgripredec - "Move far memory addressed by predecrement register to register" - () - ("movf$ws2 $Rdm,(--$Rs)") - (+ OP1_6 OP2A_C ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2))) - () -) - -(dni movfgrigr - "Move far register to memory addressed by register" - () - ("movf$ws2 ($Rs),$Rdm") - (+ OP1_7 OP2A_6 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movfgripostincgr - "Move far register to memory addressed by postincrement register" - () - ("movf$ws2 ($Rs++),$Rdm") - (+ OP1_6 OP2A_6 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movfgripredecgr - "Move far register to memory addressed by predecrement register" - () - ("movf$ws2 (--$Rs),$Rdm") - (+ OP1_6 OP2A_E ws2 Rs OP4M_0 Rdm) - (sequence () - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm))) - () -) - -(dni movfgrgrii - "Move far memory addressed by indexed register to register" - () - ("movf$ws2 $Rdm,($Rb,$Rs,$imm12)") - (+ OP1_7 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)) - () -) - -(dni movfgrgriipostinc - "Move far memory addressed by indexed register postincrement to register" - () - ("movf$ws2 $Rdm,($Rb,$Rs++,$imm12)") - (+ OP1_6 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)) - (set Rs (add Rs (add ws2 1))) - ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. - (if (eq Rs 0) (set Rb (add Rb 1))) - ) - () -) - -(dni movfgrgriipredec - "Move far memory addressed by indexed register predecrement to register" - () - ("movf$ws2 $Rdm,($Rb,--$Rs,$imm12)") - (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. - (if (eq Rs 0) (set Rb (sub Rb 1))) - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))) - () -) - -(dni movfgriigr - "Move far register to memory addressed by indexed register" - () - ("movf$ws2 ($Rb,$Rs,$imm12),$Rdm") - (+ OP1_7 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) - Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - - -(dni movfgriipostincgr - "Move far register to memory addressed by indexed register postincrement" - () - ("movf$ws2 ($Rb,$Rs++,$imm12),$Rdm") - (+ OP1_6 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1))) - ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. - (if (eq Rs 0) (set Rb (add Rb 1))) - ) - () -) - -(dni movfgriipredecgr - "Move far register to memory addressed by indexed register predecrement" - () - ("movf$ws2 ($Rb,--$Rs,$imm12),$Rdm") - (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. - (if (eq Rs 0) (set Rb (sub Rb 1))) - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm))) - () -) - -(dni maskgrgr - "Mask insert controlled by general register" - () - ("mask $Rd,$Rs") - (+ OP1_3 OP2_3 Rs Rd) - (set-psw Rd (index-of Rd) (or HI (and HI Rd (inv HI Rs)) (and (reg HI h-gr Rpsw) Rs)) 1) - () -) - -(dni maskgrimm16 - "Mask insert controlled by immediate value" - () - ("mask $Rd,#$imm16") - (+ OP1_3 OP2_0 OP3_E Rd imm16) - (set-psw Rd (index-of Rd) (or (and Rd (inv imm16)) (and (reg HI h-gr Rpsw) imm16)) 1) - () -) - -; Push, Pop -(dni pushgr - "Push register" - () - ("push $Rd") - (+ OP1_0 OP2_0 OP3_8 Rd) - (sequence () - (set (mem HI sp) Rd) - (set sp (add sp 2))) - () -) - -(dni popgr - "Pop into a register" - () - ("pop $Rd") - (+ OP1_0 OP2_0 OP3_9 Rd) - (sequence () - (set sp (add sp -2)) - (set Rd (mem HI sp))) - () -) - -; Swap -(dni swpn - "Swap low nibbles" - () - ("swpn $Rd") - (+ OP1_3 OP2_0 OP3_9 Rd) - (set-psw Rd (index-of Rd) (or (or (and (sll Rd 4) #xF0) - (and (srl Rd 4) #x0F)) - (and Rd #xFF00)) 0) - () -) - -(dni swpb - "Swap bytes" - () - ("swpb $Rd") - (+ OP1_3 OP2_0 OP3_8 Rd) - (set-psw Rd (index-of Rd) (or (sll Rd 8) (srl Rd 8)) 1) - () -) - -(dni swpw - "Swap words" - () - ("swpw $Rd,$Rs") - (+ OP1_3 OP2_2 Rs Rd) - (sequence ((HI foo)) - (set foo Rs) - (set Rs Rd) - (set-psw Rd (index-of Rd) foo 1)) - () -) - -; Logical Operations -(dni andgrgr - "AND general register with general register" - () - ("and $Rd,$Rs") - (+ OP1_4 OP2_0 Rs Rd) - (set-psw Rd (index-of Rd) (and Rd Rs) 1) - () -) - -(dni andimm8 - "AND with 8-bit immediate" - () - ("and Rx,#$imm8") - (+ OP1_4 OP2_1 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (and (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni andgrimm16 - "AND general register with 16-bit immediate" - () - ("and $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_0 Rd imm16) - (set-psw Rd (index-of Rd) (and Rd imm16) 1) - () -) - -(dni orgrgr - "OR general register with general register" - () - ("or $Rd,$Rs") - (+ OP1_4 OP2_2 Rs Rd) - (set-psw Rd (index-of Rd) (or Rd Rs) 1) - () -) - -(dni orimm8 - "OR with 8-bit immediate" - () - ("or Rx,#$imm8") - (+ OP1_4 OP2_3 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (or (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni orgrimm16 - "OR general register with 16-bit immediate" - () - ("or $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_1 Rd imm16) - (set-psw Rd (index-of Rd) (or Rd imm16) 1) - () -) - -(dni xorgrgr - "XOR general register with general register" - () - ("xor $Rd,$Rs") - (+ OP1_4 OP2_4 Rs Rd) - (set-psw Rd (index-of Rd) (xor Rd Rs) 1) - () -) - -(dni xorimm8 - "XOR with 8-bit immediate" - () - ("xor Rx,#$imm8") - (+ OP1_4 OP2_5 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (xor (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni xorgrimm16 - "XOR general register with 16-bit immediate" - () - ("xor $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_2 Rd imm16) - (set-psw Rd (index-of Rd) (xor Rd imm16) 1) - () -) - -(dni notgr - "NOT general register" - () - ("not $Rd") - (+ OP1_3 OP2_0 OP3_B Rd) - (set-psw Rd (index-of Rd) (inv Rd) 1) - () -) - -; Arithmetic operations -(dni addgrgr - "ADD general register to general register" - () - ("add $Rd,$Rs") - (+ OP1_4 OP2_9 Rs Rd) - (set-psw-add Rd (index-of Rd) Rd Rs 0) - () -) - -(dni addgrimm4 - "ADD 4-bit immediate to general register" - () - ("add $Rd,#$imm4") - (+ OP1_5 OP2_1 imm4 Rd) - (set-psw-add Rd (index-of Rd) Rd imm4 0) - () -) - -(dni addimm8 - "ADD 8-bit immediate" - () - ("add Rx,#$imm8") - (+ OP1_5 OP2_9 imm8) - (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0) - () -) - -(dni addgrimm16 - "ADD 16-bit immediate to general register" - () - ("add $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_4 Rd imm16) - (set-psw-add Rd (index-of Rd) Rd imm16 0) - () -) - -(dni adcgrgr - "ADD carry and general register to general register" - () - ("adc $Rd,$Rs") - (+ OP1_4 OP2_B Rs Rd) - (set-psw-add Rd (index-of Rd) Rd Rs psw-cy) - () -) - -(dni adcgrimm4 - "ADD carry and 4-bit immediate to general register" - () - ("adc $Rd,#$imm4") - (+ OP1_5 OP2_3 imm4 Rd) - (set-psw-add Rd (index-of Rd) Rd imm4 psw-cy) - () -) - -(dni adcimm8 - "ADD carry and 8-bit immediate" - () - ("adc Rx,#$imm8") - (+ OP1_5 OP2_B imm8) - (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy) - () -) - -(dni adcgrimm16 - "ADD carry and 16-bit immediate to general register" - () - ("adc $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_5 Rd imm16) - (set-psw-add Rd (index-of Rd) Rd imm16 psw-cy) - () -) - -(dni subgrgr - "SUB general register from general register" - () - ("sub $Rd,$Rs") - (+ OP1_4 OP2_D Rs Rd) - (set-psw-sub Rd (index-of Rd) Rd Rs 0) - () -) - -(dni subgrimm4 - "SUB 4-bit immediate from general register" - () - ("sub $Rd,#$imm4") - (+ OP1_5 OP2_5 imm4 Rd) - (set-psw-sub Rd (index-of Rd) Rd imm4 0) - () -) - -(dni subimm8 - "SUB 8-bit immediate" - () - ("sub Rx,#$imm8") - (+ OP1_5 OP2_D imm8) - (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0) - () -) - -(dni subgrimm16 - "SUB 16-bit immediate from general register" - () - ("sub $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_6 Rd imm16) - (set-psw-sub Rd (index-of Rd) Rd imm16 0) - () -) - -(dni sbcgrgr - "SUB carry and general register from general register" - () - ("sbc $Rd,$Rs") - (+ OP1_4 OP2_F Rs Rd) - (set-psw-sub Rd (index-of Rd) Rd Rs psw-cy) - () -) - -(dni sbcgrimm4 - "SUB carry and 4-bit immediate from general register" - () - ("sbc $Rd,#$imm4") - (+ OP1_5 OP2_7 imm4 Rd) - (set-psw-sub Rd (index-of Rd) Rd imm4 psw-cy) - () -) - -(dni sbcgrimm8 - "SUB carry and 8-bit immediate" - () - ("sbc Rx,#$imm8") - (+ OP1_5 OP2_F imm8) - (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy) - () -) - -(dni sbcgrimm16 - "SUB carry and 16-bit immediate from general register" - () - ("sbc $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_7 Rd imm16) - (set-psw-sub Rd (index-of Rd) Rd imm16 psw-cy) - () -) - -(dnmi incgr - "Increment general register" - () - ("inc $Rd") - (emit incgrimm2 Rd (imm2 0)) -) - -(dni incgrimm2 - "Increment general register by 2-bit immediate" - () - ("inc $Rd,#$imm2") - (+ OP1_3 OP2_0 OP3A_0 imm2 Rd) - (set-psw Rd (index-of Rd) (add Rd (add imm2 1)) 1) - () -) - -(dnmi decgr - "Decrement general register" - () - ("dec $Rd") - (emit decgrimm2 Rd (imm2 0)) -) - -(dni decgrimm2 - "Decrement general register by 2-bit immediate" - () - ("dec $Rd,#$imm2") - (+ OP1_3 OP2_0 OP3A_1 imm2 Rd) - (set-psw Rd (index-of Rd) (sub Rd (add imm2 1)) 1) - () -) - -; Logical Shift -(dni rrcgrgr - "Rotate right general register by general register" - () - ("rrc $Rd,$Rs") - (+ OP1_3 OP2_8 Rs Rd) - (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy Rs) - () -) - -(dni rrcgrimm4 - "Rotate right general register by immediate" - () - ("rrc $Rd,#$imm4") - (+ OP1_3 OP2_9 imm4 Rd) - (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy imm4) - () -) - -(dni rlcgrgr - "Rotate left general register by general register" - () - ("rlc $Rd,$Rs") - (+ OP1_3 OP2_A Rs Rd) - (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy (and Rs #xF)) - () -) - -(dni rlcgrimm4 - "Rotate left general register by immediate" - () - ("rlc $Rd,#$imm4") - (+ OP1_3 OP2_B imm4 Rd) - (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy imm4) - () -) - -(dni shrgrgr - "Shift right general register by general register" - () - ("shr $Rd,$Rs") - (+ OP1_3 OP2_C Rs Rd) - (set-psw-carry Rd (index-of Rd) - (srl Rd (and Rs #xF)) - (and SI (if SI (eq (and Rs #xF) 0) - psw-cy - (srl Rd (sub (and Rs #xF) 1))) - 1) 1) - () -) - -(dni shrgrimm - "Shift right general register by immediate" - () - ("shr $Rd,#$imm4") - (+ OP1_3 OP2_D imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (srl Rd imm4) - (and SI (if SI (eq imm4 0) - psw-cy - (srl Rd (sub imm4 1))) - 1) 1) - () -) - -(dni shlgrgr - "Shift left general register by general register" - () - ("shl $Rd,$Rs") - (+ OP1_3 OP2_E Rs Rd) - (set-psw-carry Rd (index-of Rd) - (sll Rd (and Rs #xF)) - (srl SI (if SI (eq (and Rs #xF) 0) - (sll psw-cy 15) - (sll Rd (sub (and Rs #xF) 1))) - 15) 1) - () -) - -(dni shlgrimm - "Shift left general register by immediate" - () - ("shl $Rd,#$imm4") - (+ OP1_3 OP2_F imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (sll Rd imm4) - (srl SI (if SI (eq imm4 0) - (sll psw-cy 15) - (sll Rd (sub imm4 1))) - 15) 1) - () -) - -(dni asrgrgr - "Arithmetic shift right general register by general register" - () - ("asr $Rd,$Rs") - (+ OP1_3 OP2_6 Rs Rd) - (set-psw-carry Rd (index-of Rd) - (sra HI Rd (and Rs #xF)) - (and SI (if SI (eq (and Rs #xF) 0) - psw-cy - (srl Rd (sub (and Rs #xF) 1))) - 1) 1) - () -) - -(dni asrgrimm - "Arithmetic shift right general register by immediate" - () - ("asr $Rd,#$imm4") - (+ OP1_3 OP2_7 imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (sra HI Rd imm4) - (and SI (if SI (eq imm4 0) - psw-cy - (srl Rd (sub imm4 1))) - 1) 1) - () -) - -; Bitwise operations -(dni set1grimm - "Set bit in general register by immediate" - () - ("set1 $Rd,#$imm4") - (+ OP1_0 OP2_9 imm4 Rd) - (set-psw Rd (index-of Rd) (or Rd (sll 1 imm4)) 1) - () -) - -(dni set1grgr - "Set bit in general register by general register" - () - ("set1 $Rd,$Rs") - (+ OP1_0 OP2_B Rs Rd) - (set-psw Rd (index-of Rd) (or Rd (sll 1 (and Rs #xF))) 1) - () -) - -(dni set1lmemimm - "Set bit in low memory by immediate" - () - ("set1 $lmem8,#$imm3") - (+ OP1_E imm3 OP2M_1 lmem8) - (set-mem-psw (mem QI lmem8) (or (mem QI lmem8) (sll 1 imm3)) 0) - () -) -(dni set1hmemimm - "Set bit in high memory by immediate" - () - ("set1 $hmem8,#$imm3") - (+ OP1_F imm3 OP2M_1 hmem8) - (set-mem-psw (mem QI hmem8) (or (mem QI hmem8) (sll 1 imm3)) 0) - () -) - -(dni clr1grimm - "Clear bit in general register by immediate" - () - ("clr1 $Rd,#$imm4") - (+ OP1_0 OP2_8 imm4 Rd) - (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 imm4))) 1) - () -) - -(dni clr1grgr - "Clear bit in general register by general register" - () - ("clr1 $Rd,$Rs") - (+ OP1_0 OP2_A Rs Rd) - (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 (and Rs #xF)))) 1) - () -) - -(dni clr1lmemimm - "Clear bit in low memory" - () - ("clr1 $lmem8,#$imm3") - (+ OP1_E imm3 OP2M_0 lmem8) - (set-mem-psw (mem QI lmem8) (and (mem QI lmem8) (inv (sll 1 imm3))) 0) - () -) -(dni clr1hmemimm - "Clear bit in high memory" - () - ("clr1 $hmem8,#$imm3") - (+ OP1_F imm3 OP2M_0 hmem8) - (set-mem-psw (mem QI hmem8) (and (mem QI hmem8) (inv (sll 1 imm3))) 0) - () -) - -; Data conversion - -(dni cbwgr - "Sign-extend byte in general register" - () - ("cbw $Rd") - (+ OP1_3 OP2_0 OP3_A Rd) - (set-psw Rd (index-of Rd) (ext HI (trunc QI Rd)) 1) - () -) - -(dni revgr - "Reverse bit pattern in general register" - () - ("rev $Rd") - (+ OP1_3 OP2_0 OP3_F Rd) - (set-psw Rd (index-of Rd) - (or (sll (and Rd #x0001) 15) - (or (sll (and Rd #x0002) 13) - (or (sll (and Rd #x0004) 11) - (or (sll (and Rd #x0008) 9) - (or (sll (and Rd #x0010) 7) - (or (sll (and Rd #x0020) 5) - (or (sll (and Rd #x0040) 3) - (or (sll (and Rd #x0080) 1) - (or (srl (and Rd #x0100) 1) - (or (srl (and Rd #x0200) 3) - (or (srl (and Rd #x0400) 5) - (or (srl (and Rd #x0800) 7) - (or (srl (and Rd #x1000) 9) - (or (srl (and Rd #x2000) 11) - (or (srl (and Rd #x4000) 13) - (srl (and Rd #x8000) 15)))))))))))))))) - 1) - () -) - -; Conditional Branches - -(define-pmacro (cbranch cond dest) - (sequence ((BI tmp)) - (case cond - ((0) (set tmp (not (xor psw-s psw-ov)))) ; ge - ((1) (set tmp (not psw-cy))) ; nc - ((2) (set tmp (xor psw-s psw-ov))) ; lt - ((3) (set tmp psw-cy)) ; c - ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ; gt - ((5) (set tmp (not (or psw-cy psw-z16)))) ; hi - ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ; le - ((7) (set tmp (or psw-cy psw-z16))) ; ls - ((8) (set tmp (not psw-s))) ; pl - ((9) (set tmp (not psw-ov))) ; nv - ((10) (set tmp psw-s)) ; mi - ((11) (set tmp psw-ov)) ; v - ((12) (set tmp (not psw-z8))) ; nz.b - ((13) (set tmp (not psw-z16))) ; nz - ((14) (set tmp psw-z8)) ; z.b - ((15) (set tmp psw-z16))) ; z - (if tmp (set pc dest))) -) - -(dni bccgrgr - "Conditional branch comparing general register with general register" - () - ("b$bcond5 $Rd,$Rs,$rel12") - (+ OP1_0 OP2_D Rs Rd bcond5 rel12) - (sequence () - (set-psw-cmp Rd (index-of Rd) Rd Rs) - (cbranch bcond5 rel12)) - () -) - -; 4 bytes -(dni bccgrimm8 - "Conditional branch comparing general register with 8-bit immediate" - () - ("b$bcond5 $Rm,#$imm8,$rel12") - (+ OP1_2 OP2M_0 Rm imm8 bcond5 rel12) - (sequence () - (set-psw-cmp Rm (index-of Rm) Rm imm8) - (cbranch bcond5 rel12)) - () -) - -; 4 bytes -(dni bccimm16 - "Conditional branch comparing general register with 16-bit immediate" - () - ("b$bcond2 Rx,#$imm16,${rel8-4}") - (+ OP1_C bcond2 rel8-4 imm16) - (sequence () - (set-psw-cmp (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm16) - (cbranch bcond2 rel8-4)) - () -) - -(dni bngrimm4 - "Test bit in general register by immediate and branch if 0" - () - ("bn $Rd,#$imm4,$rel12") - (+ OP1_0 OP2_4 imm4 Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (eq (and Rd (sll 1 imm4)) 0) - (set pc rel12))) - () -) - -(dni bngrgr - "Test bit in general register by general register and branch if 0" - () - ("bn $Rd,$Rs,$rel12") - (+ OP1_0 OP2_6 Rs Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (eq (and Rd (sll 1 Rs)) 0) - (set pc rel12))) - () -) - -(dni bnlmemimm - "Test bit in memory by immediate and branch if 0" - () - ("bn $lmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_C lmem8 OP5A_0 imm3b rel12) - (if (eq (and (mem QI lmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bnhmemimm - "Test bit in memory by immediate and branch if 0" - () - ("bn $hmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_E hmem8 OP5A_0 imm3b rel12) - (if (eq (and (mem QI hmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bpgrimm4 - "Test bit in general register by immediate and branch if 1" - () - ("bp $Rd,#$imm4,$rel12") - (+ OP1_0 OP2_5 imm4 Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (ne (and Rd (sll 1 imm4)) 0) - (set pc rel12))) - () -) - -(dni bpgrgr - "Test bit in general register by general register and branch if 1" - () - ("bp $Rd,$Rs,$rel12") - (+ OP1_0 OP2_7 Rs Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (ne (and Rd (sll 1 Rs)) 0) - (set pc rel12))) - () -) - -(dni bplmemimm - "Test bit in memory by immediate and branch if 1" - () - ("bp $lmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_D lmem8 OP5A_0 imm3b rel12) - (if (ne (and (mem QI lmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bphmemimm - "Test bit in memory by immediate and branch if 1" - () - ("bp $hmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_F hmem8 OP5A_0 imm3b rel12) - (if (ne (and (mem QI hmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bcc - "Conditional branch on flag registers" - () - ("b$bcond2 ${rel8-2}") - (+ OP1_D bcond2 rel8-2) - (cbranch bcond2 rel8-2) - () -) - -; Unconditional Branching - -(dni bgr - "Branch to register" - () - ("br $Rd") - (+ OP1_0 OP2_0 OP3_2 Rd) - (set pc (add (add pc 2) Rd)) - () -) - -(dni br - "Branch" - () - ("br $rel12a") - (+ OP1_1 rel12a OP4B_0) - (set pc rel12a) - () -) - -(dni jmp - "Jump" - () - ("jmp $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_4 Rbj Rd) - (set pc (join SI HI Rbj Rd)) - () -) - -(dni jmpf - "Jump far" - () - ("jmpf $abs24") - (+ OP1_0 OP2_2 abs24) - (set pc abs24) - () -) - -; Call instructions -(define-pmacro (do-call dest ilen) - (sequence () - (set (mem SI sp) (add pc ilen)) - (set sp (add sp 4)) - (set pc dest))) - -(dni callrgr - "Call relative to general register" - () - ("callr $Rd") - (+ OP1_0 OP2_0 OP3_1 Rd) - (do-call (add Rd (add pc 2)) 2) - () -) - -(dni callrimm - "Call relative to immediate address" - () - ("callr $rel12a") - (+ OP1_1 rel12a OP4B_1) - (do-call rel12a 2) - () -) - -(dni callgr - "Call to general registers" - () - ("call $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_A Rbj Rd) - (do-call (join SI HI Rbj Rd) 2) - () -) - -(dni callfimm - "Call far to absolute address" - () - ("callf $abs24") - (+ OP1_0 OP2_1 abs24) - (do-call abs24 4) - () -) - -(define-pmacro (do-calli dest ilen) - (sequence () - (set (mem SI sp) (add pc ilen)) - (set (mem HI (add sp 4)) psw) - (set sp (add sp 6)) - (set pc dest))) - -(dni icallrgr - "Call interrupt to general registers pc-relative" - () - ("icallr $Rd") - (+ OP1_0 OP2_0 OP3_3 Rd) - (do-calli (add Rd (add pc 2)) 2) - () -) - -(dni icallgr - "Call interrupt to general registers" - () - ("icall $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_6 Rbj Rd) - (do-calli (join SI HI Rbj Rd) 2) - () -) - -(dni icallfimm - "Call interrupt far to absolute address" - () - ("icallf $abs24") - (+ OP1_0 OP2_3 abs24) - (do-calli abs24 4) - () -) - -; Return instructions -(dni iret - "Return from interrupt" - () - ("iret") - (+ (f-op #x0002)) - (sequence () - (set sp (sub sp 6)) - (set pc (mem SI sp)) - (set psw (mem HI (add sp 4)))) - () -) - -(dni ret - "Return" - () - ("ret") - (+ (f-op #x0003)) - (sequence () - (set sp (sub sp 4)) - (set pc (mem SI sp))) - () -) - -; Multiply and Divide instructions - -(dni mul - "Multiply" - () - ("mul") - (+ (f-op #x00D0)) - (sequence ((SI value)) - (set value (mul SI (and SI R0 #xFFFF) (and SI R2 #xFFFF))) - (set psw (or (and psw #xFF9C) - (basic-psw (trunc HI value) 1))) - (set R0 (trunc HI value)) - (set R1 (trunc HI (srl value 16)))) - () -) -(dni div - "Divide" - () - ("div") - (+ (f-op #x00C0)) - (sequence () - (set R1 (umod R0 R2)) - (set-mem-psw R0 (udiv R0 R2) 1)) - () -) -(dni sdiv - "Signed Divide" - () - ("sdiv") - (+ (f-op #x00C8)) - (sequence () - (set R1 (mod HI R0 R2)) - (set-mem-psw R0 (div HI R0 R2) 1)) - () -) -(dni sdivlh - "Divide 32/16" - () - ("sdivlh") - (+ (f-op #x00E8)) - (sequence ((SI value)) - (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff))) - (set R1 (mod SI value (ext SI (trunc HI R2)))) - (set-mem-psw R0 (div SI value (ext SI (trunc HI R2))) 1)) - () -) -(dni divlh - "Divide 32/16" - () - ("divlh") - (+ (f-op #x00E0)) - (sequence ((SI value)) - (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff))) - (set R1 (umod SI value R2)) - (set-mem-psw R0 (udiv SI value R2) 1)) - () -) - -; System Control - -; added per sanyo's req -- eq to nop for the moment, but can -; add function later -(dni reset "reset" () ("reset") (+ (f-op #x000f)) (nop) ()) - -(dni nop "nop" () ("nop") (+ (f-op #x0000)) (nop) ()) - -(dni halt "halt" () ("halt") (+ (f-op #x0008)) (c-call VOID "do_halt") ()) - -(dni hold "hold" () ("hold") (+ (f-op #x000A)) (c-call VOID "do_hold") ()) - -(dni holdx "holdx" () ("holdx") (+ (f-op #x000B)) (c-call VOID "do_holdx") ()) - -(dni brk "brk" () ("brk") (+ (f-op #x0005)) (c-call VOID "do_brk") ()) - -; An instruction for test instrumentation. -; Using a reserved opcode. -(dni syscall - "simulator system call" - () - ("--unused--") - (+ (f-op #x0001)) - (c-call VOID "syscall") - () -) diff --git a/cpu/xstormy16.opc b/cpu/xstormy16.opc deleted file mode 100644 index 638f0a1..0000000 --- a/cpu/xstormy16.opc +++ /dev/null @@ -1,150 +0,0 @@ -/* XSTORMY16 opcode support. -*- C -*- - Copyright (C) 2001, 2002, 2005 Red Hat, Inc. - This file is part of CGEN. */ - -/* This file is an addendum to xstormy16.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - -opc.h additions use: "-- opc.h" - -opc.c additions use: "-- opc.c" - -asm.c additions use: "-- asm.c" - -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* We can't use the default hash size because many bits are used by - operands. */ -#define CGEN_DIS_HASH_SIZE 1 -#define CGEN_DIS_HASH(buf, value) 0 -/* -- */ - -/* -- asm.c */ - -/* The machine-independent code doesn't know how to disambiguate - mov (foo),r3 - and - mov (r2),r3 - where 'foo' is a label. This helps it out. */ - -static const char * -parse_mem8 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (**strp == '(') - { - const char *s = *strp; - - if (s[1] == '-' && s[2] == '-') - return _("Bad register in preincrement"); - - while (ISALNUM (*++s)) - ; - if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ',')) - return _("Bad register in postincrement"); - if (s[0] == ',' || s[0] == ')') - return _("Bad register name"); - } - else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, - (long *) valuep) == NULL) - return _("Label conflicts with register name"); - else if (strncasecmp (*strp, "rx,", 3) == 0 - || strncasecmp (*strp, "rxl,", 3) == 0 - || strncasecmp (*strp, "rxh,", 3) == 0) - return _("Label conflicts with `Rx'"); - else if (**strp == '#') - return _("Bad immediate expression"); - - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -/* For the add and subtract instructions, there are two immediate forms, - one for small operands and one for large ones. We want to use - the small one when possible, but we do not want to generate relocs - of the small size. This is somewhat tricky. */ - -static const char * -parse_small_immediate (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - if (**strp == '@') - return _("No relocation for small immediate"); - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - & result, & value); - - if (errmsg) - return errmsg; - - if (result != CGEN_PARSE_OPERAND_RESULT_NUMBER) - return _("Small operand was not an immediate number"); - - *valuep = value; - return NULL; -} - -/* Literal scan be either a normal literal, a @hi() or @lo relocation. */ - -static const char * -parse_immediate16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (strncmp (*strp, "@hi(", 4) == 0) - { - *strp += 4; - code = BFD_RELOC_HI16; - } - else - if (strncmp (*strp, "@lo(", 4) == 0) - { - *strp += 4; - code = BFD_RELOC_LO16; - } - - if (code == BFD_RELOC_NONE) - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - else - { - errmsg = cgen_parse_address (cd, strp, opindex, code, &result, &value); - if ((errmsg == NULL) && - (result != CGEN_PARSE_OPERAND_RESULT_QUEUED)) - errmsg = _("Operand is not a symbol"); - - *valuep = value; - if ((code == BFD_RELOC_HI16 || code == BFD_RELOC_LO16) - && **strp == ')') - *strp += 1; - else - { - errmsg = _("Syntax error: No trailing ')'"); - return errmsg; - } - } - return errmsg; -} -/* -- */ -- 2.43.5