Code for am_reg in InstructionDecoder_x86::decodeOneOperand
relies on internal register IDs being the same as their encoding
in the machine instruction.
Besides that, we need compatibility between x86 and x86_64 register IDs.
Some of these instructions were supported, but not all. Some had incorrect number of arguments. Some vmovdqa32/vmodqa64 instructions were recognized as regular vmovdqa.
Dmitry Koltunov [Fri, 7 Jun 2024 20:48:46 +0000 (23:48 +0300)]
x86: add support for decoding multiple instructions and fix decoding of supported instructions (#1760)
* x86: add support for blsr, blsmsk, blsi with mem operand
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: add support for adcx, adox instructions
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: add support for vblendpd, vpblendw and fix blendps, blendpd, pblendw, vblendps instructions
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: fix decoding of vpmaskmovd,vpmaskmovq instructions
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: fix decoding of pextrb, pextrw and add vpextrw with opcode 0x15
Move pextrb and pextrw instructions to the correct position in sse_ter_table
since they are prefixed with 66 and not F2. Add support for decoding of EVEX
prefixed vpextrw instruction. Make operands of vpextrw and vpextrb instructions
consistent with Intel manual. Add support for decoding a variant of vpextrw
instruction with opcode 0x15.
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: add rorx to vexw table
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: fix decoding of dpps and add vdpps instruction
Signed-off-by: koltunov <koltunov@ispras.ru>
* x86: fix decoding of pcmpestrm and add vpcmpestrm instruction
Kirill Batuzov [Fri, 31 May 2024 22:14:31 +0000 (01:14 +0300)]
x86: handle disambiguation between XOP prefix and POP instruction (#1754)
0x8f can be either the first byte of XOP prefix, or the opcode of POP instruction. The disambiguation is resolved by map_select field of XOP's second byte. If it is XOP prefix, than the field should be from [0x8, 0x1f] range. Otherwise it is ModRM byte, and 0x8f is an opcode. The only instruction with this opcode is POP, and it requires Reg filed of ModRM to be 0.
Kirill Batuzov [Fri, 31 May 2024 21:00:20 +0000 (00:00 +0300)]
x86: support XOP multiply-accumulate instructions (#1752)
Support decoding of XOP instructions from multiply-and-accumulate group. They were partially supported before. There were IDs for them and one variant was present in decoding tables.
Kirill Batuzov [Sun, 26 May 2024 16:43:46 +0000 (19:43 +0300)]
x86: check that opcode supports VEX/EVEX prefix if it is present (#1746)
Dyninst recognizes invalid combinations of VEX/EVEX prefixes and opcodes as valid instructions. The "&& false" check was introduced in 39caf8e and most probably is some debugging change that slipped into the main code by accident.
Tim Haines [Wed, 10 Apr 2024 15:39:45 +0000 (10:39 -0500)]
Disable -Wdeprecated-declarations for Boost on clang > 17 (#1723)
It's not clear why, but clang 18 and 19 do not correctly detect that
/usr/include/boost is a system directory, and it emits warnings for
use of deprecated std::unary_function.
* Use cmake's GNUInstallDirs to get the lib, bin and include directory
names instead of always using 'lib', 'bin', and 'include'. This
results in two changes to the installation:
- lib directory becomes 'lib64' on platforms where this is the
convention
- the lib, bin and include may be overwritten using the cmake
variables CMAKE_INSTALL_BINDIR, CMAKE_INSTALL_LIBDIR and
CMAKE_INSTALL_INCLUDEDIR respectively
* Update github workflows to handle the lib install dir lib64:
- use Dyninst_ROOT instead of Dyninst_DIR as it searches for the
directory used
- for non-cmake uses search for lib* to find either lib or lib64
openFileWhenNotBusy: 23aaa1c7a in 2006
waitForFileToExist: e016bde56 in 2014
uiHash: f4613dcfe in 2008
CThash: 7a737b6a0 in 2010
intHash: f8dda5e2d in 2010
ptrHash4 added by 102d5c674 in 2005, but never implemented
ptrHash16 added by 102d5c674 in 2005, but never implemented
Tim Haines [Mon, 11 Mar 2024 18:18:29 +0000 (13:18 -0500)]
MachRegister: Add interface for collecting and retrieving all registers (#1703)
This makes writing ABI rules much simpler. It could also be useful for
some power users. The registers returned are in the order they are
declared in common/h/registers/<arch>_regs.h.
Names are only save the register when a name is given because
the other constructor is used to convert registers (e.g., getBaseRegister)
and would create duplicates entries since the name isn't changed.
Kirill Batuzov [Fri, 1 Mar 2024 20:27:22 +0000 (23:27 +0300)]
Add CodeObject::parse overloads to accept multiple targets
Parser::parse_at takes only one target at a time. This has two repercussions:
1) It can't take full advantage of parallel parsing when there are multiple targets in need of it.
2) It still enters and exits OMP parallel loop. This operation has its own performance overhead that
depends on the host system (number of processors and OMP configuration). This overhead can be very significant.
This change introduces Parser::parse_vec that takes a vector of targets and parses them in parallel.
When there are significant number of parse_at calls, performance gains from migrating to parse_vec can be huge. Parsing what initial parse() missed in libLLVM-12.so.1 with parse_at took nearly 20 minutes on 4-core hyper-threaded
CPU. Doing the same with parse_vec took less than 4 minutes. On 128-bit ARM64 server we've seen even bigger gains
(from around 40 minutes to less than 3).
kupsch [Thu, 29 Feb 2024 23:12:39 +0000 (17:12 -0600)]
release 13.0.0 versions & docs (#1695)
- update dyninst version
- update CHANGELOG.md
- produce manuals with updated release dates and versions
- fix .tex files to eliminate latex errors:
- invalid char in symtabAPI/doc/API/Types/Type.tex
- invalid char in parseAPI/doc/API/Function.tex
- invalid char in patchAPI/doc/section/4_api_public.tex
- invlide line break in parseAPI/doc/API/CodeObject.tex
- restore parseAPI example code needed by docs removed in 6c2e31c0
Co-authored-by: James Kupsch <kupsch@vmbp15.local>
Tim Haines [Tue, 27 Feb 2024 20:41:36 +0000 (14:41 -0600)]
Remove explicit check for system calls in parse_frame_one_iteration (#1691)
165f19cd and 091929d6 changed the parsing semantics of system calls
such that software interrupts (e.g., `int` on x86) are always
interpreted as system calls. The `hasCFT()` check on line 1824 now
covers all of the system call cases because it considers those
instructions to have a control flow target (CFT).
Its non-use was verified against /usr/libx32/libc.so.6,
/usr/lib/i386-linux-gnu/libc.so.6, /usr/lib/x86_64-linux-gnu/libc.so.6,
and /usr/lib32/libc.so.6 on Ubuntu 22.04.
Tim Haines [Mon, 26 Feb 2024 20:16:44 +0000 (14:16 -0600)]
Add CMake option to control symbol visibility (#1688)
Currently, all symbols are hidden by default and
then explicitly made visible. This is the behavior
we want for publishing Dyninst libraries, but unit
testing the internal functionality requires access
to these symbols. This option allows that.
Tim Haines [Mon, 26 Feb 2024 16:38:05 +0000 (10:38 -0600)]
Improve syscall and interrupt instruction detection (#1686)
* Treat x86 software interrupts as system calls
* Correct detection of Linux vsyscall for 32-bit code
The existing code did not work because the Operand formatter uses AT&T
syntax and doesn't convert hex to decimal, so the '== "16"' check
always failed.
The convoluted logic in the visitor is needed because Dyninst does not
generate AST for segment registers. Yet, it _does_ record if they are
read/written.
The AST for the 'gs' register was made a file scope static because its
initialization would cause some glibc's to throw a
__gnu_cxx::recursive_init_error when using multiple threads.
File deleted by 8bb4aa76a on 2011-02-08
Reintroduced by 976099e5d on 2011-03-18
Removed from dyninstAPI.vcproj by 78e8ab184 on 2011-04-29
Refers to header files renamed by 91246b9ca on 2011-05-12
Tim Haines [Wed, 10 Jan 2024 20:34:44 +0000 (14:34 -0600)]
GithubCI: only build hpctoolkit@develop (#1667)
Building the HEAD of dynininst against the last release of HPCToolkit
is a good idea for tracking breaking changes, but it ultimately
produced more noise than signal. Making sure that HPCToolkit's latest
source will compile with Dyninst's latest source is likely a better
measure.
Tim Haines [Tue, 9 Jan 2024 22:39:36 +0000 (16:39 -0600)]
Fix libstdc++ noexcept requirement for Operand ctor (#1663)
As you can see below, std::constuct_at is requiring that Operand be
noexcept constructible. I _think_ this is a QoI item in libstdc++.
1. The offending call to std::vector::resize(size_type) at
RoseInsnFactory.C:152 is covered by the note in
(https://en.cppreference.com/w/cpp/container/vector/resize):
In overload (1), if T's move constructor is not noexcept and T is not
CopyInsertable into *this, vector will use the throwing move
constructor. If it throws, the guarantee is waived and the effects
are unspecified.
2. Operand's ctor is _not_ noexcept, but it _is_ CopyInsertable
(https://en.cppreference.com/w/cpp/named_req/CopyInsertable), so we
get the second part and encounter UB.
3. A note on CopyInsertable says that a CopyInsertable must use
std::construct_at (see cppref page above), and std::construct_at has
a caveat of behavior (https://en.cppreference.com/w/cpp/memory/construct_at):
Specialization of this function template participates in overload
resolution only if
::new(std::declval<void*>()) T(std::declval<Args>()...) is well-formed
in an unevaluated context.
From (1), we would get UB in constexpr context, but
RoseInsnFactory.C:152 isn't in a constexpr context... We have to use
std::construct_at by (2). I think the QoI issue is that (3) gets
enforced even though we aren't in a constexpr context.
In file included from /usr/include/c++/12/bits/char_traits.h:46,
from /usr/include/c++/12/string:40,
from /dyninst/src/common/h/entryIDs.h:34,
from /dyninst/src/dataflowAPI/src/RoseInsnFactory.h:34,
from /dyninst/src/dataflowAPI/src/RoseInsnFactory.C:30:
/usr/include/c++/12/bits/stl_construct.h: In instantiation of 'constexpr decltype (::new(void*(0)) _Tp) std::construct_at(_Tp*, _Args&& ...) [with _Tp = Dyninst::InstructionAPI::Operand; _Args = {}; decltype (::new(void*(0)) _Tp) = Dyninst::InstructionAPI::Operand*]':
/usr/include/c++/12/bits/stl_construct.h:115:21: required from 'constexpr void std::_Construct(_Tp*, _Args&& ...) [with _Tp = Dyninst::InstructionAPI::Operand; _Args = {}]'
/usr/include/c++/12/bits/stl_uninitialized.h:638:18: required from 'static constexpr _ForwardIterator std::__uninitialized_default_n_1<_TrivialValueType>::__uninit_default_n(_ForwardIterator, _Size) [with _ForwardIterator = Dyninst::InstructionAPI::Operand*; _Size = long unsigned int; bool _TrivialValueType = false]'
/usr/include/c++/12/bits/stl_uninitialized.h:701:20: required from 'constexpr _ForwardIterator std::__uninitialized_default_n(_ForwardIterator, _Size) [with _ForwardIterator = Dyninst::InstructionAPI::Operand*; _Size = long unsigned int]'
/usr/include/c++/12/bits/stl_uninitialized.h:766:44: required from 'constexpr _ForwardIterator std::__uninitialized_default_n_a(_ForwardIterator, _Size, allocator<_Tp>&) [with _ForwardIterator = Dyninst::InstructionAPI::Operand*; _Size = long unsigned int; _Tp = Dyninst::InstructionAPI::Operand]'
/usr/include/c++/12/bits/vector.tcc:644:35: required from 'constexpr void std::vector<_Tp, _Alloc>::_M_default_append(size_type) [with _Tp = Dyninst::InstructionAPI::Operand; _Alloc = std::allocator<Dyninst::InstructionAPI::Operand>; size_type = long unsigned int]'
/usr/include/c++/12/bits/stl_vector.h:1011:4: required from 'constexpr void std::vector<_Tp, _Alloc>::resize(size_type) [with _Tp = Dyninst::InstructionAPI::Operand; _Alloc = std::allocator<Dyninst::InstructionAPI::Operand>; size_type = long unsigned int]'
/dyninst/src/dataflowAPI/src/RoseInsnFactory.C:152:20: required from here
/usr/include/c++/12/bits/stl_construct.h:95:14: error: noexcept-expression evaluates to 'false' because of a call to 'Dyninst::InstructionAPI::Operand::Operand(Dyninst::InstructionAPI::Expression::Ptr, bool, bool, bool, bool, bool)' [-Werror=noexcept]
95 | noexcept(noexcept(::new((void*)0) _Tp(std::declval<_Args>()...)))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /dyninst/src/instructionAPI/h/Instruction.h:43,
from /dyninst/src/dataflowAPI/src/RoseInsnFactory.h:40:
/dyninst/src/instructionAPI/h/Operand.h:69:16: note: but 'Dyninst::InstructionAPI::Operand::Operand(Dyninst::InstructionAPI::Expression::Ptr, bool, bool, bool, bool, bool)' does not throw; perhaps it should be declared 'noexcept'
69 | explicit Operand(Expression::Ptr val = {}, bool read = false, bool written = false, bool implicit = false,
| ^~~~~~~
cc1plus: all warnings being treated as errors
gmake[2]: *** [parseAPI/CMakeFiles/parseAPI.dir/build.make:678: parseAPI/CMakeFiles/parseAPI.dir/__/dataflowAPI/src/RoseInsnFactory.C.o] Error 1
gmake[2]: *** Waiting for unfinished jobs....
gmake[1]: *** [CMakeFiles/Makefile2:471: parseAPI/CMakeFiles/parseAPI.dir/all] Error 2
gmake: *** [Makefile:136: all] Error 2
Error: Process completed with exit code 2.
Tim Haines [Wed, 13 Dec 2023 17:25:42 +0000 (11:25 -0600)]
Clean up InstructionAPI::Operation (#1643)
* Merge InstructionAPI::Operation and InstructionAPI::Operation_impl
The only place the impl is used is by Operation, so there's no need to
have them separate. This makes it easier to look up member functions
for Operation.
* Remove operator==
It's neither used nor documented. 'hash_value' is only used here, so
remove it, as well.
Tim Haines [Tue, 5 Dec 2023 18:05:48 +0000 (12:05 -0600)]
Set new CMake policy for upper-case <NAME>_ROOT variables (#1642)
In CMake 3.27 and above the find_package(<PackageName>) command now
searches prefixes specified by the upper-case <PACKAGENAME>_ROOT CMake
variable and the <PACKAGENAME>_ROOT environment variable in addition to
the case-preserved <PackageName>_ROOT and <PackageName>_ROOT variables
used since policy CMP0074. This policy provides compatibility with
projects that have not been updated to avoid using <PACKAGENAME>_ROOT
variables for other purposes.
The OLD behavior for this policy is to ignore <PACKAGENAME>_ROOT
variables if the original <PackageName> has lower-case characters. The
NEW behavior for this policy is to use <PACKAGENAME>_ROOT variables.
Tim Haines [Wed, 29 Nov 2023 01:00:07 +0000 (19:00 -0600)]
Synchronize x86 mnemonics with Capstone (#1634)
* Create Capstone import script
This currently only supports x86, but can be readily expanded to the
other architectures.
* Remove invalid opcodes
Some of these are used to label subtypes of the general
instruction and some are just madeup mnemonics that were never
used in Dyninst.
* Move pseudo-mnemonics to top of file
This makes them easier to see.
* Remove AT&T aliases
* Replace fstcw with fnstcw
* Replace fstenv with fnstenv
* Replace fstsw with fnstsw
* Replace fsave with fnsave
The fstX instructions are actually aliases for 'waitf' followed by
the fnstX variant. There's no need to have both.
* Rename loopn -> loopne
loopn isn't a valid mnemonic for 0xE0.
* Remove e_jmpe
The opcode 0x0FB8 is decoded as popcnt unless the preceeding byte is
0xF3. However, not even Xed decodes this instruction. From Table A-3 of
the June 2021 Intel SDM:
There's no real concensus, but Capstone and Xed use shl.
* Rename e_ud -> e_ud0
* Make cmovnbe an alias of cmova
* Make cmovnb an alias of cmovae
* Make cmovnae an alias of cmovb
* Make cmovng an alias of cmovle
* Make cmovnge an alias of cmovl
* Make cmovnl an alias of cmovge
* Make cmovpe an alias of cmovp
* Make cmovpo an alias of cmovnp
* Make cwd an alias of cdq
* Make fcomip an alias of fcompi
* Make fucomip an alias of fucompi
* Make jnb an alias of jae
* Make jnbe an alias of ja
* Make jnl an alias of jge
* Make jnle an alias of jg
* Make jnz an alias of jne
* Make jz an alias of je
* Make jrcxz an alias of jcxz
* Make lods an alias of lodsb
* Make popa an alias of popal
popal isn't a valid mnemonic, but it's what Capstone uses.
* Make popad an alias of popaw
popaw isn't a valid mnemonic, but it's what Capstone uses.
* Make pushad, pusha, and pushaw aliases of pushal
pushal isn't a valid mnemonic, but it's what Capstone uses.
* Make pushfd an alias of pushf
* Make setnb an alias of setae
* Make setnbe an alias of seta
* Make setnl an alias of setge
* Make setnle an alias of setg
* Make setnz an alias of setne
* Make setz an alias of sete
* Make xlat an alias of xlatb
Tim Haines [Tue, 28 Nov 2023 18:49:09 +0000 (12:49 -0600)]
Add x86_{i386,64} memory-management and x87 control/status registers (#1636)
* Add the memory-management registers
The processor provides four memory-management registers (GDTR, LDTR,
IDTR, and TR) that specify the locations of the data structures which
control segmented memory management. See Section 2.4 in Volume 3 of
the Intel 64 and IA-32 Architectures Software Developer’s Manual from
June 2021 for details.
* Add mxcsr
This is the SSE Control Status Word register. The AMD64
ABI doc says it's 128 bits, but it's actually 32.
* Add x87/SSE/AVX control and status word registers
Without these, getBaseRegister will convert fcw, fsw, and mxcsr to a
register with category '<id> | W_REG | ST | Arch_x86_64' which is
incorrect. getBaseRegister should return the register unmodified.
Tim Haines [Tue, 21 Nov 2023 20:59:06 +0000 (14:59 -0600)]
Clean up and improve documentation of x86_32 registers (#1629)
* Improve comments for register lengths
* Separate MMX/3DNow! and x87 register lengths and categories
The MMX* registers are only the lower 64 bits of the st* ones.
* Improve comments for EFLAGS fields
* Add conversion to ROSE register for FLAGC
FLAGC is the lower bit of the I/O Permission Level field in EFIELD.
* Add conversion to ROSE register for FLAGD
FLAGC is the upper bit of the I/O Permission Level field in EFIELD.
* Add conversion to ROSE register for Nested Task flag
* Add conversion to ROSE register for Resume Flag
* Add missing Virtual-8086 mode (VM) EFLAGS field
* Add missing Alignment Check/Access Control (AC) EFLAGS field
* Add missing Virtual Interrupt Flag (VIF) EFLAGS field
* Add missing Virtual Interrupt Pending (VIP) EFLAGS field
* Add missing ID Flag (ID) EFLAGS field
* Remove registers xmm8-xmm31 and aliases
These registers are only available in 64-bit mode.
From Intel(r) 64 and IA-32 Architectures Software Developer’s Manual
June 2021:
11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE2 extensions function like they do in
protected mode. In 64-bit mode, eight additional XMM registers are
accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.
14.1.1 256-Bit Wide SIMD Register Support
Intel AVX introduces support for 256-bit wide SIMD registers
(YMM0-YMM7 in operating modes that are 32-bit or less, YMM0-YMM15 in
64-bit mode).
15.1.2 32 SIMD Register Support
Intel AVX-512 instructions also support 32 SIMD registers in 64-bit
mode (XMM0-XMM31, YMM0-YMM31 and ZMM0-ZMM31). The number of available
vector registers in 32-bit mode is still 8.
* Fix avx-512 opmask size.
It's 64 bits, not 128.
From Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
June 2021
15.6.1 OPMASK Register to Predicate Vector Data Processing
The opmask is a set of eight architectural registers of size
MAX_KL (64-bit).
* Rename OCT to XMMS
This makes it consistent with the names used for the other vector
extensions.
* Use symbolic names for the segment register base IDs
* Add missing ROSE category conversions
* Add missing ROSE subrange conversions
* Preserve register number in getBaseRegister
* Clear whole subrange byte for GPRs in getBaseRegister
git://sourceware.org / dyninstfans.git / log