Mark Wielaard [Sun, 7 Feb 2021 23:25:52 +0000 (00:25 +0100)]
PR140939 --track-fds reports leakage of stdout/in/err and doesn't respect -q
Make --track-fds=yes not report on file descriptors 0, 1, and 2 (stdin,
stdout, and stderr) by default. Add a new option --track-fds=all that does
report on the std file descriptors still being open. Update testsuite and
documentation.
Original patch by Peter Kelly <pmk@cs.adelaide.edu.au>
Updated by Daniel Fahlgren <daniel@fahlgren.se>
https://bugs.kde.org/show_bug.cgi?id=140939
Mark Wielaard [Sat, 6 Feb 2021 21:02:56 +0000 (22:02 +0100)]
PR140178 Support opening /proc/self/exe
Some programs open /proc/self/exe to read some data. Currently valgrind
supports following the /proc/self/exe link (to the original binary, so you
could then open that), but directly opening /proc/self/exe will open the
valgrind tool, not the executable file itself.
Add ML_(handle_self_exe_open) which dups VG_(cl_exec_fd) if the file
to open is /proc/self/exe or /proc/<pid>/exe. And do the same for openat.
https://bugs.kde.org/show_bug.cgi?id=140178
Mark Wielaard [Thu, 4 Feb 2021 16:21:56 +0000 (17:21 +0100)]
PR423361 Adds io_uring support on arm64/aarch64 (and all other arches)
io_uring syscalls only work on x86/amd64, but they can be enabled on
all arches. Based on a patch by Nathan Ringo <nathan@remexre.xyz>.
https://bugs.kde.org/show_bug.cgi?id=423361
Mark Wielaard [Thu, 4 Feb 2021 15:14:00 +0000 (16:14 +0100)]
PR422261 platform selection fails for unqualified client name
Bug introduced with commit
f15beea76
"Fix memory leak in launcher-linux.c"
Need to try opening the actual 'client' path, not just the 'clientname'
file name.
Reported-by: Michael Wojcik <michael.wojcik@microfocus.com>
https://bugs.kde.org/show_bug.cgi?id=422261
Mark Wielaard [Wed, 3 Feb 2021 15:56:14 +0000 (16:56 +0100)]
syswrap-linux.c: Pass implicit VKI_IPC_64 for shmctl also on arm64.
The shmctl syscall on amd64, arm64 and riscv (but we don't have a port
for that last one) always use IPC_64. Explicitly pass it to the generic
PRE/POST handlers so they select the correct (64bit) data structures on
those architectures.
https://bugzilla.redhat.com/show_bug.cgi?id=
1909548
Anssi Hannula [Thu, 2 Jul 2020 11:49:17 +0000 (14:49 +0300)]
Fix shmat() on Linux nanomips and x86
On Linux, there are two variants of the direct shmctl syscall:
- sys_shmctl: always uses shmid64_ds, does not accept IPC_64
- sys_old_shmctl: uses shmid_ds or shmid64_ds depending on IPC_64
The following Linux ABIs have the sys_old_shmctl variant:
alpha, arm, microblaze, mips n32/n64, xtensa
Other ABIs (and future ABIs) have the sys_shmctl variant, including ABIs
that only got sys_shmctl in Linux 5.1 (such as x86, mips o32, ppc,
s390x).
We incorrectly assume the sys_old_shmctl variant on nanomips and x86,
causing shmat() calls under valgrind to fail with EINVAL.
On x86, the issue was previously masked by the non-existence of
__NR_shmctl until
a9fc7bceeb0b0 ("Update Linux x86 system call number
definitions") in 2019.
On mips o32, ppc, and s390x this issue is not visible as our headers do
not have __NR_shmctl for those ABIs (396 since Linux 5.1).
Fix the issue by correcting the preprocessor check in get_shm_size() to
only assume the old Linux sys_old_shmctl behavior on the specific
affected platforms.
Also, exclude the use of direct shmctl entirely on Linux x86, ppc,
mips o32, s390x in order to keep compatibility with pre-5.1 kernel
versions that did not yet have direct shmctl for those ABIs.
This currently only has actual effect on x86 as only it has __NR_shmctl
in our headers.
Fixes tests mremap4, mremap5, mremap6.
https://bugs.kde.org/show_bug.cgi?id=410743
Mark Wielaard [Mon, 1 Feb 2021 21:46:43 +0000 (22:46 +0100)]
Handle Iop_NegF16, Iop_AbsF16 and Iop_SqrtF16 as non-trapping.
Add Iop_NegF16, Iop_AbsF16 and Iop_SqrtF16 to VEX/priv/ir_defs.c
primopMightTrap. Also rewrite case statement slightly so GCC will warn
if an enumeration value is missed.
Assad Hashmi [Fri, 29 Jan 2021 13:38:40 +0000 (08:38 -0500)]
Bug 432161 Addition of arm64 v8.2 FADDP, FNEG and FSQRT
This patch adds FP half-precision support for the following:
FABS <Hd>, <Hn>
FABS <Vd>.<T>, <Vn>.<T>
FNEG <Hd>, <Hn>
FNEG <Vd>.<T>, <Vn>.<T>
FSQRT <Hd>, <Hn>
FSQRT <Vd>.<T>, <Vn>.<T>
Fixes https://bugs.kde.org/show_bug.cgi?id=432161
Mark Wielaard [Mon, 25 Jan 2021 14:33:34 +0000 (15:33 +0100)]
Add support for DWARF5 as produced by GCC11
Implement DWARF5 in readdwarf.c and readdwarf3.c
Since gcc11 will default to DWARF5 by default it is time for
valgrind to support it. The patch handles everything gcc11 produces
(except for the new DWARF expressions).
There is some duplication in the patch since we actually have two DWARF
readers which use slightly different abstractions (Slices vs Cursors).
It would be nice if we could merge these somehow. The reader in
readdwarf3.c is only used when --read-var-info=yes is used (which
drd uses to provide the allocation context).
The handling of DW_FORM_implicit_const is tricky with the current design.
An abbrev which contains an attribute encoded with DW_FORM_implicit_const
has its value also in the abbrev. The code in readdwarf3.c assumed it
always could simply get the data from the .debug_info/current Cursor.
For now I added a value field to the name_form field that holds the
associated value. This is slightly wasteful since the extra field is
not necessary for other forms.
Tested against GCC10 (defaulting to DWARF4) and GCC11 (defaulting to
DWARF5) on x86_64. No regressions in the regtests.
https://bugs.kde.org/show_bug.cgi?id=432102
Mark Wielaard [Sat, 23 Jan 2021 20:54:07 +0000 (21:54 +0100)]
Define AT as UChar in VEX/priv/guest_ppc_toIR.c (dis_vsx_accumulator_prefix)
GCC notices that AT is passed around as char, specifically as %u argument
to DIP. But ifieldAT returns an UChar and vsx_matrix_ger takes AT as UChar.
This causes lots of format string warnings when building with GCC11.
Simply declare AT as UChar instead of char.
Mark Wielaard [Sat, 23 Jan 2021 19:22:28 +0000 (20:22 +0100)]
Fix indentation in coregrind/m_debuginfo/readpdb.c (DEBUG_SnarfLinetab)
GCC warns:
readpdb.c:1631:16: warning: this 'if' clause does not guard...
[-Wmisleading-indentation]
1631 | if (debug)
| ^~
In file included from ./pub_core_basics.h:38,
from m_debuginfo/readpdb.c:38:
../include/pub_tool_basics.h:69:30: note: ...this statement, but the latter
is misleadingly indented as if it were guarded by the 'if'
69 | #define ML_(str) VGAPPEND(vgModuleLocal_, str)
| ^~~~~~~~~~~~~~
../include/pub_tool_basics.h:66:29: note: in definition of macro 'VGAPPEND'
66 | #define VGAPPEND(str1,str2) str1##str2
| ^~~~
m_debuginfo/readpdb.c:1636:19: note: in expansion of macro 'ML_'
1636 | ML_(addLineInfo)(
| ^~~
The warning message is slightly hard to read because of the macro expansion.
But GCC is right that the indentation is misleading. Fixed by reindenting.
Julian Seward [Fri, 15 Jan 2021 17:46:00 +0000 (18:46 +0100)]
Bug 431556 - Complete arm64 FADDP v8.2 instruction support started in 413547.
Patch from/by Assad Hashmi (assad.hashmi@linaro.org).
Carl Love [Mon, 11 Jan 2021 17:39:23 +0000 (11:39 -0600)]
PPC64: Fix load store instructions
This patch fixes numerous errors in the ISA support.
The word and prefix versions of the instructions do not use the same mask
to extract the immediate values. The prefix instructions should all use
the DFOM_IMMASK.
The parsing of prefix instructions has been fixed to ensure the ISA 3.1
instructions all have the ISA_3_1_PREFIX_CHECK check.
Fixed the commenting to improve the comments for the instruction parsing.
Fixed the parsing of the plxv instruction.
General code cleanup.
Carl Love [Mon, 11 Jan 2021 16:41:47 +0000 (10:41 -0600)]
PPC64: Fix EA calculation for prefixed instructions
The effective address (EA) calculation for the prefixed instructions
concatenate an 18-bit immediate value from the prefix word and a 16-bit
immediate value fro the instruction word. This results in a 34-bit value.
The concatenated value must be stored into a long long int not a 32-bit
integer.
Carl Love [Sun, 10 Jan 2021 02:15:46 +0000 (20:15 -0600)]
PPC64: Fix for VG_MAX_INSTR_SZB, max instruction size is now 8bytes for prefix inst
The ISA 3.1 support has both word instructions of length 4-bytes and prefixed
instruction of length 8-bytes. The following fix is needed when Valgrind
is compiled using an ISA 3.1 compiler.
Julian Seward [Thu, 7 Jan 2021 15:14:29 +0000 (16:14 +0100)]
Fix a couple of comment / crash-message typos. No functional change.
Julian Seward [Thu, 7 Jan 2021 07:34:14 +0000 (08:34 +0100)]
Bug 413547 - regression test does not check for Arm 64 features.
Patches from/by Assad Hashmi (assad.hashmi@linaro.org).
Paul Floyd [Wed, 6 Jan 2021 09:57:11 +0000 (10:57 +0100)]
Bug 391853 - Makefile.all.am:L247 and @SOLARIS_UNDEF_LARGESOURCE@ being empty
Julian Seward [Mon, 4 Jan 2021 14:16:41 +0000 (15:16 +0100)]
arm64 isel: in a couple places, use `xzr` as a source rather than loading zero into a reg.
Reduces code size by 0.27% for /usr/bin/date.
Julian Seward [Mon, 4 Jan 2021 12:33:24 +0000 (13:33 +0100)]
arm64 insn selector: improved handling of Or1/And1 trees.
This is the exact analog of
cadd90993504678607a4f95dfe5d1df5207c1eb0, to the
point of almost being a copy-n-paste. That commit split (amd64) iselCondCode
into two functions, iselCondCode_C (existing) and iselCondCode_R (new). The
latter computes an I1-typed expression into a register rather than a condition
code. The two functions cooperate so as to minimise between conversions between
a condition-code value and a value in a register.
Julian Seward [Sat, 2 Jan 2021 16:18:53 +0000 (17:18 +0100)]
More arm64 isel tuning: create {and,orr,eor,add,sub} reg,reg,reg-shifted-by-imm
Thus far the arm64 isel can't generate instructions of the form
{and,or,xor,add,sub} reg,reg,reg-shifted-by-imm
and hence sometimes winds up generating pairs like
lsh x2, x1, #13 ; orr x4, x3, x2
when instead it could just have generated
orr x4, x3, x1, lsh #13
This commit fixes that, although only for the 64-bit case, not the 32-bit
case. Specifically, it can transform the IR forms
{Add,Sub,And,Or,Xor}(E1, {Shl,Shr,Sar}(E2, immediate)) and
{Add,And,Or,Xor}({Shl,Shr,Sar}(E1, immediate), E2)
into a single arm64 instruction. Note that `Sub` is not included in the
second line, because shifting the first operand requires inverting the arg
order in the arm64 instruction, which isn't allowable with `Sub`, since it's
not commutative and arm64 doesn't offer us a reverse-subtract instruction to
use instead.
This gives a 1.1% reduction generated code size when running
/usr/bin/date on Memcheck.
Julian Seward [Sat, 2 Jan 2021 15:15:03 +0000 (16:15 +0100)]
A bit of tuning of the arm64 isel: do PUT(..) = 0x0:I64 in a single insn.
When running Memcheck, most blocks will do one and often two of `PUT(..) =
0x0:I64`, as a result of the way the front end models arm64 condition codes.
The arm64 isel would generate `mov xN, #0 ; str xN, [xBaseblock, #imm]`,
which is pretty stupid. This patch changes it to a single insn:
`str xzr, [xBaseblock, #imm]`.
This is a special-case for `PUT(..) = 0x0:I64`. General-case integer stores
of 0x0:I64 are unchanged.
This gives a 1.9% reduction in generated code size when running
/usr/bin/date on Memcheck.
Paul Floyd [Wed, 30 Dec 2020 12:57:39 +0000 (13:57 +0100)]
Add an extra suppression.
On Fedora 33 with gcc (GCC) 10.2.1
20201125 (Red Hat 10.2.1-9)
it looks like fun:__static_initialization_and_destruction_0 is
now inlined which causes the existing suppression for the
same reachable to no longer match.
Mark Wielaard [Tue, 22 Dec 2020 13:51:15 +0000 (14:51 +0100)]
expr_is_guardable doesn't handle Iex_Qop
IRExpr_Qop uses the Iex_Qop tag, which expr_is_guardable didn't handle.
https://bugs.kde.org/show_bug.cgi?id=430485
Julian Seward [Mon, 21 Dec 2020 09:44:52 +0000 (10:44 +0100)]
arm64 front end: sfbm: handle sign-extends explicitly
This is a follow-on to
41504d33dec8773c591d45192d1dda6e9c670031.
For the cases of sfbm that are actually just sign-extensions to a wider width,
emit that directly and do disassembly-printing accordingly. No functional
change.
Laurent Bonnans [Fri, 16 Nov 2018 14:22:18 +0000 (15:22 +0100)]
Fix 397605 - Add support for Linux FICLONE ioctl
Mark Wielaard [Fri, 18 Dec 2020 17:23:42 +0000 (18:23 +0100)]
Fix magic cookie reference in mc-manual.
The URL to the original C++ front-end for GCC internals document
disappeared. Replace it with an URL that still has a description of
the original magic cookie added by operator new [] by that frontend.
Julian Seward [Thu, 17 Dec 2020 16:40:46 +0000 (17:40 +0100)]
arm64 front end: ufbm/sfbm: handle plain shifts explicitly
The ufbm and sfbm instructions implement some kind of semi-magical rotate,
mask and sign/zero-extend functionality. Boring old left and right shifts are
special cases of it. The existing translation into IR is correct, but has the
disadvantage that the IR optimiser isn't clever enough to simplify the
resulting IR back into a single shift in the case where the instruction is
used simply to encode a shift. This induces inefficiency and it also makes
the resulting disassembly pretty difficult to read, if you're into that kind
of thing.
This commit does the obvious thing: detects cases where the required behaviour
is just a single shift, and emits IR and disassembly-printing accordingly.
All other cases fall through to the existing general-case handling and so are
unchanged.
Mark Wielaard [Wed, 14 Oct 2020 10:11:34 +0000 (06:11 -0400)]
arm64 VEX frontend and backend support for Iop_M{Add,Sub}F{32,64}
The arm64 frontend used to implement the scalar fmadd, fmsub, fnmadd
and fnmsub iinstructions into separate addition/substraction and
multiplication instructions, which caused rounding issues.
This patch turns them into Iop_M{Add,Sub}F{32,64} instructions
(with some arguments negated). And the backend now emits fmadd or fmsub
instructions.
Alexandra Hajkova <ahajkova@redhat.com> added tests and fixed up the
implementation to make sure rounding (and sign) are correct now.
https://bugs.kde.org/show_bug.cgi?id=426014
Mark Wielaard [Tue, 15 Dec 2020 10:49:58 +0000 (11:49 +0100)]
ppc stxsibx and stxsihx instructions write too much data
stxsibx (Store VSX Scalar as Integer Byte Indexed X-form) is implemented
by first reading a whole word, merging in the new byte, and then writing
out the whole word. Causing memcheck to warn when the destination might
have room for less than 8 bytes.
The stxsihx (Store VSX Scalar as Integer Halfword Indexed X-form)
instruction does something similar reading and then writing a full
word instead of a half word.
The code can be simplified (and made more correct) by storing the byte
(or half-word) directly, IRStmt_Store seems fine to store byte or half
word sized data, and so seems the ppc backend.
https://bugs.kde.org/show_bug.cgi?id=430354
Julian Seward [Wed, 9 Dec 2020 11:54:45 +0000 (12:54 +0100)]
Bug 414268 - Enable AArch64 feature detection and decoding for v8.x instructions (where x>0).
Patch from Assad Hashmi <assad.hashmi@linaro.org>.
Paul Floyd [Wed, 9 Dec 2020 07:55:55 +0000 (08:55 +0100)]
Initial change for Bug 429952 didn't work well with older GCC. Use the __clang__ macro instead.
Paul Floyd [Tue, 8 Dec 2020 20:29:43 +0000 (21:29 +0100)]
Fix dhat/tests/copy on Solaris
Andreas Arnez [Mon, 7 Dec 2020 19:01:26 +0000 (20:01 +0100)]
Bug 404076 - s390x: Implement z14 vector instructions
Implement the new instructions/features that were added to z/Architecture
with the vector-enhancements facility 1. Also cover the instructions from
the vector-packed-decimal facility that are defined outside the chapter
"Vector Decimal Instructions", but not the ones from that chapter itself.
For a detailed list of newly supported instructions see the updates to
`docs/internals/s390-opcodes.csv'.
Since the miscellaneous instruction extensions facility 2 was already
addressed by Bug 404406, this completes the support necessary to run
general programs built with `--march=z14' under Valgrind. The
vector-packed-decimal facility is currently not exploited by the standard
toolchain and libraries.
Paul Floyd [Tue, 8 Dec 2020 14:07:29 +0000 (15:07 +0100)]
Bug 408663 - Patch: Suppression file for musl libc
Paul Floyd [Tue, 8 Dec 2020 13:59:49 +0000 (14:59 +0100)]
Bug 429952 - Errors when building regtest with clang
Mark Wielaard [Tue, 8 Dec 2020 11:00:44 +0000 (12:00 +0100)]
dhat/tests/Makefile.am: Add filter_copy to dist_noinst_SCRIPTS
Make sure that make dist includes all needed test filters.
Mark Wielaard [Tue, 8 Dec 2020 10:52:08 +0000 (11:52 +0100)]
check_headers_and_includes: Add dhat/dhat.h to tool_export_header
dhat now has a public header dhat/dhat.h, this header may include
valgrind.h directly. Make sure check_headers_and_includes knows.
Andreas Arnez [Thu, 3 Dec 2020 17:32:45 +0000 (18:32 +0100)]
Bug 429864 - s390: Use Iop_CasCmp* to fix memcheck false positives
Compare-and-swap instructions can cause memcheck false positives when
operating on partially uninitialized data. An example is where a 1-byte
lock is allocated on the stack and then manipulated using CS on the
surrounding word. This is correct, and the uninitialized data has no
influence on the result, but memcheck still complains.
This is caused by logic in the s390 backend, where the expected and actual
memory values are compared using Iop_Sub32. Fix this by using
Iop_CasCmpNE32 instead.
Nicholas Nethercote [Mon, 9 Sep 2019 04:13:35 +0000 (14:13 +1000)]
Add support for copy and ad hoc profiling to DHAT.
Paul Floyd [Fri, 4 Dec 2020 09:11:55 +0000 (10:11 +0100)]
Bug 428909 - helgrind: need to intercept duplicate libc definitions for Fedora 33
Nicholas Nethercote [Wed, 2 Dec 2020 05:21:23 +0000 (16:21 +1100)]
Add a comment to previous commit.
Nicholas Nethercote [Wed, 2 Dec 2020 05:18:06 +0000 (16:18 +1100)]
Fix wcscpy wrapper.
wcscpy deals with wchar_t, which has a size of 4, so the adjustment in
the wrapper must be +4 instead of +1.
Mark Wielaard [Tue, 1 Dec 2020 13:57:39 +0000 (14:57 +0100)]
lmw, lswi and related PowerPC insns aren't allowed on ppc64le
Newer binutils produce an error when the assembly contains lmw, stmw,
lswi, lswx, stswi, or stswx instructions in little-endian mode.
Only build and run the lsw and ldst_multiple testcases on ppc64[be].
https://bugs.kde.org/show_bug.cgi?id=427870
Nicholas Nethercote [Tue, 1 Dec 2020 02:46:25 +0000 (13:46 +1100)]
Fix an obscure problem with peak finding.
Currently, if there are multiple equal global peaks, `intro_Block` and
`resize_Block` record the first one while `check_for_peak` records the
last one. This could lead to inconsistent output, though it's unlikely
in practice.
This commit fixes things so that all functions record the last peak.
Mark Wielaard [Fri, 27 Nov 2020 11:53:18 +0000 (12:53 +0100)]
Hook up unhandled ppc64le-linux syscall: 147 (getsid)
https://bugs.kde.org/show_bug.cgi?id=429692
Carl Love [Thu, 12 Nov 2020 21:18:23 +0000 (15:18 -0600)]
PowerPC, fix for conv_f16_to_double xscvhpdp assembler code
The previous commit:
commit
eb82a294573d15c1be663673d55b559a82ca29d3
Author: Julian Seward <jseward@acm.org>
Date: Tue Nov 10 21:10:48 2020 +0100
Add a missing ifdef, whose absence caused build breakage on non-POWER targets.
fixed the compile issue in conv_f16_to_double() where non-Power platforms
do not support the power xscvhpdp assembly instructions. The instruction
is supported by ISA 3.0 platforms. Older Power platforms still fail to
compile with the assembly instruction. This patch fixes the if def for
power systems that do not support ISA 3.0.
Julian Seward [Sun, 15 Nov 2020 17:28:09 +0000 (18:28 +0100)]
memcheck: on arm64, use expensive instrumentation for Cmp{EQ,NE}64 by default.
Julian Seward [Tue, 10 Nov 2020 20:10:48 +0000 (21:10 +0100)]
Add a missing ifdef, whose absence caused build breakage on non-POWER targets.
Carl Love [Tue, 6 Oct 2020 17:14:45 +0000 (12:14 -0500)]
Reduced Precision Outer Product Operation tests
Carl Love [Tue, 29 Sep 2020 18:29:34 +0000 (13:29 -0500)]
Fix, add ISA 3.1 check to set ISA 3.1 in Valgrind hwcaps value
Carl Love [Fri, 25 Sep 2020 21:54:12 +0000 (16:54 -0500)]
ISA 3.1 Reduced-Precision: Outer Product Operations
Add support for:
pmxvf16ger2 Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update)
pmxvf16ger2nn Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) (Negative multiply, Negative accumulate)
pmxvf16ger2np Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) (Negative multiply, Positive accumulate)
pmxvf16ger2pn Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) (Positive multiply, Negative accumulate)
pmxvf16ger2pp Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) (Positive multiply, Positive accumulate)
pmxvf32ger Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update)
pmxvf32gernn Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) (Negative multiply, Negative accumulate)
pmxvf32gernp Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) (Negative multiply, Positive accumulate)
pmxvf32gerpn Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) (Positive multiply, Negative accumulate)
pmxvf32gerpp Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) (Positive multiply, Positive accumulate)
pmxvf64ger Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update)
pmxvf64gernn Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) (Negative multiply, Negative accumulate)
pmxvf64gernp Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) (Negative multiply, Positive accumulate)
pmxvf64gerpn Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) (Positive multiply, Negative accumulate)
pmxvf64gerpp Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) (Positive multiply, Positive accumulate)
pmxvi16ger2s Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation
pmxvi16ger2spp Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation (Positive multiply, Positive accumulate)
pmxvi4ger8 Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update)
pmxvi4ger8pp Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) (Positive multiply, Positive accumulate)
pmxvi8ger4 Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
pmxvi8ger4pp Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) (Positive multiply, Positive accumulate)
xvf16ger2 VSX Vector 16-bit Floating-Point GER (rank-2 update)
xvf16ger2nn VSX Vector 16-bit Floating-Point GER (rank-2 update) (Positive multiply, Positive accumulate)
xvf16ger2np VSX Vector 16-bit Floating-Point GER (rank-2 update) (Negative multiply, Positive accumulate)
xvf16ger2pn VSX Vector 16-bit Floating-Point GER (rank-2 update) (Positive multiply, Negative accumulate)
xvf16ger2pp VSX Vector 16-bit Floating-Point GER (rank-2 update) (Positive multiply, Positive accumulate)
xvf32ger VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn VSX Vector 32-bit Floating-Point GER (rank-1 update) (Negative multiply, Negative accumulate)
xvf32gernp VSX Vector 32-bit Floating-Point GER (rank-1 update) (Negative multiply, Positive accumulate)
xvf32gerpn VSX Vector 32-bit Floating-Point GER (rank-1 update) (Positive multiply, Negative accumulate)
xvf32gerpp VSX Vector 32-bit Floating-Point GER (rank-1 update) (Positive multiply, Positive accumulate)
xvf64ger VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn VSX Vector 64-bit Floating-Point GER (rank-1 update) (Negative multiply, Negative accumulate)
xvf64gernp VSX Vector 64-bit Floating-Point GER (rank-1 update) (Negative multiply, Positive accumulate)
xvf64gerpn VSX Vector 64-bit Floating-Point GER (rank-1 update) (Positive multiply, Negative accumulate)
xvf64gerpp VSX Vector 64-bit Floating-Point GER (rank-1 update) (Positive multiply, Positive accumulate)
xvi16ger2s VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation
xvi16ger2spp VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation (Positive multiply, Positive accumulate)
xvi4ger8 VSX Vector 4-bit Signed Integer GER (rank-8 update)
xvi4ger8pp VSX Vector 4-bit Signed Integer GER (rank-8 update) (Positive multiply, Positive accumulate)
xvi8ger4 VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi8ger4pp VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) (Positive multiply, Positive accumulate)
xxmfacc VSX Move From ACC
xxmtacc VSX Move To ACC
xxsetaccz VSX Set ACC to Zero
Paul Floyd [Tue, 10 Nov 2020 13:49:27 +0000 (14:49 +0100)]
Make memcheck/tests/sized_delete conditional upon the compiler having -fsized-deallocators, add 384729 to NEWS
Carl Love [Tue, 6 Oct 2020 17:06:56 +0000 (12:06 -0500)]
VSX Load/Store rightmost element operation tests
Carl Love [Tue, 6 Oct 2020 17:05:03 +0000 (12:05 -0500)]
Test LSB by Byte operation tests
Carl Love [Tue, 6 Oct 2020 17:01:35 +0000 (12:01 -0500)]
String operation tests
Carl Love [Thu, 30 Apr 2020 15:54:43 +0000 (10:54 -0500)]
ISA 3.1 VSX Load/Store Rightmost Element Operations
Add support for:
lxvrbx Load VSX Vector Rightmost Byte Indexed
lxvrdx Load VSX Vector Rightmost Doubleword Indexed
lxvrhx Load VSX Vector Rightmost Halfword Indexed
lxvrwx Load VSX Vector Rightmost Word Indexed
stxvrbx Store VSX Vector Rightmost Byte Indexed
stxvrdx Store VSX Vector Rightmost Doubleword Indexed
stxvrhx Store VSX Vector Rightmost Halfword Indexed
stxvrwx Store VSX Vector Rightmost Word Indexed
Carl Love [Thu, 30 Apr 2020 15:53:34 +0000 (10:53 -0500)]
ISA 3.1 Test LSB by Byte Operation
Add support for:
xvtlsbb
Carl Love [Sat, 16 May 2020 01:57:24 +0000 (20:57 -0500)]
ISA 3.1 String Operations
Add support for:
vclrlb Vector Clear Leftmost Bytes
vclrrb Vector Clear Rightmost Bytes
vstribl[.] Vector String Isolate Byte Left -Justified
vstribr[.] Vector String Isolate Byte Right -Justified
vstrihl[.] Vector String Isolate Halfword Left -Justified
vstrihr[.] Vector String Isolate Halfword Right -Justified
Carl Love [Tue, 6 Oct 2020 17:01:35 +0000 (12:01 -0500)]
Bit Manipulation Operation tests
Carl Love [Tue, 6 Oct 2020 17:00:07 +0000 (12:00 -0500)]
128-bit Binary Integer Operation tests
Carl Love [Tue, 6 Oct 2020 16:58:44 +0000 (11:58 -0500)]
VSX Scalar Min/Max/Compare Quad-Precision operation tests
Carl Love [Thu, 7 May 2020 01:09:38 +0000 (20:09 -0500)]
ISA 3.1 Bit-Manipulation Operations
Add support for:
cfuged Centrifuge Doubleword
cntlzdm Count Leading Zeros Doubleword under bit Mask
cnttzdm Count Trailing Zeros Doubleword under bit Mask
pdepd Parallel Bits Deposit Doubleword
pextd Parallel Bits Extract Doubleword
vcfuged Vector Centrifuge Doubleword
vclzdm Vector Count Leading Zeros Doubleword under bit Mask
vctzdm Vector Count Trailing Zeros Doubleword under bit Mask
vgnb Vector Gather every Nth Bit
vpdepd Vector Parallel Bits Deposit Doubleword
vpextd Vector Parallel Bits Extract Doubleword
xxeval VSX Vector Evaluate
dependent on RFC2609 patch being applied first.
Carl Love [Thu, 24 Sep 2020 15:29:56 +0000 (10:29 -0500)]
ISA 3.1 128-bit Binary Integer Operations
Add support for:
vmuleud, vmuloud, vmulesd, vmulosd
vextsd2q, vcmpuq, vcmpsq
vcmpequq, vcmpequq., vcmpgtuq, vcmpgtuq., vcmpgtsq, vcmpgtsq.
vrlq, vrlqnm, vlqmi, vslq, vsrq, vsraq
Carl Love [Thu, 30 Apr 2020 15:37:07 +0000 (10:37 -0500)]
ISA 3.1 VSX Scalar Minimum/Maximum/Compare Quad-Precision Operations
Add support for:
xscmpeqqp VSX Scalar Compare Equal Quad-Precision
xscmpgeqp VSX Scalar Compare Greater Than or Equal Quad-Precision
xscmpgtqp VSX Scalar Compare Greater Than Quad-Precision
xsmaxcqp VSX Scalar Maximum Type-C Quad-Precision
xsmincqp VSX Scalar Minimum Type-C Quad-Precision
Paul Floyd [Mon, 9 Nov 2020 15:31:40 +0000 (16:31 +0100)]
Bug 384729 - __libc_freeres inhibits cross-platform valgrind
Paul Floyd [Mon, 9 Nov 2020 15:10:52 +0000 (16:10 +0100)]
Pushed binary by mistake
Paul Floyd [Mon, 9 Nov 2020 08:37:17 +0000 (09:37 +0100)]
Add testcase for C++14 sized delete
Paul Floyd [Mon, 9 Nov 2020 08:30:31 +0000 (09:30 +0100)]
Bug 424012 - fix crash if readv/writev have invalid but not NULL arg2 iovec pointer
Paul Floyd [Sun, 8 Nov 2020 07:00:36 +0000 (08:00 +0100)]
Bug 478716 - cppcheck detects potential leak in VEX/useful/smchash.c
Paul Floyd [Thu, 5 Nov 2020 14:58:23 +0000 (15:58 +0100)]
Fix build on Solaris 11.3 - ar does not like empty object files.
Andreas Arnez [Tue, 3 Nov 2020 17:17:30 +0000 (18:17 +0100)]
Bug 428648 - s390x: Force 12-bit amode for vector loads in isel
Similar to Bug 417452, where the instruction selector sometimes attempted
to generate vector stores with a 20-bit displacement, the same problem has
now been reported with vector loads.
The problem is caused in s390_isel_vec_expr_wrk(), where the addressing
mode is generated with s390_isel_amode() instead of
s390_isel_amode_short(). This is fixed.
Julian Seward [Fri, 30 Oct 2020 16:34:14 +0000 (17:34 +0100)]
arm64 front end: mark a couple of vector load/store insns as "verbose".
Mark
LD3/ST3 (multiple 3-elem structs to/from 3 regs
LD4/ST4 (multiple 4-elem structs to/from 4 regs
as "verbose", since they can generate so much IR that a long sequence
of them causes later stages of the JIT to run out of space.
Bart Van Assche [Wed, 21 Oct 2020 02:40:19 +0000 (19:40 -0700)]
drd: Unbreak the musl build
See also https://bugs.kde.org/show_bug.cgi?id=428035.
Reported-by: Stacy <stacy.gaikovaia@windriver.com>
Fixes:
15330adf7c24 ("drd: Port to Fedora 33")
Mark Wielaard [Fri, 16 Oct 2020 00:55:06 +0000 (02:55 +0200)]
Support new faccessat2 linux syscall (439)
faccessat2 is a new syscall in linux 5.8 and will be used by glibc 2.33.
faccessat2 is simply faccessat with a new flag argument. It has
a common number across all linux arches.
https://bugs.kde.org/427787
Bart Van Assche [Sat, 19 Sep 2020 21:59:06 +0000 (14:59 -0700)]
drd: Update copyright notices
Carl Love [Tue, 6 Oct 2020 16:57:00 +0000 (11:57 -0500)]
SIMD Permute-Class operations powerpc tests
Carl Love [Wed, 13 May 2020 20:29:51 +0000 (15:29 -0500)]
ISA 3.1 SIMD Permute-Class Operations
Add support for:
vxvkq Load VSX Vector Special Value Quadword
vextddvlx Vector Extract Double Dword to VSR Left-Indexed
vextddvrx Vector Extract Double Dword to VSR Right-Indexed
vextdubvlx Vector Extract Double Unsigned Byte to VR Left-Indexed
vextdubvrx Vector Extract Double Unsigned Byte to VR Right-Indexed
vextduhvlx Vector Extract Double Unsigned Hword to VR Left-Indexed
vextduhvrx Vector Extract Double Unsigned Hword to VR Right-Indexed
vextduwvlx Vector Extract Double Unsigned Word to VR Left-Indexed
vextduwvrx Vector Extract Double Unsigned Word to VR Right-Indexed
vinsblx Vector Insert Byte from GPR Left-Indexed
vinsbrx Vector Insert Byte from GPR Right-Indexed
vinsbvlx Vector Insert Byte from VSR Left-Indexed
vinsbvrx Vector Insert Byte from VSR Right-Indexed
vinsd Vector Insert Dword from GPR
vinsdlx Vector Insert Dword from GPR Left-Indexed
vinsdrx Vector Insert Dword from GPR Right-Indexed
vinshlx Vector Insert Hword from GPR Left-Indexed
vinshrx Vector Insert Hword from GPR Right-Indexed
vinshvlx Vector Insert Hword from VSR Left-Indexed
vinshvrx Vector Insert Hword from VSR Right-Indexed
vinsw Vector Insert Word from GPR
vinswlx Vector Insert Word from GPR Left-Indexed
vinswrx Vector Insert Word from GPR Right-Indexed
vinswvlx Vector Insert Word from VSR Left-Indexed
vinswvrx Vector Insert Word from VSR Right-Indexed
vsldbi Vector Shift Left Double by Bit Immediate
vsrdbi Vector Shift Right Double by Bit Immediate
xxblendvb VSX Vector Blend Variable Byte
xxblendvd VSX Vector Blend Variable Dword
xxblendvh VSX Vector Blend Variable Hword
xxblendvw VSX Vector Blend Variable Word
xxpermx VSX Vector Permute Extended
xxsplti32dx VSX Vector Splat Immediate32 Dword Indexed
xxspltidp VSX Vector Splat Immediate DP
xxspltiw VSX Vector Splat Immediate Word
Carl Love [Tue, 6 Oct 2020 16:52:34 +0000 (11:52 -0500)]
Vector Integer Multiply/Divide/Modulo Instruction tests
Carl Love [Tue, 6 Oct 2020 16:51:19 +0000 (11:51 -0500)]
VSX 32-byte storage access operations
Carl Love [Tue, 6 Oct 2020 16:44:50 +0000 (11:44 -0500)]
Set boolean support tests
Carl Love [Tue, 6 Oct 2020 16:41:04 +0000 (11:41 -0500)]
Add byte reverse tests ; cleanups to foundation patch.
Carl Love [Wed, 13 May 2020 20:19:07 +0000 (15:19 -0500)]
Add ISA 3.1 Vector Integer Multiply/Divide/Modulo Instructions
Add support for:
vdivesd Vector Divide Extended Signed Doubleword
vdivesw Vector Divide Extended Signed Word
vdiveud Vector Divide Extended Unsigned Doubleword
vdiveuw Vector Divide Extended Unsigned Word
vdivsd Vector Divide Signed Doubleword
vdivsw Vector Divide Signed Word
vdivud Vector Divide Unsigned Doubleword
vdivuw Vector Divide Unsigned Word
vmodsd Vector Modulo Signed Doubleword
vmodsw Vector Modulo Signed Word
vmodud Vector Modulo Unsigned Doubleword
vmoduw Vector Modulo Unsigned Word
vmulhsd Vector Multiply High Signed Doubleword
vmulhsw Vector Multiply High Signed Word
vmulhud Vector Multiply High Unsigned Doubleword
vmulhuw Vector Multiply High Unsigned Word
vmulld Vector Multiply Low Doubleword
Will Schmidt [Mon, 22 Jun 2020 14:57:21 +0000 (09:57 -0500)]
Add ISA 3.1 VSX 32-byte Storage Access Operations
Add support for the new ISA 3.1 load and store
instructions:
lxvpx Load VSX Vector Paired Indexed
plxvp Prefixed Load VSX Vector Paired
pstxvp Prefixed Store VSX Vector Paired
stxvpx Store VSX Vector Paired Indexed
Update the parsing of the lxvp and stxvp instructions that
were previously added.
lxvp Load VSX Vector Paired
stxvp Store VSX Vector Paired
A couple of format changes for the arguments to the
calculate_prefix_EA function.
Add comments to the else if and case statement to
clarify which instructions meet this condition.
Carl Love [Tue, 22 Sep 2020 17:30:43 +0000 (12:30 -0500)]
Add ISA 3.1 Set Boolean Extension instruction support
Add support for the new ISA 3.1 set boolean condition
word instructions:
setbc Set Boolean Condition
setbcr Set Boolean Condition Reverse
setnbc Set Negative Boolean Condition
setnbcr Set Negative Boolean Condition Reverse.
Carl Love [Tue, 22 Sep 2020 17:25:14 +0000 (12:25 -0500)]
Add ISA 3.1 Byte-Reverse Instruction support
Add support for the new ISA 3.1 word instructions:
brd Byte-Reverse Doubleword
brh Byte-Reverse Halfword
brw Byte-Reverse Word
Mark Wielaard [Fri, 25 Sep 2020 19:21:35 +0000 (21:21 +0200)]
Update .gitignore with none/tests/amd64/rdseed
Carl Love [Fri, 25 Sep 2020 16:14:58 +0000 (11:14 -0500)]
PPC64 tests Makefile.am cleanup
Fix the file consistency check in none/tests/ppc64/Makefile.am. Subsequent
patches for the PPC ISA 3.1 support will fully add the additional tests.
Mark Wielaard [Thu, 10 Sep 2020 10:30:11 +0000 (12:30 +0200)]
ir_defs.c: Iop_MAddF32 and Iop_MSubF32 are no (longer) s390 specific.
Mark Wielaard [Thu, 10 Sep 2020 10:28:57 +0000 (12:28 +0200)]
VEX/priv/guest_arm64_toIR.c: Fix vpanic messages mixup in mkDIVF.
Mark Wielaard [Wed, 23 Sep 2020 10:49:34 +0000 (12:49 +0200)]
Fix isa 3.1 test code on ppc64.
On ppc64 [old big endian] altivec.h can not be included directly.
Move the HAS_ISA_3_1 guard around so the include is only done when
the full test (and test_list_t) are build.
Carl Love [Tue, 22 Sep 2020 23:57:14 +0000 (18:57 -0500)]
Fix common isa 3.1 test code
The code in test_isa_3_1_common.c should only be included
if ISA 3.1 support exists.
Carl Love [Mon, 21 Sep 2020 20:57:26 +0000 (15:57 -0500)]
Prefixed load-store support
Carl Love [Mon, 21 Sep 2020 20:56:22 +0000 (15:56 -0500)]
valgrind isa 3.1 foundation
header files and other common parts associated with the initial isa v3.1
support
Carl Love [Tue, 28 Jul 2020 18:17:18 +0000 (13:17 -0500)]
Add prefixed support for the following word instructions.
addi Add Immediate
lbz Load Byte & Zero
ld Load Doubleword
lfd Load Floating Double
lfs Load Floating Single
lha Load Halfword Algebraic
lhz Load Halfword & Zero
lq Load Quadword
lwa Load Word Algebraic
lwz Load Word & Zero
lxsd Load VSX Scalar Doubleword
lxssp Load VSX Scalar Single-Precision
lxv Load VSX Vector
stb Store Byte
std Store Doubleword
stfd Store Floating Double
stfs Store Floating Single
sth Store Halfword
stq Store Quadword
stw Store Word
stxsd Store VSX Scalar Doubleword
stxssp Store VSX Scalar Single-Precision
stxv Store VSX Vector
Carl Love [Wed, 6 May 2020 20:27:32 +0000 (15:27 -0500)]
Instruction Prefix Support
Carl Love [Wed, 6 May 2020 20:13:42 +0000 (15:13 -0500)]
Add check for isa 3.1 support
Bart Van Assche [Sat, 19 Sep 2020 15:08:59 +0000 (08:08 -0700)]
drd: Port to Fedora 33
Apparently on Fedora 33 the POSIX thread functions exist in both libc and
libpthread. Hence this patch that intercepts the pthread functions in
libc. See also https://bugs.kde.org/show_bug.cgi?id=426144 .
Julian Seward [Sat, 19 Sep 2020 10:09:54 +0000 (12:09 +0200)]
On amd64, use by default the expensive instrumentation scheme for Iop_Add32.
This is necessary to avoid some false positives in code compiled by clang 10
at -O2. Some very crude measurements suggest the increase in generated code
size is around 0.2%, viz, insignificant.
Julian Seward [Sat, 19 Sep 2020 10:05:26 +0000 (12:05 +0200)]
Bug 425820 - Failure to recognize vpcmpeqq as a dependency breaking idiom.
In the IR optimiser (ir_opt.c): Recognise the following IROps as
dependency-breaking ops that generate an all-ones output: Iop_CmpEQ16x4
Iop_CmpEQ32x2 Iop_CmpEQ64x2 Iop_CmpEQ8x32 Iop_CmpEQ16x16 Iop_CmpEQ64x4. I
think this fixes all the known cases for sizes 32 bits to 256 bits. It also
fixes bug 425820.
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