From: DJ Delorie Date: Fri, 22 May 2009 17:37:43 +0000 (+0000) Subject: [cgen] X-Git-Url: https://sourceware.org/git/?a=commitdiff_plain;h=ac7d18e11ff2b27e177445d57293bf1e0d340a2f;p=cgen.git [cgen] * cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder. (mep_config_map): Regenerate. * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as ivc2-specific names. (simm8p20): New. (cmovc): move to after field definitions, use ivc2-specific register names. (cpmovi_b_P0S_P1): New. [utils/mep] * mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW size to default configuration. [sid/component/cgen-cpu/mep] * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-decode.h: Regenerate. * mep-cop1-16-model.cxx: Regenerate. * mep-cop1-16-model.h: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-decode.h: Regenerate. * mep-cop1-64-model.cxx: Regenerate. * mep-cop1-64-model.h: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. --- diff --git a/ChangeLog b/ChangeLog index 27309aa..7642b1e 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2009-05-22 DJ Delorie + + * cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder. + (mep_config_map): Regenerate. + + * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as + ivc2-specific names. + (simm8p20): New. + (cmovc): move to after field definitions, use ivc2-specific + register names. + (cpmovi_b_P0S_P1): New. + 2009-05-19 DJ Delorie * cpu/mep.opc: Regenerate configuration. diff --git a/cpu/mep-ivc2.cpu b/cpu/mep-ivc2.cpu index f766d32..be9a622 100644 --- a/cpu/mep-ivc2.cpu +++ b/cpu/mep-ivc2.cpu @@ -61,37 +61,34 @@ (get (index) (c-call DI "h_ccr_get" index)) (indices keyword "" (.splice - ($ivc2_acc0_0 16) - ($ivc2_acc0_1 17) - ($ivc2_acc0_2 18) - ($ivc2_acc0_3 19) - ($ivc2_acc0_4 20) - ($ivc2_acc0_5 21) - ($ivc2_acc0_6 22) - ($ivc2_acc0_7 23) - - ($ivc2_acc1_0 24) - ($ivc2_acc1_1 25) - ($ivc2_acc1_2 26) - ($ivc2_acc1_3 27) - ($ivc2_acc1_4 28) - ($ivc2_acc1_5 29) - ($ivc2_acc1_6 30) - ($ivc2_acc1_7 31) - - ($ivc2_csar0 0) - ($ivc2_csar1 15) - ($ivc2_cc 1) - ($ivc2_cofr0 4) - ($ivc2_cofr1 5) - ($ivc2_cofa0 6) - ($ivc2_cofa1 7) - - ($ivc2_ccr2 2) - ($ivc2_ccr3 3) - ($ivc2_ccr12 12) - ($ivc2_ccr13 13) - ($ivc2_ccr14 14) + + ($csar0 0) + ($cc 1) + ($cofr0 4) + ($cofr1 5) + ($cofa0 6) + ($cofa1 7) + + ($csar1 15) + + ($acc00 16) + ($acc01 17) + ($acc02 18) + ($acc03 19) + ($acc04 20) + ($acc05 21) + ($acc06 22) + ($acc07 23) + + ($acc10 24) + ($acc11 25) + ($acc12 26) + ($acc13 27) + ($acc14 28) + ($acc15 29) + ($acc16 30) + ($acc17 31) + (.unsplice (.map -ccr-reg-pair (.iota 32))) ) ) ) @@ -204,6 +201,7 @@ (dnop imm3p25 "Imm3p25" (all-mep-isas) h-uint f-ivc2-3u25) (dnop imm8p0 "Imm8p0" (all-mep-isas) h-uint f-ivc2-8u0) (dnop simm8p0 "sImm8p0" (all-mep-isas) h-sint f-ivc2-8s0) +(dnop simm8p20 "sImm8p20" (all-mep-isas) h-sint f-ivc2-8s20) (dnop imm8p20 "Imm8p20" (all-mep-isas) h-uint f-ivc2-8u20) (dnop crop "$CRo Pn" (all-mep-isas) h-cr64 f-ivc2-5u23) @@ -218,6 +216,55 @@ (dnop imm16p0 "Imm16p0" (all-mep-isas) h-uint f-ivc2-imm16p0) (dnop simm16p0 "sImm16p0" (all-mep-isas) h-sint f-ivc2-simm16p0) + + +(df f-ivc2-crn "ivc2 crn" (all-mep-isas) 0 4 UINT #f #f) +(df f-ivc2-crm "ivc2 crm" (all-mep-isas) 4 4 UINT #f #f) +(df f-ivc2-ccrn-h1 "ccrx hi 1u20" (all-mep-isas) 20 1 UINT #f #f) +(df f-ivc2-ccrn-h2 "ccrx hi 2u20" (all-mep-isas) 20 2 UINT #f #f) +(df f-ivc2-ccrn-lo "ccrx lo 4u0" (all-mep-isas) 0 4 UINT #f #f) +(df f-ivc2-cmov1 "ivc2 cmov op1" (all-mep-isas) 8 12 UINT #f #f) +(df f-ivc2-cmov2 "ivc2 cmov op2" (all-mep-isas) 22 6 UINT #f #f) +(df f-ivc2-cmov3 "ivc2 cmov op2" (all-mep-isas) 28 4 UINT #f #f) + +(define-multi-ifield + (name f-ivc2-ccrn) + (comment "Coprocessor control register number field") + (attrs all-mep-isas) + (mode UINT) + (subfields f-ivc2-ccrn-h2 f-ivc2-ccrn-lo) + (insert (sequence () + (set (ifield f-ivc2-ccrn-h2) (and (srl (ifield f-ivc2-ccrn) 4) #x3)) + (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-ccrn) #xf)))) + (extract (set (ifield f-ivc2-ccrn) + (or (sll (ifield f-ivc2-ccrn-h2) 4) + (ifield f-ivc2-ccrn-lo)))) + ) + +(define-multi-ifield + (name f-ivc2-crnx) + (comment "Coprocessor register number field") + (attrs all-mep-isas) + (mode UINT) + (subfields f-ivc2-ccrn-h1 f-ivc2-ccrn-lo) + (insert (sequence () + (set (ifield f-ivc2-ccrn-h1) (and (srl (ifield f-ivc2-crnx) 4) #x1)) + (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-crnx) #xf)))) + (extract (set (ifield f-ivc2-crnx) + (or (sll (ifield f-ivc2-ccrn-h1) 4) + (ifield f-ivc2-ccrn-lo)))) + ) + +(dnop ivc2rm "reg Rm" (all-mep-isas (CDATA REGNUM)) h-gpr f-ivc2-crm) +(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA REGNUM)) h-cr64 f-ivc2-crnx) +(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn) +(dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ccrn) + +; [--][--] [--][--] [--][--] [--] +; 0----+-- --1----+ ----2--- -+-- +; 01234567 89012345 67890123 4567 + + ; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm (dni cmov-crn-rm "cmov CRn,Rm" @@ -244,10 +291,10 @@ (dni cmovc-ccrn-rm "cmovc CCRn,Rm" (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc1")) - "cmovc $ccrn,$rm" - (+ MAJ_15 ccrn rm (f-sub4 #x7) + "cmovc $ivc2c3ccrn,$rm" + (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 0)) - (set ccrn rm) + (set ivc2c3ccrn rm) () ) @@ -255,10 +302,10 @@ (dni cmovc-rn-ccrm "cmovc Rm,CCRn" (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc2")) - "cmovc $rm,$ccrn" - (+ MAJ_15 ccrn rm (f-sub4 #x7) + "cmovc $rm,$ivc2c3ccrn" + (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 1)) - (set rm ccrn) + (set rm ivc2c3ccrn) () ) @@ -284,53 +331,6 @@ () ) - - -(df f-ivc2-crn "ivc2 crn" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-crm "ivc2 crm" (all-mep-isas) 4 4 UINT #f #f) -(df f-ivc2-ccrn-h1 "ccrx hi 1u20" (all-mep-isas) 20 1 UINT #f #f) -(df f-ivc2-ccrn-h2 "ccrx hi 2u20" (all-mep-isas) 20 2 UINT #f #f) -(df f-ivc2-ccrn-lo "ccrx lo 4u0" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-cmov1 "ivc2 cmov op1" (all-mep-isas) 8 12 UINT #f #f) -(df f-ivc2-cmov2 "ivc2 cmov op2" (all-mep-isas) 22 6 UINT #f #f) -(df f-ivc2-cmov3 "ivc2 cmov op2" (all-mep-isas) 28 4 UINT #f #f) - -(define-multi-ifield - (name f-ivc2-ccrn) - (comment "Coprocessor control register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h2 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h2) (and (srl (ifield f-ivc2-ccrn) 4) #x3)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-ccrn) #xf)))) - (extract (set (ifield f-ivc2-ccrn) - (or (sll (ifield f-ivc2-ccrn-h2) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(define-multi-ifield - (name f-ivc2-crnx) - (comment "Coprocessor register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h1 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h1) (and (srl (ifield f-ivc2-crnx) 4) #x1)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-crnx) #xf)))) - (extract (set (ifield f-ivc2-crnx) - (or (sll (ifield f-ivc2-ccrn-h1) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(dnop ivc2rm "reg Rm" (all-mep-isas (CDATA REGNUM)) h-gpr f-ivc2-crm) -(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA REGNUM)) h-cr64 f-ivc2-crnx) -(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr f-ivc2-ccrn) - -; [--][--] [--][--] [--][--] [--] -; 0----+-- --1----+ ----2--- -+-- -; 01234567 89012345 67890123 4567 - ; nnnnmmmm 11110000 0000N000 0000 cmov =crn,rm (dni cmov-crn-rm-p0 "cmov CRn,Rm" @@ -6685,6 +6685,17 @@ () ) +; 00000000 10110 qqqqq 00iii iiiii cpmovi.b =crqp,simm8p20 (p0_i) +(dni cpmovi_b_P0S_P1 "cpmovi.b $crqp,simm8p20 Pn" + (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b")) + "cpmovi.b $crqp,$simm8p20" + (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x0) imm8p20(f-ivc2-4u28 0)) + (sequence () + (c-call "check_option_cp" pc) + (set crqp (c-call DI "ivc2_cpmovi_b" pc simm8p20)) ) + () + ) + ; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1) (dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn" (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b")) diff --git a/cpu/mep.opc b/cpu/mep.opc index 4ef7897..a2416dc 100644 --- a/cpu/mep.opc +++ b/cpu/mep.opc @@ -1303,7 +1303,7 @@ mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_ else e = 0; - if ((buf[0^e] & 0xf0) != 0xf0) + if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V1 [-----core-----][--------p0s-------][------------p1------------] */ @@ -1528,7 +1528,7 @@ mep_config_map_struct mep_config_map[] = { /* config-map-start */ /* Default entry: first module, with all options enabled. */ - { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,1, 0, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, + { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, 0 | (1 << CGEN_INSN_OPTIONAL_CP_INSN)