From: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed, 26 Jun 2013 07:04:57 +0000 (+0000)
Subject: include/opcode/
X-Git-Tag: sid-snapshot-20130701~2
X-Git-Url: https://sourceware.org/git/?a=commitdiff_plain;h=aa688bddb4ab001e09986e4b2d44080413e0f6be;p=newlib-cygwin.git

include/opcode/
	* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
	Use "source" rather than "destination" for microMIPS "G".

gas/
	* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
---

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 9aa75d902..b927a2c34 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
+	Use "source" rather than "destination" for microMIPS "G".
+
 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ec9b6ba19..68cd9b6d7 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -377,7 +377,7 @@ struct mips_opcode
 
    Each of these characters corresponds to a mask field defined above.
 
-   "1" 5 bit sync type (OP_*_SHAMT)
+   "1" 5 bit sync type (OP_*_STYPE)
    "<" 5 bit shift amount (OP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
    "a" 26 bit target address (OP_*_TARGET)
@@ -1742,7 +1742,7 @@ extern const int bfd_mips16_num_opcodes;
    others too).
 
    "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
-   "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
+   "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32
        (MICROMIPSOP_*_SHAMT)
@@ -1814,9 +1814,9 @@ extern const int bfd_mips16_num_opcodes;
 
    Coprocessor instructions:
    "E" 5-bit target register (MICROMIPSOP_*_RT)
-   "G" 5-bit destination register (MICROMIPSOP_*_RS)
+   "G" 5-bit source register (MICROMIPSOP_*_RS)
    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
-   "+D" combined destination register ("G") and sel ("H") for CP0 ops,
+   "+D" combined source register ("G") and sel ("H") for CP0 ops,
 	for pretty-printing in disassembly only
 
    Macro instructions: