Added new instructions for next version of VIA PadLock core.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4ed2b86790e3b0fb16e7212f54141fbb32ee270c..684a2e7c4622b2574715584117551703a9e5120b 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2004-08-30  Michal Ludvig  <mludvig@suse.cz>
+
+       * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
+
 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 454a7fd09fbaca7eb8f9100d1769e904c82e9c0e..96bf149d59aadab59cbdf2d8db2d86c28d71f8df 100644 (file)
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1378,6 +1378,9 @@ static const template i386_optab[] =
 {"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
 {"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
 {"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"montmul",   0, 0xf30fa6c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"xsha1",     0, 0xf30fa6c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
+{"xsha256",   0, 0xf30fa6d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },
 /* Alias for xstorerng.  */
 {"xstore",    0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },