gas/

2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.h (CpuPNI): Removed.
	(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
	* config/tc-i386.c (md_assemble): Likewise.

include/opcode/

2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f9b98feacd63092f4be1a21e9b879f409f5d07c4..aad0ddbb4e405a7ed3f3daeb93067fe978e5a79b 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
+
 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 
        * score-inst.h (enum score_insn_type): Add Insn_internal.

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index bbecf3c7adaa08d9ede902fb7a8cc3a365813341..3e91aa0e410d8458753dbc6367e6988592ed40d5 100644 (file)
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1328,38 +1328,38 @@ static const template i386_optab[] =
 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
 
-/* Prescott New Instructions.  */
-
-{"addsubpd",  2, 0x660fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"addsubps",  2, 0xf20fd0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpxchg16b",1, 0x0fc7,    1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
-{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|Modrm,    { ShortMem|LongMem, 0, 0} },
-{"fisttp",    1, 0xdd,      1, CpuPNI, q_FP|Modrm,     { LLongMem, 0, 0} },
-{"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,       { LLongMem, 0, 0} },
-{"haddpd",    2, 0x660f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"haddps",    2, 0xf20f7c,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubpd",    2, 0x660f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"hsubps",    2, 0xf20f7d,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"lddqu",     2, 0xf20ff0,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
-{"monitor",   0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt,   { 0, 0, 0} },
+/* SSE-3 instructions.  */
+
+{"addsubpd",  2, 0x660fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpxchg16b",1, 0x0fc7,    1, CpuSSE3|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
+{"fisttp",    1, 0xdf,      1, CpuSSE3, sl_FP|Modrm,   { ShortMem|LongMem, 0, 0} },
+{"fisttp",    1, 0xdd,      1, CpuSSE3, q_FP|Modrm,    { LLongMem, 0, 0} },
+{"fisttpll",  1, 0xdd,      1, CpuSSE3, FP|Modrm,      { LLongMem, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuSSE3, NoSuf|ImmExt,  { 0, 0, 0} },
 /* monitor is very special. CX and DX are always 64bits with zero upper
    32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The
    address size override prefix can be used to overrride the AX size in
    all modes.  */
 /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */
-{"monitor",   3, 0x0f01, 0xc8, CpuPNI|CpuNo64, NoSuf|ImmExt,   { Reg16|Reg32, Reg32, Reg32 } },
+{"monitor",   3, 0x0f01, 0xc8, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg16|Reg32, Reg32, Reg32 } },
 /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */
-{"monitor",   3, 0x0f01, 0xc8, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg32|Reg64, Reg64, Reg64 } },
-{"movddup",   2, 0xf20f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movshdup",  2, 0xf30f16,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"movsldup",  2, 0xf30f12,  X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
-{"mwait",     0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt,   { 0, 0, 0} },
+{"monitor",   3, 0x0f01, 0xc8, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,    { Reg32|Reg64, Reg64, Reg64 } },
+{"movddup",   2, 0xf20f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuSSE3, NoSuf|ImmExt,  { 0, 0, 0} },
 /* mwait is very special. AX and CX are always 64bits with zero upper
    32bits in 64bit mode, and 32bits in 16bit and 32bit modes.  */
 /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
-{"mwait",     2, 0x0f01, 0xc9, CpuPNI|CpuNo64, NoSuf|ImmExt,   { Reg32, Reg32, 0} },
+{"mwait",     2, 0x0f01, 0xc9, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg32, Reg32, 0} },
 /* Need to ensure only "mwait %rax,%rcx" is accepted.  */
-{"mwait",     2, 0x0f01, 0xc9, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg64, Reg64, 0} },
+{"mwait",     2, 0x0f01, 0xc9, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,    { Reg64, Reg64, 0} },
 
 /* VMX instructions.  */
 {"vmcall",    0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt,   { 0, 0, 0} },