* opcodes disassembler extension

[includes]
2002-02-04  Frank Ch. Eigler  <fche@redhat.com>

	* dis-asm.h (disassemble_info): New field `insn_sets'.
	(INIT_DISASSEMBLE_INFO): Clear it.

[opcodes]
2002-02-04  Frank Ch. Eigler  <fche@redhat.com>

	* cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets.

diff --git a/include/ChangeLog b/include/ChangeLog
index 9ac65a039bc427b1f4dda4a581c5259a99e8ce61..e482f97bb14aec5790111ff7cd85a575deaf7871 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2002-02-05  Frank Ch. Eigler  <fche@redhat.com>
+
+       * dis-asm.h (disassemble_info): New field `insn_sets'.
+       (INIT_DISASSEMBLE_INFO): Clear it.
+
 2002-02-05  Jason Merrill  <jason@redhat.com>
 
        * demangle.h (cplus_demangle_v3): Add "options" parm.

diff --git a/include/dis-asm.h b/include/dis-asm.h
index 8cd848dbd396a1ef710311003bb69b2415503350..5b9e390d34c242dadde83acfbe3d45ce89dd24a2 100644 (file)
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -73,6 +73,11 @@ typedef struct disassemble_info {
   unsigned long mach;
   /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
   enum bfd_endian endian;
+  /* An arch/mach-specific bitmask of selected instruction subsets, mainly
+     for processors with run-time-switchable instruction sets.  The default,
+     zero, means that there is no constraint.  CGEN-based opcodes ports
+     may use ISA_foo masks.  */
+  unsigned long insn_sets;
 
   /* Some targets need information about the current section to accurately
      display insns.  If this is NULL, the target disassembler function
@@ -275,6 +280,7 @@ extern int generic_symbol_at_address
   (INFO).flavour = bfd_target_unknown_flavour, \
   (INFO).arch = bfd_arch_unknown, \
   (INFO).mach = 0, \
+  (INFO).insn_sets = 0, \
   (INFO).endian = BFD_ENDIAN_UNKNOWN, \
   (INFO).octets_per_byte = 1, \
   INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)