coverity: mostly unsigned >= 0 comparisons

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 505b66f30f832681cb1d1abbd4e24c813f0fa8a3..a6f5272b9ca1321240c358caecfb7ce60d394518 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -2747,7 +2747,7 @@ Bool dis_ARM64_data_processing_immediate(/*MB_OUT*/DisResult* dres,
              nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), shift);
          return True;
       }
-      if (!is64 && immS >= 0 && immS <= 30
+      if (!is64 && immS <= 30
           && immR == immS + 1 && opc == BITS2(1,0)) {
          // 32-bit shift left
          UInt shift = 32 - immR;
@@ -3690,7 +3690,7 @@ Bool dis_ARM64_data_processing_register(/*MB_OUT*/DisResult* dres,
                vassert(0);
          }
 
-         vassert(ix >= 0 && ix <= 7);
+         vassert(ix <= 7);
 
          putIReg64orZR(
             dd,
@@ -8424,7 +8424,7 @@ static IRTemp math_TBL_TBX ( IRTemp tab[4], UInt len, IRTemp src,
 
    UInt tabent;
    for (tabent = 0; tabent <= len; tabent++) {
-      vassert(tabent >= 0 && tabent < 4);
+      vassert(tabent < 4);
       IRTemp bias = newTempV128();
       assign(bias,
              mkexpr(tabent == 0 ? allZero : allXX[tabent-1]));
@@ -10351,7 +10351,7 @@ Bool dis_AdvSIMD_scalar_shift_by_imm(/*MB_OUT*/DisResult* dres, UInt insn)
    if (bitU == 1 && (immh & 8) == 8 && opcode == BITS5(0,1,0,1,0)) {
       /* -------- 1,1xxx,01010 SLI d_d_#imm -------- */
       UInt sh = immhb - 64;
-      vassert(sh >= 0 && sh < 64);
+      vassert(sh < 64);
       if (sh == 0) {
          putQReg128(dd, unop(Iop_ZeroHI64ofV128, getQReg128(nn)));
       } else {
@@ -11529,7 +11529,7 @@ Bool dis_AdvSIMD_scalar_x_indexed_element(/*MB_OUT*/DisResult* dres, UInt insn)
          case BITS4(0,1,1,1): ks = 2; break;
          default: vassert(0);
       }
-      vassert(ks >= 0 && ks <= 2);
+      vassert(ks <= 2);
       UInt mm  = 32; // invalid
       UInt ix  = 16; // invalid
       switch (size) {
@@ -11736,7 +11736,7 @@ Bool dis_AdvSIMD_shift_by_immediate(/*MB_OUT*/DisResult* dres, UInt insn)
       Bool isAcc = opcode == BITS5(0,0,1,1,0);
       Bool ok    = getLaneInfo_IMMH_IMMB(&shift, &size, immh, immb);
       if (!ok || (bitQ == 0 && size == X11)) return False;
-      vassert(size >= 0 && size <= 3);
+      vassert(size <= 3);
       UInt lanebits = 8 << size;
       vassert(shift >= 1 && shift <= lanebits);
       IROp    op   = isU ? mkVecRSHU(size) : mkVecRSHS(size);
@@ -12336,7 +12336,7 @@ Bool dis_AdvSIMD_three_different(/*MB_OUT*/DisResult* dres, UInt insn)
          case BITS4(1,0,1,1): ks = 2; break;
          default: vassert(0);
       }
-      vassert(ks >= 0 && ks <= 2);
+      vassert(ks <= 2);
       if (size == X00 || size == X11) return False;
       vassert(size <= 2);
       IRTemp vecN, vecM, vecD, res, sat1q, sat1n, sat2q, sat2n;
@@ -14305,7 +14305,7 @@ Bool dis_AdvSIMD_vector_x_indexed_elem(/*MB_OUT*/DisResult* dres, UInt insn)
          case BITS4(0,1,1,1): ks = 2; break;
          default: vassert(0);
       }
-      vassert(ks >= 0 && ks <= 2);
+      vassert(ks <= 2);
       Bool is2 = bitQ == 1;
       UInt mm  = 32; // invalid
       UInt ix  = 16; // invalid

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index cdc1265f0d96302ef61cf954541c5f566a7d0496..5e9e49568c2768fe74e2753f939f8b4db79ab347 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -1340,7 +1340,7 @@ void setFlags_D1_D2_ND ( UInt cc_op, IRTemp t_dep1,
    vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I32));
    vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I32));
    vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I32));
-   // strictly unsigned cc_op must always be >= 0,  keeong for readability
+   // strictly unsigned cc_op must always be >= 0,  keeping for readability
    vassert(cc_op >= ARMG_CC_OP_COPY && cc_op < ARMG_CC_OP_NUMBER);
    if (guardT == IRTemp_INVALID) {
       /* unconditional */

diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index bfdb11b14c00289e85bbc9764ec0ad3f723675f3..1a8e9fbf716d9ff58e7a30d4d4bb1be307dfb7a0 100644 (file)
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -1776,6 +1776,8 @@ void vsx_matrix_8bit_ger_dirty_helper( VexGuestPPC64State* gst,
             else if ( inst == XVI8GER4SPP )
                result[j] = clampS64toS32(sum + acc_word[j]);
 
+            // @todo PJF Coverity complains that if none of the abofe ifs are true
+            // then result gets used uninitialized
          } else {
             result[j] = 0;
          }

diff --git a/VEX/priv/host_amd64_isel.c b/VEX/priv/host_amd64_isel.c
index 5104e7dbe712e2a9e07a1f96be6a500a7e22d61e..762351961715c25e42be0524f9dc9158a9bdf366 100644 (file)
--- a/VEX/priv/host_amd64_isel.c
+++ b/VEX/priv/host_amd64_isel.c
@@ -619,7 +619,7 @@ void doHelperCall ( /*OUT*/UInt*   stackAdjustAfterCall,
       addInstr(env, mk_iMOVsd_RR( hregAMD64_RSP(), r_vecRetAddr ));
    }
 
-   vassert(n_args >= 0 && n_args <= 6);
+   vassert(n_args <= 6);
    for (i = 0; i < n_args; i++) {
       IRExpr* arg = args[i];
       if (UNLIKELY(arg->tag == Iex_GSPTR)) {
@@ -2610,8 +2610,11 @@ static HReg iselCondCode_R_wrk ( ISelEnv* env, const IRExpr* e )
    addInstr(env, AMD64Instr_Set64(cc, res));
    return res;
 
+   // PJF old debug code? - unreachable
+   /*
    ppIRExpr(e);
    vpanic("iselCondCode_R(amd64)");
+   */
 }
 
 

diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c
index 8d17238e3cc8d1e6f5198f7f42fbdec36fd06cdb..e30336583dcc020e674f883596619a12a35d037d 100644 (file)
--- a/VEX/priv/host_arm_defs.c
+++ b/VEX/priv/host_arm_defs.c
@@ -417,7 +417,7 @@ void ppARMAModeN ( ARMAModeN* am ) {
 /* --------- Reg or imm-8x4 operands --------- */
 
 static UInt ROR32 ( UInt x, UInt sh ) {
-   vassert(sh >= 0 && sh < 32);
+   vassert(sh < 32);
    if (sh == 0)
       return x;
    else

diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c
index f1eb4c9b187266336aa5dd06af083b6c93daaaf6..b7446921a422b546a03601610eab9bb26495370b 100644 (file)
--- a/VEX/priv/host_generic_reg_alloc3.c
+++ b/VEX/priv/host_generic_reg_alloc3.c
@@ -148,9 +148,9 @@ typedef
    }
    RRegLRState;
 
-/* v is always unsigned, wish we could static assert that */
+/* v and r are always unsigned, wish we could static assert that */
 #define IS_VALID_VREGNO(v) ((v) < n_vregs)
-#define IS_VALID_RREGNO(r) ((r) >= 0 && (r) < n_rregs)
+#define IS_VALID_RREGNO(r) ((r) < n_rregs)
 
 #define FREE_VREG(v)             \
    do {                          \

diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 75a753f75a127c0199a04ef9933fa6111d28492f..34b6afe7cfcf4485a8663b53df3f4fce9deb3f3a 100644 (file)
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -308,7 +308,6 @@ static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
 static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO,
                                ISelEnv* env, IRTemp tmp )
 {
-   vassert(tmp >= 0);
    vassert(tmp < env->n_vregmap);
    vassert(! hregIsInvalid(env->vregmapMedLo[tmp]));
    *vrLO = env->vregmapLo[tmp];

diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index c811dc5b80be420fc84c1b90dc881eb2ff35e7d1..471be8cb23ddd203301af5a0a8f25b6933190a19 100644 (file)
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -11709,8 +11709,12 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn)
       case S390_VEC_FLOAT_COMPARE_EQUAL:
          return s390_emit_VFCE(buf, v1, v2, v3, s390_getM_from_size(size), 0, 0);
       case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL:
+         // PJF I assume that CHE is cmpare higher or equal so the order need swapping
+         // coverity[SWAPPED_ARGUMENTS:FALSE]
          return s390_emit_VFCHE(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
       case S390_VEC_FLOAT_COMPARE_LESS:
+         // PJF as above but this time compare higher
+         // coverity[SWAPPED_ARGUMENTS:FALSE]
          return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0);
 
       default:

diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c
index 391b3b4834cc8245d2ec64fe1edec898ecfc0bb3..e89b145327513fa6baafa6324566b6fa8345d2e6 100644 (file)
--- a/VEX/priv/host_x86_isel.c
+++ b/VEX/priv/host_x86_isel.c
@@ -190,7 +190,6 @@ typedef
 
 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
 {
-   vassert(tmp >= 0);
    vassert(tmp < env->n_vregmap);
    return env->vregmap[tmp];
 }

diff --git a/callgrind/jumps.c b/callgrind/jumps.c
index ad0125490532668c529d35c611ef22d224b7adc3..5a0d32e9e4f94d4cacbd1d994f43268b05ada997 100644 (file)
--- a/callgrind/jumps.c
+++ b/callgrind/jumps.c
@@ -155,7 +155,7 @@ static jCC* new_jcc(BBCC* from, UInt jmp, BBCC* to)
 
    if (from) {
        /* Prohibit corruption by array overrun */
-       CLG_ASSERT((0 <= jmp) && (jmp <= from->bb->cjmp_count));
+       CLG_ASSERT(jmp <= from->bb->cjmp_count);
        jcc->next_from = from->jmp[jmp].jcc_list;
        from->jmp[jmp].jcc_list = jcc;
    }

diff --git a/coregrind/m_debuginfo/image.c b/coregrind/m_debuginfo/image.c
index 5c9d722467083ce9f4430df7091d0688069b9bc8..70c3bd859a5b0fc07fa3d1cb24df04bffacabaec 100644 (file)
--- a/coregrind/m_debuginfo/image.c
+++ b/coregrind/m_debuginfo/image.c
@@ -1322,7 +1322,7 @@ UInt ML_(img_calc_gnu_debuglink_crc32)(DiImage* img)
       DiOffT img_szB  = ML_(img_size)(img);
       DiOffT curr_off = 0;
       while (1) {
-         vg_assert(curr_off >= 0 && curr_off <= img_szB);
+         vg_assert(curr_off <= img_szB);
          if (curr_off == img_szB) break;
          DiOffT avail = img_szB - curr_off;
          vg_assert(avail > 0 && avail <= img_szB);

diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c
index 80c4b77bb59f8976cc6181be0d63526c94920175..ace485c1573f10d4bfdeba33690dc6e2dbb8ad90 100644 (file)
--- a/coregrind/m_debuginfo/storage.c
+++ b/coregrind/m_debuginfo/storage.c
@@ -748,7 +748,7 @@ DiCfSI_m* ML_(get_cfsi_m) (const DebugInfo* di, UInt pos)
 {
    UInt cfsi_m_ix;
 
-   vg_assert(pos >= 0 && pos < di->cfsi_used);
+   vg_assert(pos < di->cfsi_used);
    switch (di->sizeof_cfsi_m_ix) {
       case 1: cfsi_m_ix = ((UChar*)  di->cfsi_m_ix)[pos]; break;
       case 2: cfsi_m_ix = ((UShort*) di->cfsi_m_ix)[pos]; break;

diff --git a/coregrind/m_execontext.c b/coregrind/m_execontext.c
index 227c3c3dc71292964527939478a53b740ae6f292..9305f316efe9669fadb8b5e3645f6bc29b4d27a9 100644 (file)
--- a/coregrind/m_execontext.c
+++ b/coregrind/m_execontext.c
@@ -352,7 +352,7 @@ static void resize_ec_htab ( void )
    SizeT        new_size;
    ExeContext** new_ec_htab;
 
-   vg_assert(ec_htab_size_idx >= 0 && ec_htab_size_idx < N_EC_PRIMES);
+   vg_assert(ec_htab_size_idx < N_EC_PRIMES);
    if (ec_htab_size_idx == N_EC_PRIMES-1)
       return; /* out of primes - can't resize further */
 

diff --git a/coregrind/m_main.c b/coregrind/m_main.c
index 9087aafb0291e46ee57b14854d89a64f2b4508ba..1cedaaf2e36c5baa4db89ca2dfffefdcfc163784 100644 (file)
--- a/coregrind/m_main.c
+++ b/coregrind/m_main.c
@@ -1945,7 +1945,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
    //--------------------------------------------------------------
    VG_(debugLog)(1, "main", "Initialise scheduler (phase 1)\n");
    tid_main = VG_(scheduler_init_phase1)();
-   vg_assert(tid_main >= 0 && tid_main < VG_N_THREADS
+   vg_assert(tid_main < VG_N_THREADS
              && tid_main != VG_INVALID_THREADID);
    /* Tell the tool about tid_main */
    VG_TRACK( pre_thread_ll_create, VG_INVALID_THREADID, tid_main );

diff --git a/coregrind/m_mallocfree.c b/coregrind/m_mallocfree.c
index 44beb3d8b57cc3d7859a2966b4f5824e255fb6d4..96104c8d57c170ff00d7507fbf086c3a235cdadd 100644 (file)
--- a/coregrind/m_mallocfree.c
+++ b/coregrind/m_mallocfree.c
@@ -971,7 +971,7 @@ Superblock* findSb ( Arena* a, Block* b )
       Superblock * sb; 
       SizeT pos = min + (max - min)/2;
 
-      vg_assert(pos >= 0 && pos < a->sblocks_used);
+      vg_assert(pos < a->sblocks_used);
       sb = a->sblocks[pos];
       if ((Block*)&sb->payload_bytes[0] <= b
           && b < (Block*)&sb->payload_bytes[sb->n_payload_bytes])

diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c
index 3062c1afc30b818347e836e9073a070bc89f30da..f8b3b46c1ee4249485c23a5e6d9d9bc5529c4a06 100644 (file)
--- a/coregrind/m_scheduler/scheduler.c
+++ b/coregrind/m_scheduler/scheduler.c
@@ -595,7 +595,7 @@ void mostly_clear_thread_record ( ThreadId tid )
 {
    vki_sigset_t savedmask;
 
-   vg_assert(tid >= 0 && tid < VG_N_THREADS);
+   vg_assert(tid < VG_N_THREADS);
    VG_(cleanup_thread)(&VG_(threads)[tid].arch);
    VG_(threads)[tid].tid = tid;
 

diff --git a/coregrind/m_seqmatch.c b/coregrind/m_seqmatch.c
index 06151ee0f810974b55fed8d90cb8b3cf164b8b76..09abbca092adc2d049b514ec14eca24fb19d60f9 100644 (file)
--- a/coregrind/m_seqmatch.c
+++ b/coregrind/m_seqmatch.c
@@ -65,11 +65,10 @@ Bool VG_(generic_match) (
    Bool  havePatt, haveInput;
    const HChar *currPatt, *currInput;
   tailcall:
-   vg_assert(nPatt >= 0 && nPatt  < 1000000); /* arbitrary */
-   vg_assert(inputCompleter
-             || (nInput >= 0  && nInput < 1000000)); /* arbitrary */
-   vg_assert(ixPatt >= 0  && ixPatt <= nPatt);
-   vg_assert(ixInput >= 0 && (inputCompleter || ixInput <= nInput));
+   vg_assert(nPatt  < 1000000); /* arbitrary */
+   vg_assert(inputCompleter || (nInput < 1000000)); /* arbitrary */
+   vg_assert(ixPatt <= nPatt);
+   vg_assert(inputCompleter || ixInput <= nInput);
 
    havePatt  = ixPatt < nPatt;
    haveInput = inputCompleter ? 

diff --git a/coregrind/m_threadstate.c b/coregrind/m_threadstate.c
index 6cb6941e4d2edfb179549d16e7cbd9c08497065a..85ae03569d3e4618781d5ec0500bba00b3e48274 100644 (file)
--- a/coregrind/m_threadstate.c
+++ b/coregrind/m_threadstate.c
@@ -97,7 +97,7 @@ const HChar* VG_(name_of_VgSchedReturnCode) ( VgSchedReturnCode retcode )
 
 ThreadState *VG_(get_ThreadState)(ThreadId tid)
 {
-   vg_assert(tid >= 0 && tid < VG_N_THREADS);
+   vg_assert(tid < VG_N_THREADS);
    vg_assert(VG_(threads)[tid].tid == tid);
    return &VG_(threads)[tid];
 }

diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
index 8ae06d2a67fa966e9a365a8ce201b6b0b6b2b6fd..0dd36082d22616ca52ff62fb4b9c1f3157850375 100644 (file)
--- a/coregrind/m_translate.c
+++ b/coregrind/m_translate.c
@@ -1831,7 +1831,7 @@ Bool VG_(translate) ( ThreadId tid,
    tres = LibVEX_Translate ( &vta );
 
    vg_assert(tres.status == VexTransOK);
-   vg_assert(tres.n_sc_extents >= 0 && tres.n_sc_extents <= 3);
+   vg_assert(tres.n_sc_extents <= 3);
    vg_assert(tmpbuf_used <= N_TMPBUF);
    vg_assert(tmpbuf_used > 0);
 

diff --git a/coregrind/m_transtab.c b/coregrind/m_transtab.c
index ff5b35b53af703af19986deaebdc07f04adaca70..789a169dcd73beb344308b3e793bdcfd4a514fa4 100644 (file)
--- a/coregrind/m_transtab.c
+++ b/coregrind/m_transtab.c
@@ -1850,7 +1850,7 @@ void VG_(add_to_transtab)( const VexGuestExtents* vge,
 
    // Point an htt entry to the tt slot
    HTTno htti = HASH_TT(entry);
-   vg_assert(htti >= 0 && htti < N_HTTES_PER_SECTOR);
+   vg_assert(htti < N_HTTES_PER_SECTOR);
    while (True) {
       if (sectors[y].htt[htti] == HTT_EMPTY
           || sectors[y].htt[htti] == HTT_DELETED)
@@ -1925,7 +1925,7 @@ Bool VG_(search_transtab) ( /*OUT*/Addr*  res_hcode,
       all sectors and avoids multiple expensive % operations. */
    n_full_lookups++;
    kstart = HASH_TT(guest_addr);
-   vg_assert(kstart >= 0 && kstart < N_HTTES_PER_SECTOR);
+   vg_assert(kstart < N_HTTES_PER_SECTOR);
 
    /* Search in all the sectors,using sector_search_order[] as a
       heuristic guide as to what order to visit the sectors. */

diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c
index 45e6388b65afd26e97e47ef8da694cc7233b612c..a31aacf5c7250a9357f8e2fc62e0f5223ed3e197 100644 (file)
--- a/helgrind/hg_main.c
+++ b/helgrind/hg_main.c
@@ -3625,9 +3625,9 @@ static void univ_laog_do_GC ( void ) {
    links = NULL;
    while (VG_(nextIterFM)( laog, NULL, (UWord*)&links )) {
       tl_assert(links);
-      tl_assert(links->inns >= 0 && links->inns < univ_laog_cardinality);
+      tl_assert(links->inns < univ_laog_cardinality);
       univ_laog_seen[links->inns] = True;
-      tl_assert(links->outs >= 0 && links->outs < univ_laog_cardinality);
+      tl_assert(links->outs < univ_laog_cardinality);
       univ_laog_seen[links->outs] = True;
       links = NULL;
    }

diff --git a/helgrind/hg_wordset.c b/helgrind/hg_wordset.c
index 34978ffc5fee693124366a4d8e5f1666a845cf38..3b780262a65fac9ddeb916cc9240a0d4a38b2623 100644 (file)
--- a/helgrind/hg_wordset.c
+++ b/helgrind/hg_wordset.c
@@ -420,7 +420,6 @@ UWord HG_(cardinalityWS) ( WordSetU* wsu, WordSet ws )
    WordVec* wv;
    tl_assert(wsu);
    wv = do_ix2vec( wsu, ws );
-   tl_assert(wv->size >= 0);
    return wv->size;
 }
 
@@ -447,7 +446,6 @@ void HG_(getPayloadWS) ( /*OUT*/UWord** words, /*OUT*/UWord* nWords,
    if (HG_DEBUG) VG_(printf)("getPayloadWS %s %d\n", wsu->cc, (Int)ws);
    tl_assert(wsu);
    wv = do_ix2vec( wsu, ws );
-   tl_assert(wv->size >= 0);
    *nWords = wv->size;
    *words  = wv->words;
 }

diff --git a/helgrind/libhb_core.c b/helgrind/libhb_core.c
index 2acf3fbd8383fda42211e05e28cec2a5fddb7468..101624028f02ed8db2af18df5f884e55614bb286 100644 (file)
--- a/helgrind/libhb_core.c
+++ b/helgrind/libhb_core.c
@@ -1511,7 +1511,7 @@ static __attribute__((noinline)) void cacheline_wback ( UWord wix )
    if (0)
    VG_(printf)("scache wback line %d\n", (Int)wix);
 
-   tl_assert(wix >= 0 && wix < N_WAY_NENT);
+   tl_assert(wix < N_WAY_NENT);
 
    tag =  cache_shmem.tags0[wix];
    cl  = &cache_shmem.lyns0[wix];
@@ -1650,7 +1650,7 @@ static __attribute__((noinline)) void cacheline_fetch ( UWord wix )
    if (0)
    VG_(printf)("scache fetch line %d\n", (Int)wix);
 
-   tl_assert(wix >= 0 && wix < N_WAY_NENT);
+   tl_assert(wix < N_WAY_NENT);
 
    tag =  cache_shmem.tags0[wix];
    cl  = &cache_shmem.lyns0[wix];
@@ -5338,7 +5338,7 @@ static void record_race_info ( Thr* acc_thr,
    tl_assert(acc_thr);
    tl_assert(acc_thr->hgthread);
    tl_assert(acc_thr->hgthread->hbthr == acc_thr);
-   tl_assert(HG_(clo_history_level) >= 0 && HG_(clo_history_level) <= 2);
+   tl_assert(HG_(clo_history_level) <= 2);
 
    if (HG_(clo_history_level) == 1) {
       Bool found;
@@ -5941,6 +5941,7 @@ static
 void zsm_swrite64 ( Addr a, SVal svNew ) {
    CacheLine* cl; 
    UWord      cloff, tno;
+   SizeT      i;
    //UWord    toff;
    stats__cline_swrite64s++;
    if (UNLIKELY(!aligned64(a))) goto slowcase;

diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index 2221f8d3d84d6beccac8f23e91367e69b49c3445..e6e9ef80aafdd83691ed701d3132d399ef190232 100644 (file)
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -3711,7 +3711,7 @@ static inline UInt convert_nia_to_ecu ( Addr nia )
 
    stats__nia_cache_queries++;
    i = nia % N_NIA_TO_ECU_CACHE;
-   tl_assert(i >= 0 && i < N_NIA_TO_ECU_CACHE);
+   tl_assert(i < N_NIA_TO_ECU_CACHE);
 
    if (LIKELY( nia_to_ecu_cache[i].nia0 == nia ))
       return nia_to_ecu_cache[i].ecu0;