]> sourceware.org Git - systemtap.git/commitdiff
Add bactrace support for RISC-V
authorWilliam Cohen <wcohen@redhat.com>
Fri, 13 Aug 2021 00:58:07 +0000 (08:58 +0800)
committerWilliam Cohen <wcohen@redhat.com>
Tue, 7 Sep 2021 02:21:27 +0000 (22:21 -0400)
runtime/linux/runtime.h
runtime/unwind/riscv.h [new file with mode: 0644]
runtime/unwind/unwind.h

index e57d10a8a09ce7cbd4b6d311cf0174865b6866e5..880c1fa4a1758bab5d991c079e2d0ea656f16a6a 100644 (file)
@@ -199,7 +199,7 @@ static struct
    Only define STP_USE_DWARF_UNWINDER when STP_NEED_UNWIND_DATA,
    as set through a pragma:unwind in one of the [u]context-unwind.stp
    functions. */
-#if (defined(__arm__) || defined(__i386__) || defined(__x86_64__) || defined(__powerpc64__)) || defined (__s390x__) || defined(__aarch64__) || defined(__mips__)
+#if (defined(__arm__) || defined(__i386__) || defined(__x86_64__) || defined(__powerpc64__)) || defined (__s390x__) || defined(__aarch64__) || defined(__mips__) || defined(__riscv)
 #ifdef STP_NEED_UNWIND_DATA
 #ifndef STP_USE_DWARF_UNWINDER
 #define STP_USE_DWARF_UNWINDER
diff --git a/runtime/unwind/riscv.h b/runtime/unwind/riscv.h
new file mode 100644 (file)
index 0000000..62434cf
--- /dev/null
@@ -0,0 +1,78 @@
+/* -*- linux-c -*-
+ *
+ * RISC-V dwarf unwinder header file
+ *
+ * This file is part of systemtap, and is free software.  You can
+ * redistribute it and/or modify it under the terms of the GNU General
+ * Public License (GPL); either version 2, or (at your option) any
+ * later version.
+ */
+#ifndef _STP_RISCV_UNWIND_H
+#define _STP_RISCV_UNWIND_H
+
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+
+#define _stp_get_unaligned(ptr) (*(ptr))
+
+#define UNW_PC(frame)        (frame)->regs.epc
+#define UNW_SP(frame)        (frame)->regs.sp
+
+#define STACK_LIMIT(ptr)     (((ptr) - 1) & ~(THREAD_SIZE - 1))
+
+#define UNW_REGISTER_INFO \
+       PTREGS_INFO(epc), \
+       PTREGS_INFO(ra), \
+       PTREGS_INFO(sp), \
+       PTREGS_INFO(gp), \
+       PTREGS_INFO(tp), \
+       PTREGS_INFO(t0), \
+       PTREGS_INFO(t1), \
+       PTREGS_INFO(t2), \
+       PTREGS_INFO(s0), \
+       PTREGS_INFO(s1), \
+       PTREGS_INFO(a0), \
+       PTREGS_INFO(a1), \
+       PTREGS_INFO(a2), \
+       PTREGS_INFO(a3), \
+       PTREGS_INFO(a4), \
+       PTREGS_INFO(a5), \
+       PTREGS_INFO(a6), \
+       PTREGS_INFO(a7), \
+       PTREGS_INFO(s2), \
+       PTREGS_INFO(s3), \
+       PTREGS_INFO(s4), \
+       PTREGS_INFO(s5), \
+       PTREGS_INFO(s6), \
+       PTREGS_INFO(s7), \
+       PTREGS_INFO(s8), \
+       PTREGS_INFO(s9), \
+       PTREGS_INFO(s10), \
+       PTREGS_INFO(s11), \
+       PTREGS_INFO(t3), \
+       PTREGS_INFO(t4), \
+       PTREGS_INFO(t5), \
+       PTREGS_INFO(t6)
+
+#define UNW_PC_IDX 0
+#define UNW_SP_IDX 2
+
+/* Use default rules. The stack pointer should be set from the CFA.
+   And the instruction pointer should be set from the return address
+   column (which normally is the return register (regs[31]). */
+
+static inline void arch_unw_init_frame_info(struct unwind_frame_info *info,
+                                            /*const*/ struct pt_regs *regs,
+                                           int sanitize)
+{
+       if (&info->regs == regs) { /* happens when unwinding kernel->user */
+               info->call_frame = 1;
+               return;
+       }
+
+       memset(info, 0, sizeof(*info));
+       /* XXX handle sanitize??? */
+       info->regs = *regs;
+}
+
+#endif /* _STP_RISCV_UNWIND_H */
index 5c68a5f033b8a35d045e1e64d19d878af5d1dd8e..ce94ad3ec2946093254e19b27291caf6cf2e92da 100644 (file)
@@ -36,6 +36,8 @@ struct unwind_frame_info
 #include "arm64.h"
 #elif defined (__mips__)
 #include "mips.h"
+#elif defined (__riscv)
+#include "riscv.h"
 #else
 #error "Unsupported dwarf unwind architecture"
 #endif
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