[PATCH] [AArch64] Optional trapping exceptions support.

Trapping exceptions in AArch64 are optional.  The relevant exception
control bits in FPCR are are defined as RES0 hence the absence of
support can be detected by reading back the FPCR and comparing with
the desired value.

diff --git a/ChangeLog b/ChangeLog
index 51020ec5c7bf4a5bd871d0d214d01d7a541cdc81..88b70f1a7c0ea3c7a9d3ce17273dbcfdd20a62bf 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2014-03-07  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): Detect and
+       error absence of trapping exception support.
+       * sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Likewise.
+
 2014-03-07  Joseph Myers  <joseph@codesourcery.com>
 
        * catgets/Makefile (tests-special): Add $(objpfx)sample.SJIS.cat.

diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index d97699981f87cb0c0b935c03661d6b870329e157..07a4bbb58ef13a112315269481c747a1e1cf5239 100644 (file)
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -35,5 +35,18 @@ feenableexcept (int excepts)
 
   _FPU_SETCW (fpcr);
 
+  /* Trapping exceptions are optional in AArch64 the relevant enable
+     bits in FPCR are RES0 hence the absence of support can be
+     detected by reading back the FPCR and comparing with the required
+     value.  */
+  if (excepts)
+    {
+      fpu_control_t updated_fpcr;
+
+      _FPU_GETCW (updated_fpcr);
+      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+       return -1;
+    }
+
   return original_excepts;
 }

diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c
index 443c705d22ff9092816fb5ba5e78dcb7d5d6d9cd..a2434e37b0614997e81ee67ac362d59f501644cc 100644 (file)
--- a/sysdeps/aarch64/fpu/fesetenv.c
+++ b/sysdeps/aarch64/fpu/fesetenv.c
@@ -24,6 +24,7 @@ fesetenv (const fenv_t *envp)
 {
   fpu_control_t fpcr;
   fpu_fpsr_t fpsr;
+  fpu_control_t updated_fpcr;
 
   _FPU_GETCW (fpcr);
   _FPU_GETFPSR (fpsr);
@@ -51,6 +52,15 @@ fesetenv (const fenv_t *envp)
 
   _FPU_SETCW (fpcr);
 
+  /* Trapping exceptions are optional in AArch64 the relevant enable
+     bits in FPCR are RES0 hence the absence of support can be
+     detected by reading back the FPCR and comparing with the required
+     value.  */
+
+  _FPU_GETCW (updated_fpcr);
+  if ((updated_fpcr & fpcr) != fpcr)
+    return 1;
+
   return 0;
 }