Initializing TTBR0 to inner/outer WB

While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.

The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.

The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.

Adopted suggestion given by Richard offline to avoid using jump.

libgloss/
	* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
	cacheable WB, and no allocate on WB for arch with multiprocessor
	extension.

diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu-init/rdimon-aem.S
index 19814c6dfbeac2fb6c4ec65423cb7a7c05b47ccb..95b86e4d4400bad1101d7d632a0d0bbe5afbc1ea 100644 (file)
--- a/libgloss/arm/cpu-init/rdimon-aem.S
+++ b/libgloss/arm/cpu-init/rdimon-aem.S
@@ -127,7 +127,16 @@ spin:
     mcr         15, 0, r4, cr2, cr0, 2  @ Write TTBCR
     adr         r4, page_table_addr    @ Load the base for vectors
     ldr         r4, [r4]
-    add         r4, r4, #1             @ Page tables inner cacheable
+    mrc         p15, 0, r0, c0, c0, 5   @ read MPIDR
+    tst         r0, #0x80000000         @ bis[31]
+    @ Set page table flags - there are two page table flag formats for the
+    @ architecture.  For systems without multiprocessor extensions we use 0x1
+    @ which is Inner cacheable/Outer non-cacheable.  For systems with
+    @ multiprocessor extensions we use 0x59 which is Inner/Outer write-back,
+    @ no write-allocate, and cacheable.  See the ARMARM-v7AR for more details.
+    it          ne
+    addne       r4, r4, #0x58
+    add         r4, r4, #1
 
     mcr         15, 0, r4, cr2, cr0, 0  @ Write TTBR0