Fix support ARC processors without barrel-shifter

crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.

Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.

libgloss/ChangeLog

2016-04-29  Anton Kolesov  <anton.kolesov@synopsys.com>

        * arc/crt0.S: Fix support for processors without barrel-shifter.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

diff --git a/libgloss/arc/crt0.S b/libgloss/arc/crt0.S
index b93b63e4cc1f4e871ef3f187fa72d0a938bcc33c..99c871f21973aab92e796e6f8ebc3af023c01491 100644 (file)
--- a/libgloss/arc/crt0.S
+++ b/libgloss/arc/crt0.S
@@ -135,7 +135,12 @@ __start:
        mov_s   r2, @__sbss_start       ; r2 = start of the bss section
        sub     r3, @_end, r2           ; r3 = size of the bss section in bytes
        ; set up the loop counter register to the size (in words) of the bss section
-       asr.f   lp_count, r3, 2
+#if defined (__ARC_BARREL_SHIFTER__)
+       asr.f        lp_count, r3, 2
+#else
+       asr_s        r13, r3
+       asr.f        lp_count, r13
+#endif
 #if defined (__ARC600__)
        ; loop to zero out the bss.  Enter loop only if lp_count != 0
        lpnz    @.Lend_zbss