+2019-01-09 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * manual/tunables.texi (glibc.cpu.name): Add ares tunable.
+ * sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
+ __memcpy_falkor for ares.
+ * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
+ Add new define.
+ * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
+ Add ares cpu.
+
2019-01-07 H.J. Lu <hongjiu.lu@intel.com>
[BZ #24066]
The @code{glibc.cpu.name=xxx} tunable allows the user to tell @theglibc{} to
assume that the CPU is @code{xxx} where xxx may have one of these values:
@code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99},
-@code{thunderx2t99p1}.
+@code{thunderx2t99p1}, @code{ares}.
This tunable is specific to aarch64.
@end deftp
libc_ifunc (__libc_memcpy,
(IS_THUNDERX (midr)
? __memcpy_thunderx
- : (IS_FALKOR (midr) || IS_PHECDA (midr)
+ : (IS_FALKOR (midr) || IS_PHECDA (midr) || IS_ARES (midr)
? __memcpy_falkor
: (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr)
? __memcpy_thunderx2
{"thunderx2t99", 0x431F0AF0},
{"thunderx2t99p1", 0x420F5160},
{"phecda", 0x680F0000},
+ {"ares", 0x411FD0C0},
{"generic", 0x0}
};
#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \
&& MIDR_PARTNUM(midr) == 0x000)
+#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
+ && MIDR_PARTNUM(midr) == 0xd0c)
struct cpu_features
{