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RISC-V: Add hard float support for 32-bit CPUs
authorZong Li <zongbox@gmail.com>
Fri, 30 Nov 2018 09:16:38 +0000 (17:16 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 27 Aug 2020 15:17:42 +0000 (08:17 -0700)
commit941a55cf590ed23fdca9efff291f1ef82112bd6f
tree7fe7351bda1831df355e731cf490c5899879f898tree
parent5b6113d62efabb123db433b14adddd4a5fb6b7eccommit | diff
RISC-V: Add hard float support for 32-bit CPUs

This patch adds support for hardware floating-point support for the
RV32IF and RV32IFD platforms.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
sysdeps/riscv/rv32/rvd/s_lrint.c [new file with mode: 0644] blob
sysdeps/riscv/rv32/rvd/s_lround.c [new file with mode: 0644] blob
sysdeps/riscv/rv32/rvf/s_lrintf.c [new file with mode: 0644] blob
sysdeps/riscv/rv32/rvf/s_lroundf.c [new file with mode: 0644] blob
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