These have been defined incorrectly, as per specification and CPU
implementations SXE is bit 6 and UXE is bit 7. This was noticed when
tracking down our test suite mmu test failures.
Test Suite: https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mmu.c#L68-L72
Spec: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf
See section 8.4.8 Instruction Translation Lookaside Buffer Way y Translate
Registers where these are defined.