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author	Joe Ramsay <Joe.Ramsay@arm.com>
	Thu, 5 Oct 2023 16:10:52 +0000 (17:10 +0100)
committer	Szabolcs Nagy <szabolcs.nagy@arm.com>
	Mon, 23 Oct 2023 14:00:45 +0000 (15:00 +0100)
commit	31aaf6fed986fade042f9ffe7535d8b3f2c173a2
tree	5417d6dffd8eefa74a1506a792ed40330205ce31	tree
parent	067a34156c19fb3c53824e37d70820c0ce5b87b2	commit \| diff

aarch64: Add vector implementations of exp10 routines

Double-precision routines either reuse the exp table (AdvSIMD) or use
SVE FEXPA intruction.

13 files changed:

sysdeps/aarch64/fpu/Makefile		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/Versions		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/bits/math-vector.h		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/exp10_advsimd.c	[new file with mode: 0644]	blob
sysdeps/aarch64/fpu/exp10_sve.c	[new file with mode: 0644]	blob
sysdeps/aarch64/fpu/exp10f_advsimd.c	[new file with mode: 0644]	blob
sysdeps/aarch64/fpu/exp10f_sve.c	[new file with mode: 0644]	blob
sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/test-double-sve-wrappers.c		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c		diff \| blob \| blame \| history
sysdeps/aarch64/fpu/test-float-sve-wrappers.c		diff \| blob \| blame \| history
sysdeps/aarch64/libm-test-ulps		diff \| blob \| blame \| history
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist		diff \| blob \| blame \| history

GNU C Library master sources

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