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Bug 445415 - arm64 front end: alignment checks missing for atomic instructions.
authorJulian Seward <jseward@acm.org>
Sat, 13 Nov 2021 08:27:01 +0000 (09:27 +0100)
committerJulian Seward <jseward@acm.org>
Sat, 13 Nov 2021 08:27:01 +0000 (09:27 +0100)
commit2be719921e700a9ac9b85f470ed87cb8adf8151b
treef68d6ed35caf5cb04f9722e110d7d2e61183f820
parent92e56be59b3f32e7c749bfabcd6d775b779001ab
Bug 445415 - arm64 front end: alignment checks missing for atomic instructions.

For the arm64 front end, none of the atomic instructions have address
alignment checks included in their IR.  They all should.  The effect of
missing alignment checks in the IR is that, since this IR will in most cases
be translated back to atomic instructions in the back end, we will get
alignment traps (SIGBUS) on the host side and not on the guest side, which is
(very) incorrect behaviour of the simulation.
NEWS
VEX/priv/guest_arm64_toIR.c
VEX/priv/host_arm64_defs.c
VEX/priv/host_arm64_isel.c
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