2 * vr4300.S -- CPU specific support routines
4 * Copyright (c) 1995,1996 Cygnus Support
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21 /* This file contains 32 bit assembly code. */
30 # Taken from "R4300 Preliminary RISC Processor Specification
31 # Revision 2.0 January 1995" page 39: "The Count
32 # register... increments at a constant rate... at one-half the
34 # We can use this fact to provide small polled delays.
35 .globl __cpu_timer_poll
39 # in: a0 = (unsigned int) number of PClock ticks to wait for
42 # The Vr4300 counter updates at half PClock, so divide by 2 to
44 bnezl a0, 1f # continue if delta non-zero
45 srl a0, a0, 1 # divide ticks by 2 {DELAY SLOT}
46 # perform a quick return to the caller:
50 mfc0 v0, $9 # C0_COUNT: get current counter value
53 # We cannot just do the simple test, of adding our delta onto
54 # the current value (ignoring overflow) and then checking for
55 # equality. The counter is incrementing every two PClocks,
56 # which means the counter value can change between
57 # instructions, making it hard to sample at the exact value
60 # However, we do know that our entry delta value is less than
61 # half the number space (since we divide by 2 on entry). This
62 # means we can use a difference in signs to indicate timer
64 addu a0, v0, a0 # unsigned add (ignore overflow)
65 # We know have our end value (which will have been
66 # sign-extended to fill the 64bit register value).
68 # get current counter value:
69 mfc0 v0, $9 # C0_COUNT
72 # This is an unsigned 32bit subtraction:
73 subu v0, a0, v0 # delta = (end - now) {DELAY SLOT}
74 bgtzl v0, 2b # looping back is most likely
76 # We have now been delayed (in the foreground) for AT LEAST
77 # the required number of counter ticks.
78 j ra # return to caller
83 # Flush the processor caches to memory:
89 # NOTE: The Vr4300 *CANNOT* have any secondary cache (bit 17
90 # of the CONFIG registered is hard-wired to 1). We just
91 # provide code to flush the Data and Instruction caches.
93 # Even though the Vr4300 has hard-wired cache and cache line
94 # sizes, we still interpret the relevant Config register
95 # bits. This allows this code to be used for other conforming
96 # MIPS architectures if desired.
98 # Get the config register
102 li a1, 1 # a useful constant
104 srl a2, a0, 9 # bits 11..9 for instruction cache size
105 andi a2, a2, 0x7 # 3bits of information
106 add a2, a2, 12 # get full power-of-2 value
107 sllv a2, a1, a2 # instruction cache size
109 srl a3, a0, 6 # bits 8..6 for data cache size
110 andi a3, a3, 0x7 # 3bits of information
111 add a3, a3, 12 # get full power-of-2 value
112 sllv a3, a1, a3 # data cache size
114 li a1, (1 << 5) # check IB (instruction cache line size)
115 and a1, a0, a1 # mask against the CONFIG register value
116 beqz a1, 1f # branch on result of delay slot operation
118 li a1, 32 # non-zero, then 32bytes
125 li t0, (1 << 4) # check DB (data cache line size)
126 and a0, a0, t0 # mask against the CONFIG register value
127 beqz a0, 3f # branch on result of delay slot operation
129 li a0, 32 # non-zero, then 32bytes
136 # a0 = data cache line size
137 # a1 = instruction cache line size
138 # a2 = instruction cache size
139 # a3 = data cache size
141 lui t0, ((K0BASE >> 16) & 0xFFFF)
142 ori t0, t0, (K0BASE & 0xFFFF)
143 addu t1, t0, a2 # end cache address
144 subu t2, a1, 1 # line size mask
145 not t2 # invert the mask
146 and t3, t0, t2 # get start address
148 and t1, t2 # get end address
150 cache INDEX_INVALIDATE_I,0(t3)
154 addu t1, t0, a3 # end cache address
155 subu t2, a0, 1 # line size mask
156 not t2 # invert the mask
157 and t3, t0, t2 # get start address
159 and t1, t2 # get end address
161 cache INDEX_WRITEBACK_INVALIDATE_D,0(t3)
165 j ra # return to the caller
170 # NOTE: This variable should *NOT* be addressed relative to
171 # the $gp register since this code is executed before $gp is
172 # initialised... hence we leave it in the text area. This will
173 # cause problems if this routine is ever ROMmed:
189 # k0 and k1 available for use:
195 beq k0,$0,__buserr_do
197 # call the previous handler
203 # TODO: check that the cause is indeed a bus error
204 # - if not then just jump to the previous handler
209 lw k0,0(k1) # increment counter
219 addu k0,k0,4 # skip offending instruction
220 mtc0 k0,C0_EPC # update EPC
233 daddiu k0,k0,%lo(__buserr)
237 __exception_code_end:
241 .space (__exception_code_end - __exception_code)
242 # This subtracting two addresses is working
243 # but is not garenteed to continue working.
244 # The assemble reserves the right to put these
245 # two labels into different frags, and then
246 # cant take their difference.
250 .ent __default_buserr_handler
251 .globl __default_buserr_handler
252 __default_buserr_handler:
254 # attach our simple bus error handler:
262 lui a0,0x8000 # delay slot
267 # a0 = base vector table address
268 la a1,__exception_code_end
269 la a2,__exception_code
272 # there must be a better way of doing this????
289 .end __default_buserr_handler
291 .ent __restore_buserr_handler
292 .globl __restore_buserr_handler
293 __restore_buserr_handler:
295 # restore original (monitor) bus error handler
302 beq a1,$0,res_baseaddr
303 lui a0,0x8000 # delay slot
308 # a0 = base vector table address
309 la a1,__exception_code_end
310 la a3,__exception_code
313 # there must be a better way of doing this????
320 bne a1,$0,res_copyloop
325 .end __restore_buserr_handler
328 .globl __buserr_count
331 # restore original (monitor) bus error handler
333 # out: unsigned int __buserr_cnt
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