libgloss/bfin/include/sys/pll.h

   1 /*
   2  * The authors hereby grant permission to use, copy, modify, distribute,
   3  * and license this software and its documentation for any purpose, provided
   4  * that existing copyright notices are retained in all copies and that this
   5  * notice is included verbatim in any distributions. No written agreement,
   6  * license, or royalty fee is required for any of the authorized uses.
   7  * Modifications to this software may be copyrighted by their authors
   8  * and need not follow the licensing terms described here, provided that
   9  * the new terms are clearly indicated on the first page of each file where
  10  * they apply.
  11  */
  12
  13 /************************************************************************
  14  *
  15  * pll.h
  16  *
  17  * Copyright (C) 2008, 2009 Analog Devices, Inc.
  18  *
  19  ************************************************************************/
  20
  21 #ifndef __ASSEMBLER__
  22 #pragma once
  23 #pragma system_header
  24 #endif
  25
  26 #ifndef _PLL_H
  27 #define _PLL_H
  28
  29 #ifdef _MISRA_RULES
  30 #pragma diag(push)
  31 #pragma diag(suppress:misra_rule_6_3)
  32 #endif /* _MISRA_RULES */
  33
  34 #define NO_STARTUP_SET 0
  35 #define MAX_IN_STARTUP 1
  36
  37 #ifndef __ASSEMBLER__
  38
  39 enum clkctrl_t {
  40     /* no modification of PLL rates in CRT startup - default */
  41    no_startup_set=NO_STARTUP_SET,
  42
  43     /* CRT startup sets PLL rates to suitable maximum values */
  44    max_in_startup=MAX_IN_STARTUP
  45 };
  46
  47 /*
  48 ** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum
  49 ** speed performance rates.  The default version defined in the runtime-
  50 ** libraries defines __clk_ctrl to 0 which disables the feature.
  51 */
  52 extern enum clkctrl_t __clk_ctrl;
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 #if defined(__ADSPLPBLACKFIN__)
  59
  60 /* Sets SSEL and CSEL bits in PLL_DIV to passed values.
  61 ** Returns -1 on failure.
  62 */
  63 int pll_set_system_clocks(int _csel, int _ssel);
  64
  65 /*
  66 ** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT.
  67 ** Returns -1 on failure.
  68 */
  69 int pll_set_system_vco(int _msel, int _df, int _lockcnt);
  70
  71 #endif /* __ADSPLPBLACKFIN__ */
  72
  73 #ifdef __cplusplus
  74 }
  75 #endif
  76
  77 #endif /* __ASSEMBLER__ */
  78
  79 #ifdef _MISRA_RULES
  80 #pragma diag(pop)
  81 #endif /* _MISRA_RULES */
  82
  83 #endif /* _PLL_H */
  84