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sourceware.org Git - newlib-cygwin.git/blob - libgloss/bfin/include/defBF539.h
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2 * The authors hereby grant permission to use, copy, modify, distribute,
3 * and license this software and its documentation for any purpose, provided
4 * that existing copyright notices are retained in all copies and that this
5 * notice is included verbatim in any distributions. No written agreement,
6 * license, or royalty fee is required for any of the authorized uses.
7 * Modifications to this software may be copyrighted by their authors
8 * and need not follow the licensing terms described here, provided that
9 * the new terms are clearly indicated on the first page of each file where
14 ** Copyright (C) 2008, 2009 Analog Devices, Inc.
16 ************************************************************************************
18 ** This include file contains a list of macro "defines" to enable the programmer
19 ** to use symbolic names for Stirling peripherals.
25 /* Include all Core registers and bit definitions */
26 #include <def_LPBlackfin.h>
30 #pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
31 #pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
32 #endif /* _MISRA_RULES */
34 /*********************************************************************************** */
35 /* System MMR Register Map */
36 /*********************************************************************************** */
37 /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
38 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
39 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
40 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
41 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
42 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
43 #define CHIPID 0xFFC00014 /* Chip ID Register */
46 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
47 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
48 #define SYSCR 0xFFC00104 /* System Configuration registe */
49 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
50 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
51 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
52 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
53 #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
54 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
55 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
56 #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
57 #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
58 #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
59 #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
60 #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
61 #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
64 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
65 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
66 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
67 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
70 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
71 #define RTC_STAT 0xFFC00300 /* RTC Status Register */
72 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
73 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
74 #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
75 #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
76 #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
77 #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
80 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
81 #define UART0_THR 0xFFC00400 /* Transmit Holding register */
82 #define UART0_RBR 0xFFC00400 /* Receive Buffer register */
83 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
84 #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
85 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
86 #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
87 #define UART0_LCR 0xFFC0040C /* Line Control Register */
88 #define UART0_MCR 0xFFC00410 /* Modem Control Register */
89 #define UART0_LSR 0xFFC00414 /* Line Status Register */
90 #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
91 #define UART0_GCTL 0xFFC00424 /* Global Control Register */
94 /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
95 #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
96 #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
97 #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
98 #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
99 #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
100 #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
101 #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
104 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
105 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
106 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
107 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
108 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
110 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
111 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
112 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
113 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
115 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
116 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
117 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
118 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
120 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
121 #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
122 #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
125 /* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
126 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
127 #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
128 #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
129 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
130 #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
131 #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
132 #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
133 #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
134 #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
135 #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
136 #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
137 #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
138 #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
139 #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
140 #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
141 #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
142 #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
145 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
146 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
147 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
148 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
149 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
150 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
151 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
152 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
153 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
154 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
155 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
156 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
157 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
158 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
159 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
160 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
161 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
162 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
163 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
164 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
165 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
166 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
167 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
170 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
171 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
172 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
173 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
174 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
175 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
176 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
177 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
178 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
179 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
180 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
181 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
182 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
183 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
184 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
185 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
186 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
187 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
188 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
189 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
190 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
191 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
192 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
195 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
196 /* Asynchronous Memory Controller */
197 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
198 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
199 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
201 /* SDRAM Controller */
202 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
203 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
204 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
205 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
209 /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
211 #define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
212 #define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
214 /* Alternate deprecated register names (below) provided for backwards code compatibility */
215 #define DMA0_TCPER DMAC0_TC_PER
216 #define DMA0_TCCNT DMAC0_TC_CNT
219 /* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
221 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
222 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
223 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
224 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
225 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
226 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
227 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
228 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
229 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
230 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
231 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
232 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
233 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
235 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
236 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
237 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
238 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
239 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
240 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
241 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
242 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
243 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
244 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
245 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
246 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
247 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
249 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
250 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
251 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
252 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
253 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
254 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
255 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
256 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
257 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
258 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
259 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
260 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
261 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
263 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
264 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
265 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
266 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
267 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
268 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
269 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
270 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
271 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
272 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
273 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
274 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
275 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
277 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
278 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
279 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
280 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
281 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
282 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
283 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
284 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
285 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
286 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
287 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
288 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
289 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
291 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
292 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
293 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
294 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
295 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
296 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
297 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
298 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
299 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
300 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
301 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
302 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
303 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
305 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
306 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
307 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
308 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
309 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
310 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
311 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
312 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
313 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
314 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
315 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
316 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
317 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
319 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
320 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
321 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
322 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
323 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
324 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
325 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
326 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
327 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
328 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
329 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
330 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
331 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
333 #define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
334 #define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
335 #define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
336 #define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
337 #define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
338 #define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
339 #define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
340 #define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
341 #define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
342 #define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
343 #define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
344 #define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
345 #define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
347 #define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
348 #define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
349 #define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
350 #define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
351 #define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
352 #define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
353 #define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
354 #define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
355 #define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
356 #define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
357 #define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
358 #define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
359 #define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
361 #define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
362 #define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
363 #define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
364 #define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
365 #define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
366 #define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
367 #define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
368 #define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
369 #define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
370 #define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
371 #define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
372 #define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
373 #define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
375 #define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
376 #define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
377 #define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
378 #define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
379 #define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
380 #define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
381 #define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
382 #define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
383 #define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
384 #define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
385 #define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
386 #define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
387 #define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
390 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
391 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
392 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */
393 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
394 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
395 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
398 /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
399 #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
400 #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
401 #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
402 #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
403 #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
404 #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
405 #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
406 #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
407 #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
408 #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
409 #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
410 #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
411 #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
412 #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
413 #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
414 #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
416 /* the following are for backwards compatibility */
417 #define TWI0_PRESCALE TWI0_CONTROL
418 #define TWI0_INT_SRC TWI0_INT_STAT
419 #define TWI0_INT_ENABLE TWI0_INT_MASK
422 /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
424 /* GPIO Port C Register Names */
425 #define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */
426 #define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */
427 #define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */
428 #define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */
429 #define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */
430 #define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
431 #define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
433 /* GPIO Port D Register Names */
434 #define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */
435 #define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */
436 #define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */
437 #define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */
438 #define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */
439 #define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
440 #define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
442 /* GPIO Port E Register Names */
443 #define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */
444 #define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */
445 #define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */
446 #define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */
447 #define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */
448 #define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
449 #define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
451 /* Deprecate old macros */
452 #define GPIO_C_DAT GPIO_C_D
453 #define GPIO_C_CLR GPIO_C_C
454 #define GPIO_C_SET GPIO_C_S
455 #define GPIO_C_TGL GPIO_C_T
457 #define GPIO_D_DAT GPIO_D_D
458 #define GPIO_D_CLR GPIO_D_C
459 #define GPIO_D_SET GPIO_D_S
460 #define GPIO_D_TGL GPIO_D_T
462 #define GPIO_E_DAT GPIO_E_D
463 #define GPIO_E_CLR GPIO_E_C
464 #define GPIO_E_SET GPIO_E_S
465 #define GPIO_E_TGL GPIO_E_T
467 /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
469 #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
470 #define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
472 /* Alternate deprecated register names (below) provided for backwards code compatibility */
473 #define DMA1_TCPER DMAC1_TC_PER
474 #define DMA1_TCCNT DMAC1_TC_CNT
477 /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
478 #define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
479 #define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
480 #define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
481 #define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
482 #define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
483 #define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
484 #define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
485 #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
486 #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
487 #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
488 #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
489 #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
490 #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
492 #define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
493 #define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
494 #define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
495 #define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
496 #define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
497 #define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
498 #define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
499 #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
500 #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
501 #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
502 #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
503 #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
504 #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
506 #define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
507 #define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
508 #define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
509 #define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
510 #define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
511 #define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
512 #define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
513 #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
514 #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
515 #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
516 #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
517 #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
518 #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
520 #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
521 #define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
522 #define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
523 #define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
524 #define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
525 #define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
526 #define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
527 #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
528 #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
529 #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
530 #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
531 #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
532 #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
534 #define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
535 #define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
536 #define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
537 #define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
538 #define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
539 #define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
540 #define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
541 #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
542 #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
543 #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
544 #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
545 #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
546 #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
548 #define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
549 #define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
550 #define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
551 #define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
552 #define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
553 #define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
554 #define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
555 #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
556 #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
557 #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
558 #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
559 #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
560 #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
562 #define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
563 #define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
564 #define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
565 #define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
566 #define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
567 #define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
568 #define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
569 #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
570 #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
571 #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
572 #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
573 #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
574 #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
576 #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
577 #define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
578 #define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
579 #define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
580 #define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
581 #define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
582 #define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
583 #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
584 #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
585 #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
586 #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
587 #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
588 #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
590 #define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
591 #define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
592 #define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
593 #define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
594 #define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
595 #define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
596 #define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
597 #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
598 #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
599 #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
600 #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
601 #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
602 #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
604 #define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
605 #define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
606 #define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
607 #define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
608 #define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
609 #define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
610 #define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
611 #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
612 #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
613 #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
614 #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
615 #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
616 #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
618 #define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
619 #define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
620 #define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
621 #define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
622 #define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
623 #define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
624 #define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
625 #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
626 #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
627 #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
628 #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
629 #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
630 #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
632 #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
633 #define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
634 #define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
635 #define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
636 #define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
637 #define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
638 #define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
639 #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
640 #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
641 #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
642 #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
643 #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
644 #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
646 #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
647 #define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
648 #define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
649 #define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
650 #define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
651 #define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
652 #define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
653 #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
654 #define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
655 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
656 #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
657 #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
658 #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
660 #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
661 #define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
662 #define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
663 #define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
664 #define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
665 #define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
666 #define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
667 #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
668 #define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
669 #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
670 #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
671 #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
672 #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
674 #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
675 #define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
676 #define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
677 #define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
678 #define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
679 #define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
680 #define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
681 #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
682 #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
683 #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
684 #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
685 #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
686 #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
688 #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
689 #define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
690 #define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
691 #define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
692 #define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
693 #define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
694 #define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
695 #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
696 #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
697 #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
698 #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
699 #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
700 #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
703 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
704 #define UART1_THR 0xFFC02000 /* Transmit Holding register */
705 #define UART1_RBR 0xFFC02000 /* Receive Buffer register */
706 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
707 #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
708 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
709 #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
710 #define UART1_LCR 0xFFC0200C /* Line Control Register */
711 #define UART1_MCR 0xFFC02010 /* Modem Control Register */
712 #define UART1_LSR 0xFFC02014 /* Line Status Register */
713 #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
714 #define UART1_GCTL 0xFFC02024 /* Global Control Register */
717 /* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
718 #define UART2_THR 0xFFC02100 /* Transmit Holding register */
719 #define UART2_RBR 0xFFC02100 /* Receive Buffer register */
720 #define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
721 #define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
722 #define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
723 #define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
724 #define UART2_LCR 0xFFC0210C /* Line Control Register */
725 #define UART2_MCR 0xFFC02110 /* Modem Control Register */
726 #define UART2_LSR 0xFFC02114 /* Line Status Register */
727 #define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
728 #define UART2_GCTL 0xFFC02124 /* Global Control Register */
731 /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
732 #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
733 #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
734 #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
735 #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
736 #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
737 #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
738 #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
739 #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
740 #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
741 #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
742 #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
743 #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
744 #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
745 #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
746 #define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
747 #define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
749 /* the following are for backwards compatibility */
750 #define TWI1_PRESCALE TWI1_CONTROL
751 #define TWI1_INT_SRC TWI1_INT_STAT
752 #define TWI1_INT_ENABLE TWI1_INT_MASK
755 /* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
756 #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
757 #define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
758 #define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
759 #define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
760 #define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
761 #define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
762 #define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
765 /* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
766 #define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
767 #define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
768 #define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
769 #define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
770 #define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
771 #define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
772 #define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
775 /* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
776 #define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
777 #define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
778 #define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
779 #define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
780 #define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
781 #define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
782 #define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
783 #define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
784 #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
785 #define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
786 #define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
787 #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
788 #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
789 #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
790 #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
791 #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
792 #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
793 #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
794 #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
795 #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
796 #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
797 #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
800 /* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
801 #define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
802 #define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
803 #define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
804 #define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
805 #define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
806 #define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
807 #define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
808 #define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
809 #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
810 #define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
811 #define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
812 #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
813 #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
814 #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
815 #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
816 #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
817 #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
818 #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
819 #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
820 #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
821 #define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
822 #define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
825 /* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
827 #define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
828 #define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
830 #define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
831 #define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
833 #define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
834 #define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
836 #define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
837 #define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
839 #define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
840 #define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
842 #define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
843 #define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
845 #define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
846 #define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
847 #define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
849 #define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
850 #define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
851 #define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
852 #define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
853 #define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
854 #define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
855 #define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
856 #define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
857 #define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
858 #define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
859 #define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
860 #define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
861 #define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
862 #define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
863 #define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
865 #define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
866 #define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
867 #define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
868 #define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
869 #define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
870 #define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
871 #define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
872 #define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
874 #define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
875 #define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
876 #define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
877 #define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
878 #define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
880 #define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
881 #define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
882 #define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
883 #define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
884 #define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
886 #define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
887 #define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
888 #define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
889 #define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
890 #define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
892 #define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
893 #define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
894 #define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
895 #define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
896 #define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
898 #define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
899 #define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
900 #define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
901 #define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
902 #define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
904 #define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
905 #define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
906 #define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
907 #define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
908 #define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
910 #define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
911 #define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
912 #define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
913 #define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
914 #define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
916 #define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
917 #define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
918 #define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
919 #define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
920 #define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
922 #define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
923 #define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
924 #define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
925 #define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
926 #define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
928 #define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
929 #define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
930 #define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
931 #define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
932 #define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
934 #define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
935 #define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
937 #define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
938 #define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
939 #define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
940 #define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
942 #define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
943 #define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
945 #define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
946 #define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
947 #define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
948 #define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
949 #define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
950 #define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
951 #define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
952 #define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
953 #define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
954 #define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
955 #define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
956 #define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
957 #define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
958 #define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
959 #define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
961 #define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
962 #define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
963 #define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
966 /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
967 /* For Mailboxes 0-15 */
968 #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
969 #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
970 #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
971 #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
972 #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
973 #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
974 #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
975 #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
976 #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
977 #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
978 #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
979 #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
980 #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
982 /* For Mailboxes 16-31 */
983 #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
984 #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
985 #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
986 #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
987 #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
988 #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
989 #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
990 #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
991 #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
992 #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
993 #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
994 #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
995 #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
997 #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
998 #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
1000 #define CAN_DEBUG 0xFFC02A88 /* Debug Register */
1001 /* the following is for backwards compatibility */
1002 #define CAN_CNF CAN_DEBUG
1004 #define CAN_STATUS 0xFFC02A8C /* Global Status Register */
1005 #define CAN_CEC 0xFFC02A90 /* Error Counter Register */
1006 #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
1007 #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
1008 #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
1009 #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
1010 #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
1011 #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
1012 #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
1013 #define CAN_ESR 0xFFC02AB4 /* Error Status Register */
1014 #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
1015 #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
1016 #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
1018 /* Mailbox Acceptance Masks */
1019 #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
1020 #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
1021 #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
1022 #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
1023 #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
1024 #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
1025 #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
1026 #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
1027 #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
1028 #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
1029 #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
1030 #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
1031 #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
1032 #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
1033 #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
1034 #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
1035 #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
1036 #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
1037 #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
1038 #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
1039 #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
1040 #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
1041 #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
1042 #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
1043 #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
1044 #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
1045 #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
1046 #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
1047 #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
1048 #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
1049 #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
1050 #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
1052 #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
1053 #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
1054 #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
1055 #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
1056 #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
1057 #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
1058 #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
1059 #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
1060 #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
1061 #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
1062 #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
1063 #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
1064 #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
1065 #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
1066 #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
1067 #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
1068 #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
1069 #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
1070 #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
1071 #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
1072 #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
1073 #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
1074 #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
1075 #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
1076 #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
1077 #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
1078 #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
1079 #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
1080 #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
1081 #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
1082 #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
1083 #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
1085 /* CAN Acceptance Mask Macros */
1086 #define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
1087 #define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
1089 /* Mailbox Registers */
1090 #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
1091 #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
1092 #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
1093 #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
1094 #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
1095 #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
1096 #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
1097 #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
1099 #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
1100 #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
1101 #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
1102 #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
1103 #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
1104 #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
1105 #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
1106 #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
1108 #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
1109 #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
1110 #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
1111 #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
1112 #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
1113 #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
1114 #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
1115 #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
1117 #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
1118 #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
1119 #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
1120 #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
1121 #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
1122 #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
1123 #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
1124 #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
1126 #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
1127 #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
1128 #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
1129 #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
1130 #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
1131 #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
1132 #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
1133 #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
1135 #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
1136 #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
1137 #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
1138 #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
1139 #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
1140 #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
1141 #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
1142 #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
1144 #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
1145 #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
1146 #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
1147 #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
1148 #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
1149 #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
1150 #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
1151 #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
1153 #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
1154 #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
1155 #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
1156 #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
1157 #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
1158 #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
1159 #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
1160 #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
1162 #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
1163 #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
1164 #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
1165 #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
1166 #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
1167 #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
1168 #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
1169 #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
1171 #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
1172 #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
1173 #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
1174 #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
1175 #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
1176 #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
1177 #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
1178 #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
1180 #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
1181 #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
1182 #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
1183 #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
1184 #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
1185 #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
1186 #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
1187 #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
1189 #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
1190 #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
1191 #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
1192 #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
1193 #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
1194 #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
1195 #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
1196 #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
1198 #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
1199 #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
1200 #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
1201 #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
1202 #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
1203 #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
1204 #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
1205 #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
1207 #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
1208 #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
1209 #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
1210 #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
1211 #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
1212 #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
1213 #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
1214 #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
1216 #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
1217 #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
1218 #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
1219 #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
1220 #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
1221 #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
1222 #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
1223 #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
1225 #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
1226 #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
1227 #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
1228 #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
1229 #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
1230 #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
1231 #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
1232 #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
1234 #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
1235 #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
1236 #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
1237 #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
1238 #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
1239 #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
1240 #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
1241 #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
1243 #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
1244 #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
1245 #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
1246 #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
1247 #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
1248 #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
1249 #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
1250 #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
1252 #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
1253 #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
1254 #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
1255 #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
1256 #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
1257 #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
1258 #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
1259 #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
1261 #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
1262 #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
1263 #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
1264 #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
1265 #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
1266 #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
1267 #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
1268 #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
1270 #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
1271 #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
1272 #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
1273 #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
1274 #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
1275 #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
1276 #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
1277 #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
1279 #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
1280 #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
1281 #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
1282 #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
1283 #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
1284 #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
1285 #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
1286 #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
1288 #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
1289 #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
1290 #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
1291 #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
1292 #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
1293 #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
1294 #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
1295 #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
1297 #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
1298 #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
1299 #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
1300 #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
1301 #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
1302 #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
1303 #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
1304 #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
1306 #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
1307 #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
1308 #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
1309 #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
1310 #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
1311 #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
1312 #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
1313 #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
1315 #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
1316 #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
1317 #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
1318 #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
1319 #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
1320 #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
1321 #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
1322 #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
1324 #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
1325 #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
1326 #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
1327 #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
1328 #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
1329 #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
1330 #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
1331 #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
1333 #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
1334 #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
1335 #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
1336 #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
1337 #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
1338 #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
1339 #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
1340 #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
1342 #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
1343 #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
1344 #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
1345 #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
1346 #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
1347 #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
1348 #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
1349 #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
1351 #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
1352 #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
1353 #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
1354 #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
1355 #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
1356 #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
1357 #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
1358 #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
1360 #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
1361 #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
1362 #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
1363 #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
1364 #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
1365 #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
1366 #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
1367 #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
1369 #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
1370 #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
1371 #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
1372 #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
1373 #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
1374 #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
1375 #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
1376 #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
1378 /* CAN Mailbox Area Macros */
1379 #define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
1380 #define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
1381 #define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
1382 #define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
1383 #define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
1384 #define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
1385 #define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
1386 #define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
1389 /*********************************************************************************** */
1390 /* System MMR Register Bits and Macros */
1391 /******************************************************************************* */
1393 /* ********************* PLL AND RESET MASKS ************************ */
1395 #define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
1396 #define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
1397 #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1398 #define PLL_OFF 0x0002 /* Shut off PLL clocks */
1399 #define STOPCK_OFF 0x0008 /* Core clock off */
1400 #define STOPCK 0x0008 /* Core Clock Off */
1401 #define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
1402 #define IN_DELAY 0x0014 /* EBIU Input Delay Select */
1403 #define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
1404 #define BYPASS 0x0100 /* Bypass the PLL */
1405 #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
1407 /* PLL_CTL Macros */
1409 #define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1410 #define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
1411 #define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
1413 #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1414 #define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
1415 #define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
1416 #endif /* _MISRA_RULES */
1419 #define SSEL 0x000F /* System Select */
1420 #define CSEL 0x0030 /* Core Select */
1421 #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1422 #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1423 #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1424 #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1426 #define SCLK_DIV(x) (x) /* SCLK = VCO / x */
1428 #define CCLK_DIV1 0x0000 /* CCLK = VCO / 1 */
1429 #define CCLK_DIV2 0x0010 /* CCLK = VCO / 2 */
1430 #define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
1431 #define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
1433 /* PLL_DIV Macros */
1435 #define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1437 #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1438 #endif /* _MISRA_RULES */
1440 /* PLL_STAT Masks */
1441 #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1442 #define FULL_ON 0x0002 /* Processor In Full On Mode */
1443 #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1444 #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1447 #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1448 #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1449 #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1450 #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1451 #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1453 #define GAIN 0x000C /* Voltage Level Gain */
1454 #define GAIN_5 0x0000 /* GAIN = 5 */
1455 #define GAIN_10 0x0004 /* GAIN = 10 */
1456 #define GAIN_20 0x0008 /* GAIN = 20 */
1457 #define GAIN_50 0x000C /* GAIN = 50 */
1459 #define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1460 #define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1461 #define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1462 #define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1463 #define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1464 #define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1465 #define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1466 #define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1468 #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1469 #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1470 #define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
1471 #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
1474 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1475 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1476 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1477 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1478 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1481 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1482 #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1485 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
1487 /* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
1488 #define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
1489 #define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
1490 #define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
1491 #define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
1492 #define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
1493 #define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
1494 #define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
1495 #define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
1496 #define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
1497 #define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
1498 #define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
1499 #define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
1500 #define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
1501 #define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
1502 #define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
1503 #define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
1504 #define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
1505 #define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
1506 #define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
1507 #define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
1508 #define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
1509 #define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
1510 #define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
1511 #define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
1512 #define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
1513 #define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
1514 #define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
1515 #define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
1516 #define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
1517 #define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
1518 #define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
1519 #define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
1521 /* the following are for backwards compatibility */
1522 #define DMA0_ERR_IRQ DMAC0_ERR_IRQ
1523 #define DMA1_ERR_IRQ DMAC1_ERR_IRQ
1526 /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
1527 #define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
1528 #define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
1529 #define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
1530 #define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
1531 #define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
1532 #define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
1533 #define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
1534 #define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
1535 #define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
1536 #define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
1537 #define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
1538 #define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
1539 #define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
1540 #define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
1541 #define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
1542 #define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
1543 #define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
1544 #define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
1545 #define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
1546 #define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
1547 #define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
1548 #define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
1550 /* the following are for backwards compatibility */
1551 #define MDMA0_IRQ MDMA1_0_IRQ
1552 #define MDMA1_IRQ MDMA1_1_IRQ
1560 #endif /* _MISRA_RULES */
1562 /* SIC_IAR0 Macros */
1563 #define P0_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #0 assigned IVG #x */
1564 #define P1_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #1 assigned IVG #x */
1565 #define P2_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #2 assigned IVG #x */
1566 #define P3_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #3 assigned IVG #x */
1567 #define P4_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #4 assigned IVG #x */
1568 #define P5_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #5 assigned IVG #x */
1569 #define P6_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #6 assigned IVG #x */
1570 #define P7_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #7 assigned IVG #x */
1572 /* SIC_IAR1 Macros */
1573 #define P8_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #8 assigned IVG #x */
1574 #define P9_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #9 assigned IVG #x */
1575 #define P10_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #10 assigned IVG #x */
1576 #define P11_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #11 assigned IVG #x */
1577 #define P12_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #12 assigned IVG #x */
1578 #define P13_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #13 assigned IVG #x */
1579 #define P14_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #14 assigned IVG #x */
1580 #define P15_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #15 assigned IVG #x */
1582 /* SIC_IAR2 Macros */
1583 #define P16_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #16 assigned IVG #x */
1584 #define P17_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #17 assigned IVG #x */
1585 #define P18_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #18 assigned IVG #x */
1586 #define P19_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #19 assigned IVG #x */
1587 #define P20_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #20 assigned IVG #x */
1588 #define P21_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #21 assigned IVG #x */
1589 #define P22_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #22 assigned IVG #x */
1590 #define P23_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #23 assigned IVG #x */
1592 /* SIC_IAR3 Macros */
1593 #define P24_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #24 assigned IVG #x */
1594 #define P25_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #25 assigned IVG #x */
1595 #define P26_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #26 assigned IVG #x */
1596 #define P27_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #27 assigned IVG #x */
1597 #define P28_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #28 assigned IVG #x */
1598 #define P29_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #29 assigned IVG #x */
1599 #define P30_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #30 assigned IVG #x */
1600 #define P31_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #31 assigned IVG #x */
1602 /* SIC_IAR4 Macros */
1603 #define P32_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #32 assigned IVG #x */
1604 #define P33_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #33 assigned IVG #x */
1605 #define P34_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #34 assigned IVG #x */
1606 #define P35_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #35 assigned IVG #x */
1607 #define P36_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #36 assigned IVG #x */
1608 #define P37_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #37 assigned IVG #x */
1609 #define P38_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #38 assigned IVG #x */
1610 #define P39_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #39 assigned IVG #x */
1612 /* SIC_IAR5 Macros */
1613 #define P40_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #40 assigned IVG #x */
1614 #define P41_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #41 assigned IVG #x */
1615 #define P42_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #42 assigned IVG #x */
1616 #define P43_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #43 assigned IVG #x */
1617 #define P44_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #44 assigned IVG #x */
1618 #define P45_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #45 assigned IVG #x */
1619 #define P46_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #46 assigned IVG #x */
1620 #define P47_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #47 assigned IVG #x */
1622 /* SIC_IAR6 Macros */
1623 #define P48_IVG(x) (((x)-_MF7)&_MF15) /* Peripheral #48 assigned IVG #x */
1624 #define P49_IVG(x) (((x)-_MF7)&_MF15) << 0x4 /* Peripheral #49 assigned IVG #x */
1625 #define P50_IVG(x) (((x)-_MF7)&_MF15) << 0x8 /* Peripheral #50 assigned IVG #x */
1626 #define P51_IVG(x) (((x)-_MF7)&_MF15) << 0xC /* Peripheral #51 assigned IVG #x */
1627 #define P52_IVG(x) (((x)-_MF7)&_MF15) << 0x10 /* Peripheral #52 assigned IVG #x */
1628 #define P53_IVG(x) (((x)-_MF7)&_MF15) << 0x14 /* Peripheral #53 assigned IVG #x */
1629 #define P54_IVG(x) (((x)-_MF7)&_MF15) << 0x18 /* Peripheral #54 assigned IVG #x */
1630 #define P55_IVG(x) (((x)-_MF7)&_MF15) << 0x1C /* Peripheral #55 assigned IVG #x */
1632 /* SIC_IARx Macros */
1635 #define PX_IVG_CLR(x) (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
1636 /* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
1637 #define PX_IVG(x,y) ((((y)-7u)&0xFu) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
1638 /* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
1640 #define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
1641 /* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
1642 #define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
1643 /* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
1644 #endif /* _MISRA_RULES */
1646 /* SIC_IMASKx Masks */
1647 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1648 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1650 #define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
1651 #define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
1653 #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1654 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1655 #endif /* _MISRA_RULES */
1657 /* SIC_IWRx Masks */
1658 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1659 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1661 #define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
1662 #define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
1664 #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1665 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1666 #endif /* _MISRA_RULES */
1669 /* ********* WATCHDOG TIMER MASKS ******************** */
1670 /* Watchdog Timer WDOG_CTL Register Masks */
1672 #define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
1674 #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
1675 #endif /* _MISRA_RULES */
1676 #define WDEV_RESET 0x0000 /* generate reset event on roll over */
1677 #define WDEV_NMI 0x0002 /* generate NMI event on roll over */
1678 #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
1679 #define WDEV_NONE 0x0006 /* no event on roll over */
1680 #define WDEN 0x0FF0 /* enable watchdog */
1681 #define WDDIS 0x0AD0 /* disable watchdog */
1682 #define WDRO 0x8000 /* watchdog rolled over latch */
1684 /* deprecated WDOG_CTL Register Masks for legacy code */
1686 #define ENABLE_RESET WDEV_RESET
1687 #define WDOG_RESET WDEV_RESET
1688 #define ENABLE_NMI WDEV_NMI
1689 #define WDOG_NMI WDEV_NMI
1690 #define ENABLE_GPI WDEV_GPI
1691 #define WDOG_GPI WDEV_GPI
1692 #define DISABLE_EVT WDEV_NONE
1693 #define WDOG_NONE WDEV_NONE
1696 #define WDOG_DISABLE WDDIS
1699 #define ICTL_P0 0x01
1700 #define ICTL_P1 0x02
1704 /* *************** REAL TIME CLOCK MASKS **************************/
1705 /* RTC_STAT and RTC_ALARM register */
1706 #define RTSEC 0x0000003F /* Real-Time Clock Seconds */
1707 #define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
1708 #define RTHR 0x0001F000 /* Real-Time Clock Hours */
1709 #define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
1711 /* RTC_ICTL register */
1712 #define SWIE 0x0001 /* Stopwatch Interrupt Enable */
1713 #define AIE 0x0002 /* Alarm Interrupt Enable */
1714 #define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
1715 #define MIE 0x0008 /* Minutes Interrupt Enable */
1716 #define HIE 0x0010 /* Hours Interrupt Enable */
1717 #define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
1718 #define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1719 #define WCIE 0x8000 /* Write Complete Interrupt Enable */
1721 /* RTC_ISTAT register */
1722 #define SWEF 0x0001 /* Stopwatch Event Flag */
1723 #define AEF 0x0002 /* Alarm Event Flag */
1724 #define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
1725 #define MEF 0x0008 /* Minutes Event Flag */
1726 #define HEF 0x0010 /* Hours Event Flag */
1727 #define DEF 0x0020 /* 24 Hours (Days) Event Flag */
1728 #define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
1729 #define WPS 0x4000 /* Write Pending Status (RO) */
1730 #define WCOM 0x8000 /* Write Complete */
1732 /* RTC_FAST Mask (RTC_PREN Mask) */
1733 #define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
1734 #define PREN 0x00000001
1735 /* ** Must be set after power-up for proper operation of RTC */
1737 /* RTC_ALARM Macro z=day y=hr x=min w=sec */
1739 #define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
1741 #define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
1742 #endif /* _MISRA_RULES */
1744 /* Deprecated RTC_STAT and RTC_ALARM Masks */
1745 #define RTC_SEC RTSEC /* Real-Time Clock Seconds */
1746 #define RTC_MIN RTMIN /* Real-Time Clock Minutes */
1747 #define RTC_HR RTHR /* Real-Time Clock Hours */
1748 #define RTC_DAY RTDAY /* Real-Time Clock Days */
1750 /* Deprecated RTC_ICTL/RTC_ISTAT Masks */
1751 #define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
1752 #define ALARM AIE /* Alarm Interrupt Enable */
1753 #define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
1754 #define MINUTE MIE /* Minutes Interrupt Enable */
1755 #define HOUR HIE /* Hours Interrupt Enable */
1756 #define DAY DIE /* 24 Hours (Days) Interrupt Enable */
1757 #define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1758 #define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
1761 /* ***************************** UART CONTROLLER MASKS ********************** */
1762 /* UARTx_LCR Register */
1764 #define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
1766 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1767 #endif /* _MISRA_RULES */
1768 #define STB 0x04 /* Stop Bits */
1769 #define PEN 0x08 /* Parity Enable */
1770 #define EPS 0x10 /* Even Parity Select */
1771 #define STP 0x20 /* Stick Parity */
1772 #define SB 0x40 /* Set Break */
1773 #define DLAB 0x80 /* Divisor Latch Access */
1784 /* UARTx_MCR Register */
1785 #define LOOP_ENA 0x10 /* Loopback Mode Enable */
1786 #define LOOP_ENA_P 0x04
1787 /* Deprecated UARTx_MCR Mask */
1789 /* UARTx_LSR Register */
1790 #define DR 0x01 /* Data Ready */
1791 #define OE 0x02 /* Overrun Error */
1792 #define PE 0x04 /* Parity Error */
1793 #define FE 0x08 /* Framing Error */
1794 #define BI 0x10 /* Break Interrupt */
1795 #define THRE 0x20 /* THR Empty */
1796 #define TEMT 0x40 /* TSR and UART_THR Empty */
1806 /* UARTx_IER Register */
1807 #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1808 #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1809 #define ELSI 0x04 /* Enable RX Status Interrupt */
1812 #define ETBEI_P 0x01
1813 #define ERBFI_P 0x00
1815 /* UARTx_IIR Register */
1817 #define STATUS(x) (((x) << 1) & 0x06u)
1819 #define STATUS(x) (((x) << 1) & 0x06)
1820 #endif /* _MISRA_RULES */
1822 #define STATUS_P1 0x02
1823 #define STATUS_P0 0x01
1826 /* UARTx_GCTL Register */
1827 #define UCEN 0x01 /* Enable UARTx Clocks */
1828 #define IREN 0x02 /* Enable IrDA Mode */
1829 #define TPOLC 0x04 /* IrDA TX Polarity Change */
1830 #define RPOLC 0x08 /* IrDA RX Polarity Change */
1831 #define FPE 0x10 /* Force Parity Error On Transmit */
1832 #define FFE 0x20 /* Force Framing Error On Transmit */
1836 #define RPOLC_P 0x03
1837 #define TPOLC_P 0x02
1842 /* ********** SERIAL PORT MASKS ********************** */
1843 /* SPORTx_TCR1 Masks */
1844 #define TSPEN 0x0001 /* TX enable */
1845 #define ITCLK 0x0002 /* Internal TX Clock Select */
1846 #define TDTYPE 0x000C /* TX Data Formatting Select */
1847 #define DTYPE_NORM 0x0000 /* Data Format Normal */
1848 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1849 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1850 #define TLSBIT 0x0010 /* TX Bit Order */
1851 #define ITFS 0x0200 /* Internal TX Frame Sync Select */
1852 #define TFSR 0x0400 /* TX Frame Sync Required Select */
1853 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1854 #define LTFS 0x1000 /* Low TX Frame Sync Select */
1855 #define LATFS 0x2000 /* Late TX Frame Sync Select */
1856 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1857 /* SPORTx_RCR1 Deprecated Masks */
1858 #define TULAW DTYPE_ULAW /* Compand Using u-Law */
1859 #define TALAW DTYPE_ALAW /* Compand Using A-Law */
1861 /* SPORTx_TCR2 Masks */
1863 #define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
1865 #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1866 #endif /* _MISRA_RULES */
1867 #define TXSE 0x0100 /*TX Secondary Enable */
1868 #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
1869 #define TRFST 0x0400 /*TX Right-First Data Order */
1871 /* SPORTx_RCR1 Masks */
1872 #define RSPEN 0x0001 /* RX enable */
1873 #define IRCLK 0x0002 /* Internal RX Clock Select */
1874 #define RDTYPE 0x000C /* RX Data Formatting Select */
1875 #define DTYPE_NORM 0x0000 /* no companding */
1876 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1877 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1878 #define RLSBIT 0x0010 /* RX Bit Order */
1879 #define IRFS 0x0200 /* Internal RX Frame Sync Select */
1880 #define RFSR 0x0400 /* RX Frame Sync Required Select */
1881 #define LRFS 0x1000 /* Low RX Frame Sync Select */
1882 #define LARFS 0x2000 /* Late RX Frame Sync Select */
1883 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1884 /* SPORTx_RCR1 Deprecated Masks */
1885 #define RULAW DTYPE_ULAW /* Compand Using u-Law */
1886 #define RALAW DTYPE_ALAW /* Compand Using A-Law */
1888 /* SPORTx_RCR2 Masks */
1890 #define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
1892 #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1893 #endif /* _MISRA_RULES */
1894 #define RXSE 0x0100 /*RX Secondary Enable */
1895 #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
1896 #define RRFST 0x0400 /*Right-First Data Order */
1898 /*SPORTx_STAT Masks */
1899 #define RXNE 0x0001 /*RX FIFO Not Empty Status */
1900 #define RUVF 0x0002 /*RX Underflow Status */
1901 #define ROVF 0x0004 /*RX Overflow Status */
1902 #define TXF 0x0008 /*TX FIFO Full Status */
1903 #define TUVF 0x0010 /*TX Underflow Status */
1904 #define TOVF 0x0020 /*TX Overflow Status */
1905 #define TXHRE 0x0040 /*TX Hold Register Empty */
1907 /*SPORTx_MCMC1 Masks */
1908 #define WSIZE 0x0000F000 /*Multichannel Window Size Field */
1909 #define WOFF 0x000003FF /*Multichannel Window Offset Field */
1910 /* SPORTx_MCMC1 Macros */
1912 #define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
1913 /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1914 #define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1916 #define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1917 /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
1918 #define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1919 #endif /* _MISRA_RULES */
1922 /*SPORTx_MCMC2 Masks */
1923 #define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
1924 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1925 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1926 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1927 #define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
1928 #define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
1929 #define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
1930 #define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
1931 #define MFD 0xF000 /*Multichannel Frame Delay */
1932 #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1933 #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1934 #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1935 #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1936 #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1937 #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1938 #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1939 #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1940 #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1941 #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1942 #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1943 #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1944 #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1945 #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1946 #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1947 #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1950 /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1951 /* PPI_CONTROL Masks */
1952 #define PORT_EN 0x0001 /* PPI Port Enable */
1953 #define PORT_DIR 0x0002 /* PPI Port Direction */
1954 #define XFR_TYPE 0x000C /* PPI Transfer Type */
1955 #define PORT_CFG 0x0030 /* PPI Port Configuration */
1956 #define FLD_SEL 0x0040 /* PPI Active Field Select */
1957 #define PACK_EN 0x0080 /* PPI Packing Mode */
1958 /* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1959 #define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1960 #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1961 #define DLENGTH 0x3800 /* PPI Data Length */
1962 #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1963 #define DLEN_10 0x0800 /* Data Length = 10 Bits */
1964 #define DLEN_11 0x1000 /* Data Length = 11 Bits */
1965 #define DLEN_12 0x1800 /* Data Length = 12 Bits */
1966 #define DLEN_13 0x2000 /* Data Length = 13 Bits */
1967 #define DLEN_14 0x2800 /* Data Length = 14 Bits */
1968 #define DLEN_15 0x3000 /* Data Length = 15 Bits */
1969 #define DLEN_16 0x3800 /* Data Length = 16 Bits */
1971 #define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1973 #define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1974 #endif /* _MISRA_RULES */
1975 #define POL 0xC000 /* PPI Signal Polarities */
1976 #define POLC 0x4000 /* PPI Clock Polarity */
1977 #define POLS 0x8000 /* PPI Frame Sync Polarity */
1980 /* PPI_STATUS Masks */
1981 #define FLD 0x0400 /* Field Indicator */
1982 #define FT_ERR 0x0800 /* Frame Track Error */
1983 #define OVR 0x1000 /* FIFO Overflow Error */
1984 #define UNDR 0x2000 /* FIFO Underrun Error */
1985 #define ERR_DET 0x4000 /* Error Detected Indicator */
1986 #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1989 /* ********** DMA CONTROLLER MASKS ***********************/
1990 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1991 #define DMAEN 0x0001 /* Channel Enable */
1992 #define WNR 0x0002 /* Channel Direction (W/R*) */
1993 #define WDSIZE_8 0x0000 /* Word Size 8 bits */
1994 #define WDSIZE_16 0x0004 /* Word Size 16 bits */
1995 #define WDSIZE_32 0x0008 /* Word Size 32 bits */
1996 #define DMA2D 0x0010 /* 2D/1D* Mode */
1997 #define RESTART 0x0020 /* Restart */
1998 #define DI_SEL 0x0040 /* Data Interrupt Select */
1999 #define DI_EN 0x0080 /* Data Interrupt Enable */
2000 #define NDSIZE 0x0900 /* Next Descriptor Size */
2001 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
2002 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
2003 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
2004 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
2005 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
2006 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
2007 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
2008 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
2009 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
2010 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
2011 #define FLOW 0x7000 /* Flow Control */
2012 #define FLOW_STOP 0x0000 /* Stop Mode */
2013 #define FLOW_AUTO 0x1000 /* Autobuffer Mode */
2014 #define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
2015 #define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
2016 #define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
2018 #define DMAEN_P 0x0 /* Channel Enable */
2019 #define WNR_P 0x1 /* Channel Direction (W/R*) */
2020 #define DMA2D_P 0x4 /* 2D/1D* Mode */
2021 #define RESTART_P 0x5 /* Restart */
2022 #define DI_SEL_P 0x6 /* Data Interrupt Select */
2023 #define DI_EN_P 0x7 /* Data Interrupt Enable */
2025 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
2026 #define DMA_DONE 0x0001 /* DMA Done Indicator */
2027 #define DMA_ERR 0x0002 /* DMA Error Indicator */
2028 #define DFETCH 0x0004 /* Descriptor Fetch Indicator */
2029 #define DMA_RUN 0x0008 /* DMA Running Indicator */
2031 #define DMA_DONE_P 0x0 /* DMA Done Indicator */
2032 #define DMA_ERR_P 0x1 /* DMA Error Indicator */
2033 #define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
2034 #define DMA_RUN_P 0x3 /* DMA Running Indicator */
2036 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
2038 #define CTYPE 0x0040 /* DMA Channel Type Indicator */
2039 #define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
2040 #define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
2041 #define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
2042 #define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
2043 #define PCAPWR 0x0400 /* DMA Write Operation Indicator */
2044 #define PCAPRD 0x0800 /* DMA Read Operation Indicator */
2045 #define PMAP 0xF000 /* DMA Peripheral Map Field */
2047 /* PMAP Encodings For DMA Controller 0 */
2048 #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
2049 #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
2050 #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
2051 #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
2052 #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
2053 #define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
2054 #define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
2055 #define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
2057 /* PMAP Encodings For DMA Controller 1 */
2058 #define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
2059 #define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
2060 #define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
2061 #define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
2062 #define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
2063 #define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
2064 #define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
2065 #define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
2066 #define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
2067 #define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
2070 /* ************* GENERAL PURPOSE TIMER MASKS ******************** */
2071 /* PWM Timer bit definitions */
2072 /* TIMER_ENABLE Register */
2073 #define TIMEN0 0x0001 /* Enable Timer 0 */
2074 #define TIMEN1 0x0002 /* Enable Timer 1 */
2075 #define TIMEN2 0x0004 /* Enable Timer 2 */
2077 #define TIMEN0_P 0x00
2078 #define TIMEN1_P 0x01
2079 #define TIMEN2_P 0x02
2081 /* TIMER_DISABLE Register */
2082 #define TIMDIS0 0x0001 /* Disable Timer 0 */
2083 #define TIMDIS1 0x0002 /* Disable Timer 1 */
2084 #define TIMDIS2 0x0004 /* Disable Timer 2 */
2086 #define TIMDIS0_P 0x00
2087 #define TIMDIS1_P 0x01
2088 #define TIMDIS2_P 0x02
2090 /* TIMER_STATUS Register */
2091 #define TIMIL0 0x0001 /* Timer 0 Interrupt */
2092 #define TIMIL1 0x0002 /* Timer 1 Interrupt */
2093 #define TIMIL2 0x0004 /* Timer 2 Interrupt */
2094 #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
2095 #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
2096 #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
2097 #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2098 #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2099 #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2101 #define TIMIL0_P 0x00
2102 #define TIMIL1_P 0x01
2103 #define TIMIL2_P 0x02
2104 #define TOVF_ERR0_P 0x04
2105 #define TOVF_ERR1_P 0x05
2106 #define TOVF_ERR2_P 0x06
2107 #define TRUN0_P 0x0C
2108 #define TRUN1_P 0x0D
2109 #define TRUN2_P 0x0E
2111 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2112 #define TOVL_ERR0 TOVF_ERR0
2113 #define TOVL_ERR1 TOVF_ERR1
2114 #define TOVL_ERR2 TOVF_ERR2
2115 #define TOVL_ERR0_P TOVF_ERR0_P
2116 #define TOVL_ERR1_P TOVF_ERR1_P
2117 #define TOVL_ERR2_P TOVF_ERR2_P
2119 /* TIMERx_CONFIG Registers */
2120 #define PWM_OUT 0x0001
2121 #define WDTH_CAP 0x0002
2122 #define EXT_CLK 0x0003
2123 #define PULSE_HI 0x0004
2124 #define PERIOD_CNT 0x0008
2125 #define IRQ_ENA 0x0010
2126 #define TIN_SEL 0x0020
2127 #define OUT_DIS 0x0040
2128 #define CLK_SEL 0x0080
2129 #define TOGGLE_HI 0x0100
2130 #define EMU_RUN 0x0200
2132 #define ERR_TYP(x) (((x) & 0x03u) << 14)
2134 #define ERR_TYP(x) (((x) & 0x03) << 14)
2135 #endif /* _MISRA_RULES */
2137 #define TMODE_P0 0x00
2138 #define TMODE_P1 0x01
2139 #define PULSE_HI_P 0x02
2140 #define PERIOD_CNT_P 0x03
2141 #define IRQ_ENA_P 0x04
2142 #define TIN_SEL_P 0x05
2143 #define OUT_DIS_P 0x06
2144 #define CLK_SEL_P 0x07
2145 #define TOGGLE_HI_P 0x08
2146 #define EMU_RUN_P 0x09
2147 #define ERR_TYP_P0 0x0E
2148 #define ERR_TYP_P1 0x0F
2151 /*/ ****************** GENERAL-PURPOSE I/O ********************* */
2152 /* Flag I/O (FIO_) Masks */
2170 /* PORT F BIT POSITIONS */
2189 /******************* GPIO MASKS *********************/
2199 /* Port C Bit Positions */
2226 /* Port D Bit Positions */
2261 /* Port E Bit Positions */
2280 /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
2281 /* SPIx_CTL Masks */
2282 #define TIMOD 0x0003 /* Transfer Initiate Mode */
2283 #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
2284 #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
2285 #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
2286 #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
2287 #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
2288 #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
2289 #define PSSE 0x0010 /* Slave-Select Input Enable */
2290 #define EMISO 0x0020 /* Enable MISO As Output */
2291 #define SIZE 0x0100 /* Size of Words (16/8* Bits) */
2292 #define LSBF 0x0200 /* LSB First */
2293 #define CPHA 0x0400 /* Clock Phase */
2294 #define CPOL 0x0800 /* Clock Polarity */
2295 #define MSTR 0x1000 /* Master/Slave* */
2296 #define WOM 0x2000 /* Write Open Drain Master */
2297 #define SPE 0x4000 /* SPI Enable */
2299 /* SPIx_FLG Masks */
2300 #define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
2301 #define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
2302 #define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
2303 #define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
2304 #define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
2305 #define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
2306 #define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
2308 #define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
2309 #define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
2310 #define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
2311 #define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
2312 #define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
2313 #define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
2314 #define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
2316 /* SPIx_FLG Bit Positions */
2317 #define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
2318 #define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
2319 #define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
2320 #define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
2321 #define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
2322 #define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
2323 #define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
2324 #define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
2325 #define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
2326 #define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
2327 #define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
2328 #define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
2329 #define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
2330 #define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
2332 /* SPIx_STAT Masks */
2333 #define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
2334 #define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
2335 #define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
2336 #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
2337 #define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
2338 #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
2339 #define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
2341 /* SPIx_FLG Masks */
2342 #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
2343 #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
2344 #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
2345 #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
2346 #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
2347 #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
2348 #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
2351 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
2352 /* EBIU_AMGCTL Masks */
2353 #define AMCKEN 0x0001 /* Enable CLKOUT */
2354 #define AMBEN_NONE 0x0000 /* All Banks Disabled */
2355 #define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
2356 #define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
2357 #define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
2358 #define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
2359 #define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
2361 /* EBIU_AMGCTL Bit Positions */
2362 #define AMCKEN_P 0x0000 /* Enable CLKOUT */
2363 #define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
2364 #define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
2365 #define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
2367 /* EBIU_AMBCTL0 Masks */
2368 #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
2369 #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
2370 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
2371 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
2372 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
2373 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
2374 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
2375 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
2376 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
2377 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
2378 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
2379 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
2380 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
2381 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
2382 #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
2383 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
2384 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
2385 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
2386 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
2387 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
2388 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
2389 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
2390 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
2391 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
2392 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
2393 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
2394 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
2395 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
2396 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
2397 #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
2398 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
2399 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
2400 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
2401 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
2402 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
2403 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
2404 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
2405 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
2406 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
2407 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
2408 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
2409 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
2410 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
2411 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
2412 #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
2413 #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
2414 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
2415 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
2416 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
2417 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
2418 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
2419 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
2420 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
2421 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
2422 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
2423 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
2424 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
2425 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
2426 #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
2427 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
2428 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
2429 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
2430 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
2431 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
2432 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
2433 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
2434 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
2435 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
2436 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
2437 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
2438 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
2439 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
2440 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
2441 #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
2442 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
2443 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
2444 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
2445 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
2446 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
2447 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
2448 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
2449 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
2450 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
2451 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
2452 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
2453 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
2454 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
2455 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
2457 /* EBIU_AMBCTL1 Masks */
2458 #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
2459 #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
2460 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
2461 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
2462 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
2463 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
2464 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
2465 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
2466 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
2467 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
2468 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
2469 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
2470 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
2471 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
2472 #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
2473 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
2474 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
2475 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
2476 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
2477 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
2478 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
2479 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
2480 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
2481 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
2482 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
2483 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
2484 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
2485 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
2486 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
2487 #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
2488 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
2489 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
2490 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
2491 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
2492 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
2493 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
2494 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
2495 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
2496 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
2497 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
2498 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
2499 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
2500 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
2501 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
2502 #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
2503 #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
2504 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
2505 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
2506 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
2507 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
2508 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
2509 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
2510 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
2511 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
2512 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
2513 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
2514 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
2515 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
2516 #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
2517 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
2518 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
2519 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
2520 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
2521 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
2522 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
2523 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
2524 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
2525 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
2526 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
2527 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
2528 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
2529 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
2530 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
2531 #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
2532 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
2533 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
2534 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
2535 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
2536 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
2537 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
2538 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
2539 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
2540 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
2541 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
2542 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
2543 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
2544 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
2545 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
2547 /* ********************** SDRAM CONTROLLER MASKS *************************** */
2548 /* EBIU_SDGCTL Masks */
2549 #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
2550 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
2551 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
2552 #define PFE 0x00000010 /* Enable SDRAM prefetch */
2553 #define PFP 0x00000020 /* Prefetch has priority over AMC requests */
2554 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
2555 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
2556 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
2557 #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
2558 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
2559 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
2560 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
2561 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
2562 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
2563 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
2564 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
2565 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
2566 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
2567 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
2568 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
2569 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
2570 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
2571 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
2572 #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
2573 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
2574 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
2575 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
2576 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
2577 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
2578 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
2579 #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
2580 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
2581 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
2582 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
2583 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
2584 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
2585 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
2586 #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
2587 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
2588 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
2589 #define PUPSD 0x00200000 /*Power-up start delay */
2590 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
2591 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
2592 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
2593 #define EBUFE 0x02000000 /* Enable external buffering timing */
2594 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
2595 #define EMREN 0x10000000 /* Extended mode register enable */
2596 #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
2597 #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
2599 /* EBIU_SDBCTL Masks */
2600 #define EBE 0x0001 /* Enable SDRAM external bank */
2601 #define EBSZ_16 0x0000 /* SDRAM external bank size = 16MB */
2602 #define EBSZ_32 0x0002 /* SDRAM external bank size = 32MB */
2603 #define EBSZ_64 0x0004 /* SDRAM external bank size = 64MB */
2604 #define EBSZ_128 0x0006 /* SDRAM external bank size = 128MB */
2605 #define EBSZ 0x0006 /* SDRAM external bank size */
2606 #define EBCAW_8 0x0000 /* SDRAM external bank column address width = 8 bits */
2607 #define EBCAW_9 0x0010 /* SDRAM external bank column address width = 9 bits */
2608 #define EBCAW_10 0x0020 /* SDRAM external bank column address width = 9 bits */
2609 #define EBCAW_11 0x0030 /* SDRAM external bank column address width = 9 bits */
2611 /* EBIU_SDSTAT Masks */
2612 #define SDCI 0x00000001 /* SDRAM controller is idle */
2613 #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
2614 #define SDPUA 0x00000004 /* SDRAM power up active */
2615 #define SDRS 0x00000008 /* SDRAM is in reset state */
2616 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
2617 #define BGSTAT 0x00000020 /* Bus granted */
2620 /* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
2621 /* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
2623 #define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
2624 #define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
2626 #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
2627 #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
2628 #endif /* _MISRA_RULES */
2630 /* TWIx_PRESCALE Masks */
2631 #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
2632 #define TWI_ENA 0x0080 /* TWI Enable */
2633 #define SCCB 0x0200 /* SCCB Compatibility Enable */
2635 /* TWIx_SLAVE_CTRL Masks */
2636 #define SEN 0x0001 /* Slave Enable */
2637 #define SADD_LEN 0x0002 /* Slave Address Length */
2638 #define STDVAL 0x0004 /* Slave Transmit Data Valid */
2639 #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
2640 #define GEN 0x0010 /* General Call Adrress Matching Enabled */
2642 /* TWIx_SLAVE_STAT Masks */
2643 #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
2644 #define GCALL 0x0002 /* General Call Indicator */
2646 /* TWIx_MASTER_CTRL Masks */
2647 #define MEN 0x0001 /* Master Mode Enable */
2648 #define MADD_LEN 0x0002 /* Master Address Length */
2649 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
2650 #define FAST 0x0008 /* Use Fast Mode Timing Specs */
2651 #define STOP 0x0010 /* Issue Stop Condition */
2652 #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
2653 #define DCNT 0x3FC0 /* Data Bytes To Transfer */
2654 #define SDAOVR 0x4000 /* Serial Data Override */
2655 #define SCLOVR 0x8000 /* Serial Clock Override */
2657 /* TWIx_MASTER_STAT Masks */
2658 #define MPROG 0x0001 /* Master Transfer In Progress */
2659 #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
2660 #define ANAK 0x0004 /* Address Not Acknowledged */
2661 #define DNAK 0x0008 /* Data Not Acknowledged */
2662 #define BUFRDERR 0x0010 /* Buffer Read Error */
2663 #define BUFWRERR 0x0020 /* Buffer Write Error */
2664 #define SDASEN 0x0040 /* Serial Data Sense */
2665 #define SCLSEN 0x0080 /* Serial Clock Sense */
2666 #define BUSBUSY 0x0100 /* Bus Busy Indicator */
2668 /* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
2669 #define SINIT 0x0001 /* Slave Transfer Initiated */
2670 #define SCOMP 0x0002 /* Slave Transfer Complete */
2671 #define SERR 0x0004 /* Slave Transfer Error */
2672 #define SOVF 0x0008 /* Slave Overflow */
2673 #define MCOMP 0x0010 /* Master Transfer Complete */
2674 #define MERR 0x0020 /* Master Transfer Error */
2675 #define XMTSERV 0x0040 /* Transmit FIFO Service */
2676 #define RCVSERV 0x0080 /* Receive FIFO Service */
2678 /* TWIx_FIFO_CTRL Masks */
2679 #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
2680 #define RCVFLUSH 0x0002 /* Receive Buffer Flush */
2681 #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
2682 #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
2684 /* TWIx_FIFO_STAT Masks */
2685 #define XMTSTAT 0x0003 /* Transmit FIFO Status */
2686 #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
2687 #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
2688 #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
2690 #define RCVSTAT 0x000C /* Receive FIFO Status */
2691 #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
2692 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
2693 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2696 /********************************* MXVR MASKS ****************************************/
2698 /* MXVR_CONFIG Masks */
2700 #define MXVREN 0x00000001lu
2701 #define MMSM 0x00000002lu
2702 #define ACTIVE 0x00000004lu
2703 #define SDELAY 0x00000008lu
2704 #define NCMRXEN 0x00000010lu
2705 #define RWRRXEN 0x00000020lu
2706 #define MTXEN 0x00000040lu
2707 #define MTXON 0x00000080lu /*legacy*/
2708 #define MTXONB 0x00000080lu
2709 #define EPARITY 0x00000100lu
2710 #define MSB 0x00001E00lu
2711 #define APRXEN 0x00002000lu
2712 #define WAKEUP 0x00004000lu
2713 #define LMECH 0x00008000lu
2716 #define SET_MSB(x) (((x)&0xFu) << 0x9)
2718 #define SET_MSB(x) (((x)&0xF) << 0x9)
2719 #endif /* _MISRA_RULES */
2722 /* MXVR_PLL_CTL_0 Masks */
2724 #define MXTALCEN 0x00000001lu
2725 #define MXTALFEN 0x00000002lu
2726 #define MPLLMS 0x00000008lu
2727 #define MXTALMUL 0x00000030lu
2728 #define MPLLEN 0x00000040lu
2729 #define MPLLEN0 0x00000040lu /* legacy */
2730 #define MPLLEN1 0x00000080lu /* legacy */
2731 #define MMCLKEN 0x00000100lu
2732 #define MMCLKMUL 0x00001E00lu
2733 #define MPLLRSTB 0x00002000lu
2734 #define MPLLRSTB0 0x00002000lu /* legacy */
2735 #define MPLLRSTB1 0x00004000lu /* legacy */
2736 #define MBCLKEN 0x00010000lu
2737 #define MBCLKDIV 0x001E0000lu
2738 #define MPLLCDR 0x00200000lu
2739 #define MPLLCDR0 0x00200000lu /* legacy */
2740 #define MPLLCDR1 0x00400000lu /* legacy */
2741 #define INVRX 0x00800000lu
2742 #define MFSEN 0x01000000lu
2743 #define MFSDIV 0x1E000000lu
2744 #define MFSSEL 0x60000000lu
2745 #define MFSSYNC 0x80000000lu
2747 #define MXTALMUL_256FS 0x00000000lu /* legacy */
2748 #define MXTALMUL_384FS 0x00000010lu /* legacy */
2749 #define MXTALMUL_512FS 0x00000020lu /* legacy */
2750 #define MXTALMUL_1024FS 0x00000030lu
2752 #define MMCLKMUL_1024FS 0x00000000lu
2753 #define MMCLKMUL_512FS 0x00000200lu
2754 #define MMCLKMUL_256FS 0x00000400lu
2755 #define MMCLKMUL_128FS 0x00000600lu
2756 #define MMCLKMUL_64FS 0x00000800lu
2757 #define MMCLKMUL_32FS 0x00000A00lu
2758 #define MMCLKMUL_16FS 0x00000C00lu
2759 #define MMCLKMUL_8FS 0x00000E00lu
2760 #define MMCLKMUL_4FS 0x00001000lu
2761 #define MMCLKMUL_2FS 0x00001200lu
2762 #define MMCLKMUL_1FS 0x00001400lu
2763 #define MMCLKMUL_1536FS 0x00001A00lu
2764 #define MMCLKMUL_768FS 0x00001C00lu
2765 #define MMCLKMUL_384FS 0x00001E00lu
2767 #define MBCLKDIV_DIV2 0x00020000lu
2768 #define MBCLKDIV_DIV4 0x00040000lu
2769 #define MBCLKDIV_DIV8 0x00060000lu
2770 #define MBCLKDIV_DIV16 0x00080000lu
2771 #define MBCLKDIV_DIV32 0x000A0000lu
2772 #define MBCLKDIV_DIV64 0x000C0000lu
2773 #define MBCLKDIV_DIV128 0x000E0000lu
2774 #define MBCLKDIV_DIV256 0x00100000lu
2775 #define MBCLKDIV_DIV512 0x00120000lu
2776 #define MBCLKDIV_DIV1024 0x00140000lu
2778 #define MFSDIV_DIV2 0x02000000lu
2779 #define MFSDIV_DIV4 0x04000000lu
2780 #define MFSDIV_DIV8 0x06000000lu
2781 #define MFSDIV_DIV16 0x08000000lu
2782 #define MFSDIV_DIV32 0x0A000000lu
2783 #define MFSDIV_DIV64 0x0C000000lu
2784 #define MFSDIV_DIV128 0x0E000000lu
2785 #define MFSDIV_DIV256 0x10000000lu
2786 #define MFSDIV_DIV512 0x12000000lu
2787 #define MFSDIV_DIV1024 0x14000000lu
2789 #define MFSSEL_CLOCK 0x00000000lu
2790 #define MFSSEL_PULSE_HI 0x20000000lu
2791 #define MFSSEL_PULSE_LO 0x40000000lu
2794 /* MXVR_PLL_CTL_1 Masks */
2796 #define MSTO 0x00000001lu
2797 #define MSTO0 0x00000001lu /* legacy */
2798 #define MHOGGD 0x00000004lu
2799 #define MHOGGD0 0x00000004lu /* legacy */
2800 #define MHOGGD1 0x00000008lu /* legacy */
2801 #define MSHAPEREN 0x00000010lu
2802 #define MSHAPEREN0 0x00000010lu /* legacy */
2803 #define MSHAPEREN1 0x00000020lu /* legacy */
2804 #define MPLLCNTEN 0x00008000lu
2805 #define MPLLCNT 0xFFFF0000lu
2808 #define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10)
2810 #define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
2811 #endif /* _MISRA_RULES */
2814 /* MXVR_PLL_CTL_2 Masks */
2816 #define MSHAPERSEL 0x00000007lu
2817 #define MCPSEL 0x000000E0lu
2820 #define SET_MSHAPERSEL(x) ( (x) & 0x0007u )
2821 #define SET_MCPSEL(x) ( ( (x) & 0x0007u ) << 0x5 )
2823 #define SET_MSHAPERSEL(x) ( (x) & 0x0007 )
2824 #define SET_MCPSEL(x) ( ( (x) & 0x0007 ) << 0x5 )
2825 #endif /* _MISRA_RULES */
2828 /* MXVR_INT_STAT_0 Masks */
2830 #define NI2A 0x00000001lu
2831 #define NA2I 0x00000002lu
2832 #define SBU2L 0x00000004lu
2833 #define SBL2U 0x00000008lu
2834 #define PRU 0x00000010lu
2835 #define MPRU 0x00000020lu
2836 #define DRU 0x00000040lu
2837 #define MDRU 0x00000080lu
2838 #define SBU 0x00000100lu
2839 #define ATU 0x00000200lu
2840 #define FCZ0 0x00000400lu
2841 #define FCZ1 0x00000800lu
2842 #define PERR 0x00001000lu
2843 #define MH2L 0x00002000lu
2844 #define ML2H 0x00004000lu
2845 #define WUP 0x00008000lu
2846 #define FU2L 0x00010000lu
2847 #define FL2U 0x00020000lu
2848 #define BU2L 0x00040000lu
2849 #define BL2U 0x00080000lu
2850 #define PCZ 0x00400000lu
2851 #define FERR 0x00800000lu
2852 #define CMR 0x01000000lu
2853 #define CMROF 0x02000000lu
2854 #define CMTS 0x04000000lu
2855 #define CMTC 0x08000000lu
2856 #define RWRC 0x10000000lu
2857 #define BCZ 0x20000000lu
2858 #define BMERR 0x40000000lu
2859 #define DERR 0x80000000lu
2862 /* MXVR_INT_EN_0 Masks */
2866 #define SBU2LEN SBU2L
2867 #define SBL2UEN SBL2U
2887 #define CMROFEN CMROF
2892 #define BMERREN BMERR
2896 /* MXVR_INT_STAT_1 Masks */
2898 #define APR 0x00000004lu
2899 #define APROF 0x00000008lu
2900 #define APTS 0x00000040lu
2901 #define APTC 0x00000080lu
2902 #define APRCE 0x00000400lu
2903 #define APRPE 0x00000800lu
2905 #define HDONE0 0x00000001lu
2906 #define DONE0 0x00000002lu
2907 #define HDONE1 0x00000010lu
2908 #define DONE1 0x00000020lu
2909 #define HDONE2 0x00000100lu
2910 #define DONE2 0x00000200lu
2911 #define HDONE3 0x00001000lu
2912 #define DONE3 0x00002000lu
2913 #define HDONE4 0x00010000lu
2914 #define DONE4 0x00020000lu
2915 #define HDONE5 0x00100000lu
2916 #define DONE5 0x00200000lu
2917 #define HDONE6 0x01000000lu
2918 #define DONE6 0x02000000lu
2919 #define HDONE7 0x10000000lu
2920 #define DONE7 0x20000000lu
2922 #define DONEX(x) (0x00000002 << (4 * (x)))
2923 #define HDONEX(x) (0x00000001 << (4 * (x)))
2926 /* MXVR_INT_EN_1 Masks */
2929 #define APROFEN APROF
2932 #define APRCEEN APRCE
2933 #define APRPEEN APRPE
2935 #define HDONEEN0 HDONE0
2936 #define DONEEN0 DONE0
2937 #define HDONEEN1 HDONE1
2938 #define DONEEN1 DONE1
2939 #define HDONEEN2 HDONE2
2940 #define DONEEN2 DONE2
2941 #define HDONEEN3 HDONE3
2942 #define DONEEN3 DONE3
2943 #define HDONEEN4 HDONE4
2944 #define DONEEN4 DONE4
2945 #define HDONEEN5 HDONE5
2946 #define DONEEN5 DONE5
2947 #define HDONEEN6 HDONE6
2948 #define DONEEN6 DONE6
2949 #define HDONEEN7 HDONE7
2950 #define DONEEN7 DONE7
2952 #define DONEENX(x) (0x00000002 << (4 * (x)))
2953 #define HDONEENX(x) (0x00000001 << (4 * (x)))
2956 /* MXVR_STATE_0 Masks */
2958 #define NACT 0x00000001lu
2959 #define SBLOCK 0x00000002lu
2960 #define PFDLOCK 0x00000004lu
2961 #define PFDLOCK0 0x00000004lu /* legacy */
2962 #define PDD 0x00000008lu
2963 #define PDD0 0x00000008lu /* legacy */
2964 #define PVCO 0x00000010lu
2965 #define PVCO0 0x00000010lu /* legacy */
2966 #define PFDLOCK1 0x00000020lu /* legacy */
2967 #define PDD1 0x00000040lu /* legacy */
2968 #define PVCO1 0x00000080lu /* legacy */
2969 #define APBSY 0x00000100lu
2970 #define APARB 0x00000200lu
2971 #define APTX 0x00000400lu
2972 #define APRX 0x00000800lu
2973 #define CMBSY 0x00001000lu
2974 #define CMARB 0x00002000lu
2975 #define CMTX 0x00004000lu
2976 #define CMRX 0x00008000lu
2977 #define MRXONB 0x00010000lu
2978 #define RGSIP 0x00020000lu
2979 #define DALIP 0x00040000lu
2980 #define ALIP 0x00080000lu
2981 #define RRDIP 0x00100000lu
2982 #define RWRIP 0x00200000lu
2983 #define FLOCK 0x00400000lu
2984 #define BLOCK 0x00800000lu
2985 #define RSB 0x0F000000lu
2986 #define DERRNUM 0xF0000000lu
2989 /* MXVR_STATE_1 Masks */
2991 #define STXNUMB 0x0000000Flu
2992 #define SRXNUMB 0x000000F0lu
2993 #define APCONT 0x00000100lu
2994 #define DMAACTIVEX 0x00FF0000lu
2995 #define DMAACTIVE0 0x00010000lu
2996 #define DMAACTIVE1 0x00020000lu
2997 #define DMAACTIVE2 0x00040000lu
2998 #define DMAACTIVE3 0x00080000lu
2999 #define DMAACTIVE4 0x00100000lu
3000 #define DMAACTIVE5 0x00200000lu
3001 #define DMAACTIVE6 0x00400000lu
3002 #define DMAACTIVE7 0x00800000lu
3003 #define DMAPMENX 0xFF000000lu
3004 #define DMAPMEN0 0x01000000lu
3005 #define DMAPMEN1 0x02000000lu
3006 #define DMAPMEN2 0x04000000lu
3007 #define DMAPMEN3 0x08000000lu
3008 #define DMAPMEN4 0x10000000lu
3009 #define DMAPMEN5 0x20000000lu
3010 #define DMAPMEN6 0x40000000lu
3011 #define DMAPMEN7 0x80000000lu
3014 /* MXVR_POSITION Masks */
3016 #define PVALID 0x8000
3017 #define POSITION 0x003F
3020 /* MXVR_MAX_POSITION Masks */
3022 #define MPVALID 0x8000
3023 #define MPOSITION 0x003F
3026 /* MXVR_DELAY Masks */
3028 #define DVALID 0x8000
3029 #define DELAY 0x003F
3032 /* MXVR_MAX_DELAY Masks */
3034 #define MDVALID 0x8000
3035 #define MDELAY 0x003F
3038 /* MXVR_LADDR Masks */
3040 #define LVALID 0x80000000lu
3041 #define LADDR 0x0000FFFFlu
3044 /* MXVR_GADDR Masks */
3046 #define GVALID 0x8000
3047 #define GADDRL 0x00FF
3050 /* MXVR_AADDR Masks */
3052 #define AVALID 0x80000000lu
3053 #define AADDR 0x0000FFFFlu
3056 /* MXVR_ALLOC_0 Masks */
3058 #define CIU0 0x00000080lu
3059 #define CIU1 0x00008000lu
3060 #define CIU2 0x00800000lu
3061 #define CIU3 0x80000000lu
3063 #define CL0 0x0000007Flu
3064 #define CL1 0x00007F00lu
3065 #define CL2 0x007F0000lu
3066 #define CL3 0x7F000000lu
3069 /* MXVR_ALLOC_1 Masks */
3071 #define CIU4 0x00000080lu
3072 #define CIU5 0x00008000lu
3073 #define CIU6 0x00800000lu
3074 #define CIU7 0x80000000lu
3076 #define CL4 0x0000007Flu
3077 #define CL5 0x00007F00lu
3078 #define CL6 0x007F0000lu
3079 #define CL7 0x7F000000lu
3082 /* MXVR_ALLOC_2 Masks */
3084 #define CIU8 0x00000080lu
3085 #define CIU9 0x00008000lu
3086 #define CIU10 0x00800000lu
3087 #define CIU11 0x80000000lu
3089 #define CL8 0x0000007Flu
3090 #define CL9 0x00007F00lu
3091 #define CL10 0x007F0000lu
3092 #define CL11 0x7F000000lu
3095 /* MXVR_ALLOC_3 Masks */
3097 #define CIU12 0x00000080lu
3098 #define CIU13 0x00008000lu
3099 #define CIU14 0x00800000lu
3100 #define CIU15 0x80000000lu
3102 #define CL12 0x0000007Flu
3103 #define CL13 0x00007F00lu
3104 #define CL14 0x007F0000lu
3105 #define CL15 0x7F000000lu
3108 /* MXVR_ALLOC_4 Masks */
3110 #define CIU16 0x00000080lu
3111 #define CIU17 0x00008000lu
3112 #define CIU18 0x00800000lu
3113 #define CIU19 0x80000000lu
3115 #define CL16 0x0000007Flu
3116 #define CL17 0x00007F00lu
3117 #define CL18 0x007F0000lu
3118 #define CL19 0x7F000000lu
3121 /* MXVR_ALLOC_5 Masks */
3123 #define CIU20 0x00000080lu
3124 #define CIU21 0x00008000lu
3125 #define CIU22 0x00800000lu
3126 #define CIU23 0x80000000lu
3128 #define CL20 0x0000007Flu
3129 #define CL21 0x00007F00lu
3130 #define CL22 0x007F0000lu
3131 #define CL23 0x7F000000lu
3134 /* MXVR_ALLOC_6 Masks */
3136 #define CIU24 0x00000080lu
3137 #define CIU25 0x00008000lu
3138 #define CIU26 0x00800000lu
3139 #define CIU27 0x80000000lu
3141 #define CL24 0x0000007Flu
3142 #define CL25 0x00007F00lu
3143 #define CL26 0x007F0000lu
3144 #define CL27 0x7F000000lu
3147 /* MXVR_ALLOC_7 Masks */
3149 #define CIU28 0x00000080lu
3150 #define CIU29 0x00008000lu
3151 #define CIU30 0x00800000lu
3152 #define CIU31 0x80000000lu
3154 #define CL28 0x0000007Flu
3155 #define CL29 0x00007F00lu
3156 #define CL30 0x007F0000lu
3157 #define CL31 0x7F000000lu
3160 /* MXVR_ALLOC_8 Masks */
3162 #define CIU32 0x00000080lu
3163 #define CIU33 0x00008000lu
3164 #define CIU34 0x00800000lu
3165 #define CIU35 0x80000000lu
3167 #define CL32 0x0000007Flu
3168 #define CL33 0x00007F00lu
3169 #define CL34 0x007F0000lu
3170 #define CL35 0x7F000000lu
3173 /* MXVR_ALLOC_9 Masks */
3175 #define CIU36 0x00000080lu
3176 #define CIU37 0x00008000lu
3177 #define CIU38 0x00800000lu
3178 #define CIU39 0x80000000lu
3180 #define CL36 0x0000007Flu
3181 #define CL37 0x00007F00lu
3182 #define CL38 0x007F0000lu
3183 #define CL39 0x7F000000lu
3186 /* MXVR_ALLOC_10 Masks */
3188 #define CIU40 0x00000080lu
3189 #define CIU41 0x00008000lu
3190 #define CIU42 0x00800000lu
3191 #define CIU43 0x80000000lu
3193 #define CL40 0x0000007Flu
3194 #define CL41 0x00007F00lu
3195 #define CL42 0x007F0000lu
3196 #define CL43 0x7F000000lu
3199 /* MXVR_ALLOC_11 Masks */
3201 #define CIU44 0x00000080lu
3202 #define CIU45 0x00008000lu
3203 #define CIU46 0x00800000lu
3204 #define CIU47 0x80000000lu
3206 #define CL44 0x0000007Flu
3207 #define CL45 0x00007F00lu
3208 #define CL46 0x007F0000lu
3209 #define CL47 0x7F000000lu
3212 /* MXVR_ALLOC_12 Masks */
3214 #define CIU48 0x00000080lu
3215 #define CIU49 0x00008000lu
3216 #define CIU50 0x00800000lu
3217 #define CIU51 0x80000000lu
3219 #define CL48 0x0000007Flu
3220 #define CL49 0x00007F00lu
3221 #define CL50 0x007F0000lu
3222 #define CL51 0x7F000000lu
3225 /* MXVR_ALLOC_13 Masks */
3227 #define CIU52 0x00000080lu
3228 #define CIU53 0x00008000lu
3229 #define CIU54 0x00800000lu
3230 #define CIU55 0x80000000lu
3232 #define CL52 0x0000007Flu
3233 #define CL53 0x00007F00lu
3234 #define CL54 0x007F0000lu
3235 #define CL55 0x7F000000lu
3238 /* MXVR_ALLOC_14 Masks */
3240 #define CIU56 0x00000080lu
3241 #define CIU57 0x00008000lu
3242 #define CIU58 0x00800000lu
3243 #define CIU59 0x80000000lu
3245 #define CL56 0x0000007Flu
3246 #define CL57 0x00007F00lu
3247 #define CL58 0x007F0000lu
3248 #define CL59 0x7F000000lu
3251 /* MXVR_SYNC_LCHAN_0 Masks */
3253 #define LCHANPC0 0x0000000Flu
3254 #define LCHANPC1 0x000000F0lu
3255 #define LCHANPC2 0x00000F00lu
3256 #define LCHANPC3 0x0000F000lu
3257 #define LCHANPC4 0x000F0000lu
3258 #define LCHANPC5 0x00F00000lu
3259 #define LCHANPC6 0x0F000000lu
3260 #define LCHANPC7 0xF0000000lu
3263 /* MXVR_SYNC_LCHAN_1 Masks */
3265 #define LCHANPC8 0x0000000Flu
3266 #define LCHANPC9 0x000000F0lu
3267 #define LCHANPC10 0x00000F00lu
3268 #define LCHANPC11 0x0000F000lu
3269 #define LCHANPC12 0x000F0000lu
3270 #define LCHANPC13 0x00F00000lu
3271 #define LCHANPC14 0x0F000000lu
3272 #define LCHANPC15 0xF0000000lu
3275 /* MXVR_SYNC_LCHAN_2 Masks */
3277 #define LCHANPC16 0x0000000Flu
3278 #define LCHANPC17 0x000000F0lu
3279 #define LCHANPC18 0x00000F00lu
3280 #define LCHANPC19 0x0000F000lu
3281 #define LCHANPC20 0x000F0000lu
3282 #define LCHANPC21 0x00F00000lu
3283 #define LCHANPC22 0x0F000000lu
3284 #define LCHANPC23 0xF0000000lu
3287 /* MXVR_SYNC_LCHAN_3 Masks */
3289 #define LCHANPC24 0x0000000Flu
3290 #define LCHANPC25 0x000000F0lu
3291 #define LCHANPC26 0x00000F00lu
3292 #define LCHANPC27 0x0000F000lu
3293 #define LCHANPC28 0x000F0000lu
3294 #define LCHANPC29 0x00F00000lu
3295 #define LCHANPC30 0x0F000000lu
3296 #define LCHANPC31 0xF0000000lu
3299 /* MXVR_SYNC_LCHAN_4 Masks */
3301 #define LCHANPC32 0x0000000Flu
3302 #define LCHANPC33 0x000000F0lu
3303 #define LCHANPC34 0x00000F00lu
3304 #define LCHANPC35 0x0000F000lu
3305 #define LCHANPC36 0x000F0000lu
3306 #define LCHANPC37 0x00F00000lu
3307 #define LCHANPC38 0x0F000000lu
3308 #define LCHANPC39 0xF0000000lu
3311 /* MXVR_SYNC_LCHAN_5 Masks */
3313 #define LCHANPC40 0x0000000Flu
3314 #define LCHANPC41 0x000000F0lu
3315 #define LCHANPC42 0x00000F00lu
3316 #define LCHANPC43 0x0000F000lu
3317 #define LCHANPC44 0x000F0000lu
3318 #define LCHANPC45 0x00F00000lu
3319 #define LCHANPC46 0x0F000000lu
3320 #define LCHANPC47 0xF0000000lu
3323 /* MXVR_SYNC_LCHAN_6 Masks */
3325 #define LCHANPC48 0x0000000Flu
3326 #define LCHANPC49 0x000000F0lu
3327 #define LCHANPC50 0x00000F00lu
3328 #define LCHANPC51 0x0000F000lu
3329 #define LCHANPC52 0x000F0000lu
3330 #define LCHANPC53 0x00F00000lu
3331 #define LCHANPC54 0x0F000000lu
3332 #define LCHANPC55 0xF0000000lu
3335 /* MXVR_SYNC_LCHAN_7 Masks */
3337 #define LCHANPC56 0x0000000Flu
3338 #define LCHANPC57 0x000000F0lu
3339 #define LCHANPC58 0x00000F00lu
3340 #define LCHANPC59 0x0000F000lu
3343 /* MXVR_DMAx_CONFIG Masks */
3345 #define MDMAEN 0x00000001lu
3346 #define DD 0x00000002lu
3347 #define LCHAN 0x000003C0lu
3348 #define BITSWAPEN 0x00000400lu
3349 #define BYSWAPEN 0x00000800lu
3350 #define MFLOW 0x00007000lu
3351 #define FIXEDPM 0x00080000lu
3352 #define STARTPAT 0x00300000lu
3353 #define STOPPAT 0x00C00000lu
3354 #define COUNTPOS 0x1C000000lu
3356 #define DD_TX 0x00000000lu
3357 #define DD_RX 0x00000002lu
3359 #define LCHAN_0 0x00000000lu
3360 #define LCHAN_1 0x00000040lu
3361 #define LCHAN_2 0x00000080lu
3362 #define LCHAN_3 0x000000C0lu
3363 #define LCHAN_4 0x00000100lu
3364 #define LCHAN_5 0x00000140lu
3365 #define LCHAN_6 0x00000180lu
3366 #define LCHAN_7 0x000001C0lu
3368 #define MFLOW_STOP 0x00000000lu
3369 #define MFLOW_AUTO 0x00001000lu
3370 #define MFLOW_PVC 0x00002000lu
3371 #define MFLOW_PSS 0x00003000lu
3372 #define MFLOW_PFC 0x00004000lu
3374 #define STARTPAT_0 0x00000000lu
3375 #define STARTPAT_1 0x00100000lu
3377 #define STOPPAT_0 0x00000000lu
3378 #define STOPPAT_1 0x00400000lu
3380 #define COUNTPOS_0 0x00000000lu
3381 #define COUNTPOS_1 0x04000000lu
3382 #define COUNTPOS_2 0x08000000lu
3383 #define COUNTPOS_3 0x0C000000lu
3384 #define COUNTPOS_4 0x10000000lu
3385 #define COUNTPOS_5 0x14000000lu
3386 #define COUNTPOS_6 0x18000000lu
3387 #define COUNTPOS_7 0x1C000000lu
3390 /* MXVR_AP_CTL Masks */
3392 #define STARTAP 0x00000001lu
3393 #define CANCELAP 0x00000002lu
3394 #define RESETAP 0x00000004lu
3395 #define APRBE0 0x00004000lu
3396 #define APRBE1 0x00008000lu
3397 #define APRBEX 0x0000C000lu
3400 /* MXVR_CM_CTL Masks */
3402 #define STARTCM 0x00000001lu
3403 #define CANCELCM 0x00000002lu
3404 #define CMRBEX 0xFFFF0000lu
3405 #define CMRBE0 0x00010000lu
3406 #define CMRBE1 0x00020000lu
3407 #define CMRBE2 0x00040000lu
3408 #define CMRBE3 0x00080000lu
3409 #define CMRBE4 0x00100000lu
3410 #define CMRBE5 0x00200000lu
3411 #define CMRBE6 0x00400000lu
3412 #define CMRBE7 0x00800000lu
3413 #define CMRBE8 0x01000000lu
3414 #define CMRBE9 0x02000000lu
3415 #define CMRBE10 0x04000000lu
3416 #define CMRBE11 0x08000000lu
3417 #define CMRBE12 0x10000000lu
3418 #define CMRBE13 0x20000000lu
3419 #define CMRBE14 0x40000000lu
3420 #define CMRBE15 0x80000000lu
3423 /* MXVR_PAT_DATA_x Masks */
3425 #define MATCH_DATA_0 0x000000FFlu
3426 #define MATCH_DATA_1 0x0000FF00lu
3427 #define MATCH_DATA_2 0x00FF0000lu
3428 #define MATCH_DATA_3 0xFF000000lu
3432 /* MXVR_PAT_EN_x Masks */
3434 #define MATCH_EN_0_0 0x00000001lu
3435 #define MATCH_EN_0_1 0x00000002lu
3436 #define MATCH_EN_0_2 0x00000004lu
3437 #define MATCH_EN_0_3 0x00000008lu
3438 #define MATCH_EN_0_4 0x00000010lu
3439 #define MATCH_EN_0_5 0x00000020lu
3440 #define MATCH_EN_0_6 0x00000040lu
3441 #define MATCH_EN_0_7 0x00000080lu
3443 #define MATCH_EN_1_0 0x00000100lu
3444 #define MATCH_EN_1_1 0x00000200lu
3445 #define MATCH_EN_1_2 0x00000400lu
3446 #define MATCH_EN_1_3 0x00000800lu
3447 #define MATCH_EN_1_4 0x00001000lu
3448 #define MATCH_EN_1_5 0x00002000lu
3449 #define MATCH_EN_1_6 0x00004000lu
3450 #define MATCH_EN_1_7 0x00008000lu
3452 #define MATCH_EN_2_0 0x00010000lu
3453 #define MATCH_EN_2_1 0x00020000lu
3454 #define MATCH_EN_2_2 0x00040000lu
3455 #define MATCH_EN_2_3 0x00080000lu
3456 #define MATCH_EN_2_4 0x00100000lu
3457 #define MATCH_EN_2_5 0x00200000lu
3458 #define MATCH_EN_2_6 0x00400000lu
3459 #define MATCH_EN_2_7 0x00800000lu
3461 #define MATCH_EN_3_0 0x01000000lu
3462 #define MATCH_EN_3_1 0x02000000lu
3463 #define MATCH_EN_3_2 0x04000000lu
3464 #define MATCH_EN_3_3 0x08000000lu
3465 #define MATCH_EN_3_4 0x10000000lu
3466 #define MATCH_EN_3_5 0x20000000lu
3467 #define MATCH_EN_3_6 0x40000000lu
3468 #define MATCH_EN_3_7 0x80000000lu
3471 /* MXVR_ROUTING_0 Masks */
3473 #define MUTE_CH0 0x00000080lu
3474 #define MUTE_CH1 0x00008000lu
3475 #define MUTE_CH2 0x00800000lu
3476 #define MUTE_CH3 0x80000000lu
3478 #define TX_CH0 0x0000007Flu
3479 #define TX_CH1 0x00007F00lu
3480 #define TX_CH2 0x007F0000lu
3481 #define TX_CH3 0x7F000000lu
3484 /* MXVR_ROUTING_1 Masks */
3486 #define MUTE_CH4 0x00000080lu
3487 #define MUTE_CH5 0x00008000lu
3488 #define MUTE_CH6 0x00800000lu
3489 #define MUTE_CH7 0x80000000lu
3491 #define TX_CH4 0x0000007Flu
3492 #define TX_CH5 0x00007F00lu
3493 #define TX_CH6 0x007F0000lu
3494 #define TX_CH7 0x7F000000lu
3497 /* MXVR_ROUTING_2 Masks */
3499 #define MUTE_CH8 0x00000080lu
3500 #define MUTE_CH9 0x00008000lu
3501 #define MUTE_CH10 0x00800000lu
3502 #define MUTE_CH11 0x80000000lu
3504 #define TX_CH8 0x0000007Flu
3505 #define TX_CH9 0x00007F00lu
3506 #define TX_CH10 0x007F0000lu
3507 #define TX_CH11 0x7F000000lu
3509 /* MXVR_ROUTING_3 Masks */
3511 #define MUTE_CH12 0x00000080lu
3512 #define MUTE_CH13 0x00008000lu
3513 #define MUTE_CH14 0x00800000lu
3514 #define MUTE_CH15 0x80000000lu
3516 #define TX_CH12 0x0000007Flu
3517 #define TX_CH13 0x00007F00lu
3518 #define TX_CH14 0x007F0000lu
3519 #define TX_CH15 0x7F000000lu
3522 /* MXVR_ROUTING_4 Masks */
3524 #define MUTE_CH16 0x00000080lu
3525 #define MUTE_CH17 0x00008000lu
3526 #define MUTE_CH18 0x00800000lu
3527 #define MUTE_CH19 0x80000000lu
3529 #define TX_CH16 0x0000007Flu
3530 #define TX_CH17 0x00007F00lu
3531 #define TX_CH18 0x007F0000lu
3532 #define TX_CH19 0x7F000000lu
3535 /* MXVR_ROUTING_5 Masks */
3537 #define MUTE_CH20 0x00000080lu
3538 #define MUTE_CH21 0x00008000lu
3539 #define MUTE_CH22 0x00800000lu
3540 #define MUTE_CH23 0x80000000lu
3542 #define TX_CH20 0x0000007Flu
3543 #define TX_CH21 0x00007F00lu
3544 #define TX_CH22 0x007F0000lu
3545 #define TX_CH23 0x7F000000lu
3548 /* MXVR_ROUTING_6 Masks */
3550 #define MUTE_CH24 0x00000080lu
3551 #define MUTE_CH25 0x00008000lu
3552 #define MUTE_CH26 0x00800000lu
3553 #define MUTE_CH27 0x80000000lu
3555 #define TX_CH24 0x0000007Flu
3556 #define TX_CH25 0x00007F00lu
3557 #define TX_CH26 0x007F0000lu
3558 #define TX_CH27 0x7F000000lu
3561 /* MXVR_ROUTING_7 Masks */
3563 #define MUTE_CH28 0x00000080lu
3564 #define MUTE_CH29 0x00008000lu
3565 #define MUTE_CH30 0x00800000lu
3566 #define MUTE_CH31 0x80000000lu
3568 #define TX_CH28 0x0000007Flu
3569 #define TX_CH29 0x00007F00lu
3570 #define TX_CH30 0x007F0000lu
3571 #define TX_CH31 0x7F000000lu
3574 /* MXVR_ROUTING_8 Masks */
3576 #define MUTE_CH32 0x00000080lu
3577 #define MUTE_CH33 0x00008000lu
3578 #define MUTE_CH34 0x00800000lu
3579 #define MUTE_CH35 0x80000000lu
3581 #define TX_CH32 0x0000007Flu
3582 #define TX_CH33 0x00007F00lu
3583 #define TX_CH34 0x007F0000lu
3584 #define TX_CH35 0x7F000000lu
3587 /* MXVR_ROUTING_9 Masks */
3589 #define MUTE_CH36 0x00000080lu
3590 #define MUTE_CH37 0x00008000lu
3591 #define MUTE_CH38 0x00800000lu
3592 #define MUTE_CH39 0x80000000lu
3594 #define TX_CH36 0x0000007Flu
3595 #define TX_CH37 0x00007F00lu
3596 #define TX_CH38 0x007F0000lu
3597 #define TX_CH39 0x7F000000lu
3600 /* MXVR_ROUTING_10 Masks */
3602 #define MUTE_CH40 0x00000080lu
3603 #define MUTE_CH41 0x00008000lu
3604 #define MUTE_CH42 0x00800000lu
3605 #define MUTE_CH43 0x80000000lu
3607 #define TX_CH40 0x0000007Flu
3608 #define TX_CH41 0x00007F00lu
3609 #define TX_CH42 0x007F0000lu
3610 #define TX_CH43 0x7F000000lu
3613 /* MXVR_ROUTING_11 Masks */
3615 #define MUTE_CH44 0x00000080lu
3616 #define MUTE_CH45 0x00008000lu
3617 #define MUTE_CH46 0x00800000lu
3618 #define MUTE_CH47 0x80000000lu
3620 #define TX_CH44 0x0000007Flu
3621 #define TX_CH45 0x00007F00lu
3622 #define TX_CH46 0x007F0000lu
3623 #define TX_CH47 0x7F000000lu
3626 /* MXVR_ROUTING_12 Masks */
3628 #define MUTE_CH48 0x00000080lu
3629 #define MUTE_CH49 0x00008000lu
3630 #define MUTE_CH50 0x00800000lu
3631 #define MUTE_CH51 0x80000000lu
3633 #define TX_CH48 0x0000007Flu
3634 #define TX_CH49 0x00007F00lu
3635 #define TX_CH50 0x007F0000lu
3636 #define TX_CH51 0x7F000000lu
3639 /* MXVR_ROUTING_13 Masks */
3641 #define MUTE_CH52 0x00000080lu
3642 #define MUTE_CH53 0x00008000lu
3643 #define MUTE_CH54 0x00800000lu
3644 #define MUTE_CH55 0x80000000lu
3646 #define TX_CH52 0x0000007Flu
3647 #define TX_CH53 0x00007F00lu
3648 #define TX_CH54 0x007F0000lu
3649 #define TX_CH55 0x7F000000lu
3652 /* MXVR_ROUTING_14 Masks */
3654 #define MUTE_CH56 0x00000080lu
3655 #define MUTE_CH57 0x00008000lu
3656 #define MUTE_CH58 0x00800000lu
3657 #define MUTE_CH59 0x80000000lu
3659 #define TX_CH56 0x0000007Flu
3660 #define TX_CH57 0x00007F00lu
3661 #define TX_CH58 0x007F0000lu
3662 #define TX_CH59 0x7F000000lu
3665 /* Control Message Receive Buffer (CMRB) Address Offsets */
3667 #define CMRB_STRIDE 0x00000016lu
3669 #define CMRB_DST_OFFSET 0x00000000lu
3670 #define CMRB_SRC_OFFSET 0x00000002lu
3671 #define CMRB_DATA_OFFSET 0x00000005lu
3674 /* Control Message Transmit Buffer (CMTB) Address Offsets */
3676 #define CMTB_PRIO_OFFSET 0x00000000lu
3677 #define CMTB_DST_OFFSET 0x00000002lu
3678 #define CMTB_SRC_OFFSET 0x00000004lu
3679 #define CMTB_TYPE_OFFSET 0x00000006lu
3680 #define CMTB_DATA_OFFSET 0x00000007lu
3682 #define CMTB_ANSWER_OFFSET 0x0000000Alu
3684 #define CMTB_STAT_N_OFFSET 0x00000018lu
3685 #define CMTB_STAT_A_OFFSET 0x00000016lu
3686 #define CMTB_STAT_D_OFFSET 0x0000000Elu
3687 #define CMTB_STAT_R_OFFSET 0x00000014lu
3688 #define CMTB_STAT_W_OFFSET 0x00000014lu
3689 #define CMTB_STAT_G_OFFSET 0x00000014lu
3692 /* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
3694 #define APRB_STRIDE 0x00000400lu
3696 #define APRB_DST_OFFSET 0x00000000lu
3697 #define APRB_LEN_OFFSET 0x00000002lu
3698 #define APRB_SRC_OFFSET 0x00000004lu
3699 #define APRB_DATA_OFFSET 0x00000006lu
3702 /* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
3704 #define APTB_PRIO_OFFSET 0x00000000lu
3705 #define APTB_DST_OFFSET 0x00000002lu
3706 #define APTB_LEN_OFFSET 0x00000004lu
3707 #define APTB_SRC_OFFSET 0x00000006lu
3708 #define APTB_DATA_OFFSET 0x00000008lu
3711 /* Remote Read Buffer (RRDB) Address Offsets */
3713 #define RRDB_WADDR_OFFSET 0x00000100lu
3714 #define RRDB_WLEN_OFFSET 0x00000101lu
3718 /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
3719 /* CAN_CONTROL Masks */
3720 #define SRS 0x0001 /* Software Reset */
3721 #define DNM 0x0002 /* Device Net Mode */
3722 #define ABO 0x0004 /* Auto-Bus On Enable */
3723 #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
3724 #define SMR 0x0020 /* Sleep Mode Request */
3725 #define CSR 0x0040 /* CAN Suspend Mode Request */
3726 #define CCR 0x0080 /* CAN Configuration Mode Request */
3728 /* CAN_STATUS Masks */
3729 #define WT 0x0001 /* TX Warning Flag */
3730 #define WR 0x0002 /* RX Warning Flag */
3731 #define EP 0x0004 /* Error Passive Mode */
3732 #define EBO 0x0008 /* Error Bus Off Mode */
3733 #define CSA 0x0040 /* Suspend Mode Acknowledge */
3734 #define CCA 0x0080 /* Configuration Mode Acknowledge */
3735 #define MBPTR 0x1F00 /* Mailbox Pointer */
3736 #define TRM 0x4000 /* Transmit Mode */
3737 #define REC 0x8000 /* Receive Mode */
3739 /* CAN_CLOCK Masks */
3740 #define BRP 0x03FF /* Bit-Rate Pre-Scaler */
3742 /* CAN_TIMING Masks */
3743 #define TSEG1 0x000F /* Time Segment 1 */
3744 #define TSEG2 0x0070 /* Time Segment 2 */
3745 #define SAM 0x0080 /* Sampling */
3746 #define SJW 0x0300 /* Synchronization Jump Width */
3748 /* CAN_DEBUG Masks */
3749 #define DEC 0x0001 /* Disable CAN Error Counters */
3750 #define DRI 0x0002 /* Disable CAN RX Input */
3751 #define DTO 0x0004 /* Disable CAN TX Output */
3752 #define DIL 0x0008 /* Disable CAN Internal Loop */
3753 #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
3754 #define MRB 0x0020 /* Mode Read Back Enable */
3755 #define CDE 0x8000 /* CAN Debug Enable */
3758 #define RXECNT 0x00FF /* Receive Error Counter */
3759 #define TXECNT 0xFF00 /* Transmit Error Counter */
3761 /* CAN_INTR Masks */
3762 #define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
3763 #define MBRIF MBRIRQ /* legacy */
3764 #define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
3765 #define MBTIF MBTIRQ /* legacy */
3766 #define GIRQ 0x0004 /* Global Interrupt */
3767 #define SMACK 0x0008 /* Sleep Mode Acknowledge */
3768 #define CANTX 0x0040 /* CAN TX Bus Value */
3769 #define CANRX 0x0080 /* CAN RX Bus Value */
3771 /* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
3772 #define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
3773 #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
3774 #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
3775 #define BASEID 0x1FFC /* Base Identifier */
3776 #define IDE 0x2000 /* Identifier Extension */
3777 #define RTR 0x4000 /* Remote Frame Transmission Request */
3778 #define AME 0x8000 /* Acceptance Mask Enable */
3780 /* CAN_MBxx_TIMESTAMP Masks */
3781 #define TSV 0xFFFF /* Timestamp */
3783 /* CAN_MBxx_LENGTH Masks */
3784 #define DLC 0x000F /* Data Length Code */
3786 /* CAN_AMxxH and CAN_AMxxL Masks */
3787 #define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
3788 #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
3789 #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
3790 #define BASEID 0x1FFC /* Base Identifier */
3791 #define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
3792 #define FMD 0x4000 /* Full Mask Data Field Enable */
3793 #define FDF 0x8000 /* Filter On Data Field Enable */
3796 #define MC0 0x0001 /* Enable Mailbox 0 */
3797 #define MC1 0x0002 /* Enable Mailbox 1 */
3798 #define MC2 0x0004 /* Enable Mailbox 2 */
3799 #define MC3 0x0008 /* Enable Mailbox 3 */
3800 #define MC4 0x0010 /* Enable Mailbox 4 */
3801 #define MC5 0x0020 /* Enable Mailbox 5 */
3802 #define MC6 0x0040 /* Enable Mailbox 6 */
3803 #define MC7 0x0080 /* Enable Mailbox 7 */
3804 #define MC8 0x0100 /* Enable Mailbox 8 */
3805 #define MC9 0x0200 /* Enable Mailbox 9 */
3806 #define MC10 0x0400 /* Enable Mailbox 10 */
3807 #define MC11 0x0800 /* Enable Mailbox 11 */
3808 #define MC12 0x1000 /* Enable Mailbox 12 */
3809 #define MC13 0x2000 /* Enable Mailbox 13 */
3810 #define MC14 0x4000 /* Enable Mailbox 14 */
3811 #define MC15 0x8000 /* Enable Mailbox 15 */
3814 #define MC16 0x0001 /* Enable Mailbox 16 */
3815 #define MC17 0x0002 /* Enable Mailbox 17 */
3816 #define MC18 0x0004 /* Enable Mailbox 18 */
3817 #define MC19 0x0008 /* Enable Mailbox 19 */
3818 #define MC20 0x0010 /* Enable Mailbox 20 */
3819 #define MC21 0x0020 /* Enable Mailbox 21 */
3820 #define MC22 0x0040 /* Enable Mailbox 22 */
3821 #define MC23 0x0080 /* Enable Mailbox 23 */
3822 #define MC24 0x0100 /* Enable Mailbox 24 */
3823 #define MC25 0x0200 /* Enable Mailbox 25 */
3824 #define MC26 0x0400 /* Enable Mailbox 26 */
3825 #define MC27 0x0800 /* Enable Mailbox 27 */
3826 #define MC28 0x1000 /* Enable Mailbox 28 */
3827 #define MC29 0x2000 /* Enable Mailbox 29 */
3828 #define MC30 0x4000 /* Enable Mailbox 30 */
3829 #define MC31 0x8000 /* Enable Mailbox 31 */
3832 #define MD0 0x0001 /* Enable Mailbox 0 For Receive */
3833 #define MD1 0x0002 /* Enable Mailbox 1 For Receive */
3834 #define MD2 0x0004 /* Enable Mailbox 2 For Receive */
3835 #define MD3 0x0008 /* Enable Mailbox 3 For Receive */
3836 #define MD4 0x0010 /* Enable Mailbox 4 For Receive */
3837 #define MD5 0x0020 /* Enable Mailbox 5 For Receive */
3838 #define MD6 0x0040 /* Enable Mailbox 6 For Receive */
3839 #define MD7 0x0080 /* Enable Mailbox 7 For Receive */
3840 #define MD8 0x0100 /* Enable Mailbox 8 For Receive */
3841 #define MD9 0x0200 /* Enable Mailbox 9 For Receive */
3842 #define MD10 0x0400 /* Enable Mailbox 10 For Receive */
3843 #define MD11 0x0800 /* Enable Mailbox 11 For Receive */
3844 #define MD12 0x1000 /* Enable Mailbox 12 For Receive */
3845 #define MD13 0x2000 /* Enable Mailbox 13 For Receive */
3846 #define MD14 0x4000 /* Enable Mailbox 14 For Receive */
3847 #define MD15 0x8000 /* Enable Mailbox 15 For Receive */
3850 #define MD16 0x0001 /* Enable Mailbox 16 For Receive */
3851 #define MD17 0x0002 /* Enable Mailbox 17 For Receive */
3852 #define MD18 0x0004 /* Enable Mailbox 18 For Receive */
3853 #define MD19 0x0008 /* Enable Mailbox 19 For Receive */
3854 #define MD20 0x0010 /* Enable Mailbox 20 For Receive */
3855 #define MD21 0x0020 /* Enable Mailbox 21 For Receive */
3856 #define MD22 0x0040 /* Enable Mailbox 22 For Receive */
3857 #define MD23 0x0080 /* Enable Mailbox 23 For Receive */
3858 #define MD24 0x0100 /* Enable Mailbox 24 For Receive */
3859 #define MD25 0x0200 /* Enable Mailbox 25 For Receive */
3860 #define MD26 0x0400 /* Enable Mailbox 26 For Receive */
3861 #define MD27 0x0800 /* Enable Mailbox 27 For Receive */
3862 #define MD28 0x1000 /* Enable Mailbox 28 For Receive */
3863 #define MD29 0x2000 /* Enable Mailbox 29 For Receive */
3864 #define MD30 0x4000 /* Enable Mailbox 30 For Receive */
3865 #define MD31 0x8000 /* Enable Mailbox 31 For Receive */
3867 /* CAN_RMP1 Masks */
3868 #define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
3869 #define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
3870 #define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
3871 #define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
3872 #define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
3873 #define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
3874 #define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
3875 #define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
3876 #define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
3877 #define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
3878 #define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
3879 #define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
3880 #define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
3881 #define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
3882 #define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
3883 #define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
3885 /* CAN_RMP2 Masks */
3886 #define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
3887 #define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
3888 #define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
3889 #define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
3890 #define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
3891 #define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
3892 #define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
3893 #define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
3894 #define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
3895 #define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
3896 #define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
3897 #define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
3898 #define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
3899 #define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
3900 #define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
3901 #define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
3903 /* CAN_RML1 Masks */
3904 #define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
3905 #define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
3906 #define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
3907 #define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
3908 #define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
3909 #define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
3910 #define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
3911 #define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
3912 #define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
3913 #define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
3914 #define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
3915 #define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
3916 #define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
3917 #define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
3918 #define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
3919 #define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
3921 /* CAN_RML2 Masks */
3922 #define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
3923 #define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
3924 #define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
3925 #define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
3926 #define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
3927 #define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
3928 #define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
3929 #define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
3930 #define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
3931 #define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
3932 #define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
3933 #define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
3934 #define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
3935 #define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
3936 #define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
3937 #define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
3939 /* CAN_OPSS1 Masks */
3940 #define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
3941 #define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
3942 #define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
3943 #define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
3944 #define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
3945 #define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
3946 #define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
3947 #define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
3948 #define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
3949 #define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
3950 #define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
3951 #define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
3952 #define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
3953 #define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
3954 #define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
3955 #define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
3957 /* CAN_OPSS2 Masks */
3958 #define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
3959 #define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
3960 #define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
3961 #define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
3962 #define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
3963 #define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
3964 #define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
3965 #define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
3966 #define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
3967 #define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
3968 #define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
3969 #define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
3970 #define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
3971 #define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
3972 #define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
3973 #define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
3975 /* CAN_TRR1 Masks */
3976 #define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
3977 #define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
3978 #define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
3979 #define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
3980 #define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
3981 #define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
3982 #define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
3983 #define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
3984 #define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
3985 #define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
3986 #define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
3987 #define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
3988 #define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
3989 #define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
3990 #define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
3991 #define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
3993 /* CAN_TRR2 Masks */
3994 #define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
3995 #define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
3996 #define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
3997 #define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
3998 #define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
3999 #define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
4000 #define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
4001 #define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
4002 #define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
4003 #define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
4004 #define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
4005 #define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
4006 #define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
4007 #define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
4008 #define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
4009 #define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
4011 /* CAN_TRS1 Masks */
4012 #define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
4013 #define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
4014 #define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
4015 #define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
4016 #define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
4017 #define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
4018 #define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
4019 #define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
4020 #define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
4021 #define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
4022 #define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
4023 #define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
4024 #define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
4025 #define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
4026 #define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
4027 #define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
4029 /* CAN_TRS2 Masks */
4030 #define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
4031 #define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
4032 #define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
4033 #define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
4034 #define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
4035 #define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
4036 #define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
4037 #define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
4038 #define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
4039 #define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
4040 #define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
4041 #define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
4042 #define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
4043 #define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
4044 #define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
4045 #define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
4048 #define AA0 0x0001 /* Aborted Message In Mailbox 0 */
4049 #define AA1 0x0002 /* Aborted Message In Mailbox 1 */
4050 #define AA2 0x0004 /* Aborted Message In Mailbox 2 */
4051 #define AA3 0x0008 /* Aborted Message In Mailbox 3 */
4052 #define AA4 0x0010 /* Aborted Message In Mailbox 4 */
4053 #define AA5 0x0020 /* Aborted Message In Mailbox 5 */
4054 #define AA6 0x0040 /* Aborted Message In Mailbox 6 */
4055 #define AA7 0x0080 /* Aborted Message In Mailbox 7 */
4056 #define AA8 0x0100 /* Aborted Message In Mailbox 8 */
4057 #define AA9 0x0200 /* Aborted Message In Mailbox 9 */
4058 #define AA10 0x0400 /* Aborted Message In Mailbox 10 */
4059 #define AA11 0x0800 /* Aborted Message In Mailbox 11 */
4060 #define AA12 0x1000 /* Aborted Message In Mailbox 12 */
4061 #define AA13 0x2000 /* Aborted Message In Mailbox 13 */
4062 #define AA14 0x4000 /* Aborted Message In Mailbox 14 */
4063 #define AA15 0x8000 /* Aborted Message In Mailbox 15 */
4066 #define AA16 0x0001 /* Aborted Message In Mailbox 16 */
4067 #define AA17 0x0002 /* Aborted Message In Mailbox 17 */
4068 #define AA18 0x0004 /* Aborted Message In Mailbox 18 */
4069 #define AA19 0x0008 /* Aborted Message In Mailbox 19 */
4070 #define AA20 0x0010 /* Aborted Message In Mailbox 20 */
4071 #define AA21 0x0020 /* Aborted Message In Mailbox 21 */
4072 #define AA22 0x0040 /* Aborted Message In Mailbox 22 */
4073 #define AA23 0x0080 /* Aborted Message In Mailbox 23 */
4074 #define AA24 0x0100 /* Aborted Message In Mailbox 24 */
4075 #define AA25 0x0200 /* Aborted Message In Mailbox 25 */
4076 #define AA26 0x0400 /* Aborted Message In Mailbox 26 */
4077 #define AA27 0x0800 /* Aborted Message In Mailbox 27 */
4078 #define AA28 0x1000 /* Aborted Message In Mailbox 28 */
4079 #define AA29 0x2000 /* Aborted Message In Mailbox 29 */
4080 #define AA30 0x4000 /* Aborted Message In Mailbox 30 */
4081 #define AA31 0x8000 /* Aborted Message In Mailbox 31 */
4084 #define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
4085 #define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
4086 #define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
4087 #define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
4088 #define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
4089 #define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
4090 #define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
4091 #define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
4092 #define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
4093 #define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
4094 #define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
4095 #define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
4096 #define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
4097 #define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
4098 #define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
4099 #define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
4102 #define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
4103 #define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
4104 #define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
4105 #define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
4106 #define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
4107 #define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
4108 #define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
4109 #define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
4110 #define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
4111 #define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
4112 #define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
4113 #define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
4114 #define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
4115 #define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
4116 #define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
4117 #define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
4119 /* CAN_MBTD Masks */
4120 #define TDPTR 0x001F /* Mailbox To Temporarily Disable */
4121 #define TDA 0x0040 /* Temporary Disable Acknowledge */
4122 #define TDR 0x0080 /* Temporary Disable Request */
4124 /* CAN_RFH1 Masks */
4125 #define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
4126 #define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
4127 #define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
4128 #define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
4129 #define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
4130 #define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
4131 #define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
4132 #define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
4133 #define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
4134 #define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
4135 #define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
4136 #define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
4137 #define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
4138 #define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
4139 #define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
4140 #define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
4142 /* CAN_RFH2 Masks */
4143 #define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
4144 #define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
4145 #define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
4146 #define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
4147 #define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
4148 #define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
4149 #define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
4150 #define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
4151 #define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
4152 #define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
4153 #define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
4154 #define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
4155 #define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
4156 #define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
4157 #define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
4158 #define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
4160 /* CAN_MBTIF1 Masks */
4161 #define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
4162 #define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
4163 #define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
4164 #define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
4165 #define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
4166 #define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
4167 #define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
4168 #define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
4169 #define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
4170 #define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
4171 #define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
4172 #define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
4173 #define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
4174 #define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
4175 #define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
4176 #define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
4178 /* CAN_MBTIF2 Masks */
4179 #define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
4180 #define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
4181 #define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
4182 #define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
4183 #define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
4184 #define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
4185 #define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
4186 #define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
4187 #define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
4188 #define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
4189 #define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
4190 #define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
4191 #define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
4192 #define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
4193 #define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
4194 #define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
4196 /* CAN_MBRIF1 Masks */
4197 #define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
4198 #define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
4199 #define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
4200 #define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
4201 #define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
4202 #define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
4203 #define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
4204 #define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
4205 #define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
4206 #define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
4207 #define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
4208 #define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
4209 #define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
4210 #define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
4211 #define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
4212 #define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
4214 /* CAN_MBRIF2 Masks */
4215 #define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
4216 #define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
4217 #define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
4218 #define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
4219 #define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
4220 #define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
4221 #define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
4222 #define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
4223 #define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
4224 #define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
4225 #define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
4226 #define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
4227 #define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
4228 #define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
4229 #define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
4230 #define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
4232 /* CAN_MBIM1 Masks */
4233 #define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
4234 #define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
4235 #define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
4236 #define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
4237 #define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
4238 #define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
4239 #define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
4240 #define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
4241 #define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
4242 #define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
4243 #define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
4244 #define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
4245 #define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
4246 #define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
4247 #define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
4248 #define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
4250 /* CAN_MBIM2 Masks */
4251 #define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
4252 #define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
4253 #define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
4254 #define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
4255 #define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
4256 #define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
4257 #define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
4258 #define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
4259 #define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
4260 #define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
4261 #define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
4262 #define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
4263 #define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
4264 #define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
4265 #define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
4266 #define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
4269 #define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
4270 #define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
4271 #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
4272 #define BOIM 0x0008 /* Enable Bus Off Interrupt */
4273 #define WUIM 0x0010 /* Enable Wake-Up Interrupt */
4274 #define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
4275 #define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
4276 #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
4277 #define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
4278 #define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
4279 #define ADIM 0x0400 /* Enable Access Denied Interrupt */
4282 #define EWTIS 0x0001 /* TX Error Count IRQ Status */
4283 #define EWRIS 0x0002 /* RX Error Count IRQ Status */
4284 #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
4285 #define BOIS 0x0008 /* Bus Off IRQ Status */
4286 #define WUIS 0x0010 /* Wake-Up IRQ Status */
4287 #define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
4288 #define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
4289 #define RMLIS 0x0080 /* RX Message Lost IRQ Status */
4290 #define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
4291 #define EXTIS 0x0200 /* External Trigger Output IRQ Status */
4292 #define ADIS 0x0400 /* Access Denied IRQ Status */
4295 #define EWTIF 0x0001 /* TX Error Count IRQ Flag */
4296 #define EWRIF 0x0002 /* RX Error Count IRQ Flag */
4297 #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
4298 #define BOIF 0x0008 /* Bus Off IRQ Flag */
4299 #define WUIF 0x0010 /* Wake-Up IRQ Flag */
4300 #define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
4301 #define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
4302 #define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
4303 #define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
4304 #define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
4305 #define ADIF 0x0400 /* Access Denied IRQ Flag */
4307 /* CAN_UCCNF Masks */
4308 #define UCCNF 0x000F /* Universal Counter Mode */
4309 #define UC_STAMP 0x0001 /* Timestamp Mode */
4310 #define UC_WDOG 0x0002 /* Watchdog Mode */
4311 #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
4312 #define UC_ERROR 0x0006 /* CAN Error Frame Count */
4313 #define UC_OVER 0x0007 /* CAN Overload Frame Count */
4314 #define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
4315 #define UC_AA 0x0009 /* TX Abort Count */
4316 #define UC_TA 0x000A /* TX Successful Count */
4317 #define UC_REJECT 0x000B /* RX Message Rejected Count */
4318 #define UC_RML 0x000C /* RX Message Lost Count */
4319 #define UC_RX 0x000D /* Total Successful RX Messages Count */
4320 #define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
4321 #define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
4322 #define UCRC 0x0020 /* Universal Counter Reload/Clear */
4323 #define UCCT 0x0040 /* Universal Counter CAN Trigger */
4324 #define UCE 0x0080 /* Universal Counter Enable */
4327 #define ACKE 0x0004 /* Acknowledge Error */
4328 #define SER 0x0008 /* Stuff Error */
4329 #define CRCE 0x0010 /* CRC Error */
4330 #define SA0 0x0020 /* Stuck At Dominant Error */
4331 #define BEF 0x0040 /* Bit Error Flag */
4332 #define FER 0x0080 /* Form Error Flag */
4335 #define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
4336 #define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
4341 #endif /* _MISRA_RULES */
4343 #endif /* _DEF_BF539_H */
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