libgloss/bfin/include/defBF514.h

   1 /*
   2  * The authors hereby grant permission to use, copy, modify, distribute,
   3  * and license this software and its documentation for any purpose, provided
   4  * that existing copyright notices are retained in all copies and that this
   5  * notice is included verbatim in any distributions. No written agreement,
   6  * license, or royalty fee is required for any of the authorized uses.
   7  * Modifications to this software may be copyrighted by their authors
   8  * and need not follow the licensing terms described here, provided that
   9  * the new terms are clearly indicated on the first page of each file where
  10  * they apply.
  11  */
  12
  13 /*
  14 ** Copyright (C) 2009 Analog Devices, Inc.
  15 **
  16 ************************************************************************************
  17 **
  18 ** This include file contains a list of macro "defines" to enable the programmer
  19 ** to use symbolic names for register-access and bit-manipulation.
  20 **
  21 **/
  22 #ifndef _DEF_BF514_H
  23 #define _DEF_BF514_H
  24
  25 /* Include all Core registers and bit definitions */
  26 #include <def_LPBlackfin.h>
  27
  28 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
  29
  30 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
  31 #include <defBF51x_base.h>
  32
  33 #ifdef _MISRA_RULES
  34 #pragma diag(push)
  35 #pragma diag(suppress:misra_rule_19_4:"macros violate rule 19.4")
  36 #endif /* _MISRA_RULES */
  37
  38 /* The following are the #defines needed by ADSP-BF514 that are not in the common header */
  39
  40 /* RSI Registers */
  41
  42 #define RSI_PWR_CONTROL                 0xFFC03800              /* RSI Power Control Register */
  43 /* legacy register name (below) provided for backwards code compatibility */
  44 #define SDH_PWR_CTL                     RSI_PWR_CONTROL /* SDH Power Control */
  45 #define RSI_CLK_CONTROL                 0xFFC03804              /* RSI Clock Control Register */
  46 /* legacy register name (below) provided for backwards code compatibility */
  47 #define SDH_CLK_CTL                     RSI_CLK_CONTROL /* SDH Clock Control */
  48 #define RSI_ARGUMENT                    0xFFC03808              /* RSI Argument Register */
  49 /* legacy register name (below) provided for backwards code compatibility */
  50 #define SDH_ARGUMENT                    RSI_ARGUMENT    /* SDH Argument */
  51 #define RSI_COMMAND                     0xFFC0380C              /* RSI Command Register */
  52 /* legacy register name (below) provided for backwards code compatibility */
  53 #define SDH_COMMAND                     RSI_COMMAND             /* SDH Command */
  54 #define RSI_RESP_CMD                    0xFFC03810              /* RSI Response Command Register */
  55 /* legacy register name (below) provided for backwards code compatibility */
  56 #define SDH_RESP_CMD                    RSI_RESP_CMD            /* SDH Response Command */
  57 #define RSI_RESPONSE0                   0xFFC03814              /* RSI Response Register */
  58 /* legacy register name (below) provided for backwards code compatibility */
  59 #define SDH_RESPONSE0                   RSI_RESPONSE0           /* SDH Response0 */
  60 #define RSI_RESPONSE1                   0xFFC03818              /* RSI Response Register */
  61 /* legacy register name (below) provided for backwards code compatibility */
  62 #define SDH_RESPONSE1                   RSI_RESPONSE1           /* SDH Response1 */
  63 #define RSI_RESPONSE2                   0xFFC0381C      /* RSI Response Register */
  64 /* legacy register name (below) provided for backwards code compatibility */
  65 #define SDH_RESPONSE2                   RSI_RESPONSE2           /* SDH Response2 */
  66 #define RSI_RESPONSE3                   0xFFC03820              /* RSI Response Register */
  67 /* legacy register name (below) provided for backwards code compatibility */
  68 #define SDH_RESPONSE3                   RSI_RESPONSE3           /* SDH Response3 */
  69 #define RSI_DATA_TIMER                  0xFFC03824              /* RSI Data Timer Register */
  70 /* legacy register name (below) provided for backwards code compatibility */
  71 #define SDH_DATA_TIMER                  RSI_DATA_TIMER          /* SDH Data Timer */
  72 #define RSI_DATA_LGTH                   0xFFC03828              /* RSI Data Length Register */
  73 /* legacy register name (below) provided for backwards code compatibility */
  74 #define SDH_DATA_LGTH                   RSI_DATA_LGTH           /* SDH Data Length */
  75 #define RSI_DATA_CONTROL                0xFFC0382C              /* RSI Data Control Register */
  76 /* legacy register name (below) provided for backwards code compatibility */
  77 #define SDH_DATA_CTL                    RSI_DATA_CONTROL        /* SDH Data Control */
  78 #define RSI_DATA_CNT                    0xFFC03830              /* RSI Data Counter Register */
  79 /* legacy register name (below) provided for backwards code compatibility */
  80 #define SDH_DATA_CNT                    RSI_DATA_CNT            /* SDH Data Counter */
  81 #define RSI_STATUS                      0xFFC03834              /* RSI Status Register */
  82 /* legacy register name (below) provided for backwards code compatibility */
  83 #define SDH_STATUS                      RSI_STATUS              /* SDH Status */
  84 #define RSI_STATUSCL                    0xFFC03838              /* RSI Status Clear Register */
  85 /* legacy register name (below) provided for backwards code compatibility */
  86 #define SDH_STATUS_CLR                  RSI_STATUSCL            /* SDH Status Clear */
  87 #define RSI_MASK0                               0xFFC0383C              /* RSI Interrupt 0 Mask Register */
  88 /* legacy register name (below) provided for backwards code compatibility */
  89 #define SDH_MASK0                       RSI_MASK0               /* SDH Interrupt0 Mask */
  90 #define RSI_MASK1                               0xFFC03840              /* RSI Interrupt 1 Mask Register */
  91 /* legacy register name (below) provided for backwards code compatibility */
  92 #define SDH_MASK1                       RSI_MASK1               /* SDH Interrupt1 Mask */
  93 #define RSI_FIFO_CNT                    0xFFC03848              /* RSI FIFO Counter Register */
  94 /* legacy register name (below) provided for backwards code compatibility */
  95 #define SDH_FIFO_CNT                    RSI_FIFO_CNT            /* SDH FIFO Counter */
  96 #define RSI_CEATA_CONTROL               0xFFC0384C              /* RSI CEATA Register */
  97 #define RSI_FIFO                                0xFFC03880              /* RSI Data FIFO Register */
  98 /* legacy register name (below) provided for backwards code compatibility */
  99 #define SDH_FIFO                        RSI_FIFO                /* SDH Data FIFO */
 100 #define RSI_ESTAT                               0xFFC038C0              /* RSI Exception Status Register */
 101 /* legacy register name (below) provided for backwards code compatibility */
 102 #define SDH_E_STATUS                    RSI_ESTAT               /* SDH Exception Status */
 103 #define RSI_EMASK                               0xFFC038C4              /* RSI Exception Mask Register */
 104 /* legacy register name (below) provided for backwards code compatibility */
 105 #define SDH_E_MASK                      RSI_EMASK               /* SDH Exception Mask */
 106 #define RSI_CONFIG                      0xFFC038C8              /* RSI Configuration Register */
 107 /* legacy register name (below) provided for backwards code compatibility */
 108 #define SDH_CFG                                 RSI_CONFIG              /* SDH Configuration */
 109 #define RSI_RD_WAIT_EN                  0xFFC038CC              /* RSI Read Wait Enable Register */
 110 /* legacy register name (below) provided for backwards code compatibility */
 111 #define SDH_RD_WAIT_EN                  RSI_RD_WAIT_EN          /* SDH Read Wait Enable */
 112 #define RSI_PID0                                0xFFC038D0              /* RSI Peripheral ID Register 0 */
 113 /* legacy register name (below) provided for backwards code compatibility */
 114 #define SDH_PID0                        RSI_PID0                /* SDH Peripheral Identification0 */
 115 #define RSI_PID1                                0xFFC038D4              /* RSI Peripheral ID Register 1 */
 116 /* legacy register name (below) provided for backwards code compatibility */
 117 #define SDH_PID1                        RSI_PID1                /* SDH Peripheral Identification1 */
 118 #define RSI_PID2                                0xFFC038D8              /* RSI Peripheral ID Register 2 */
 119 /* legacy register name (below) provided for backwards code compatibility */
 120 #define SDH_PID2                        RSI_PID2                /* SDH Peripheral Identification2 */
 121 #define RSI_PID3                                0xFFC038DC              /* RSI Peripheral ID Register 3 */
 122 /* legacy register name (below) provided for backwards code compatibility */
 123 #define SDH_PID3                        RSI_PID3                /* SDH Peripheral Identification3 */
 124 /* RSI Registers */
 125
 126
 127
 128 /* ********************************************************** */
 129 /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
 130 /*     and MULTI BIT READ MACROS                              */
 131 /* ********************************************************** */
 132
 133 /* Bit masks for RSI_PWR_CONTROL */
 134 #define                    PWR_ON  0x3                  /* Power On */
 135 #define                RSI_CMD_OD  0x40                 /* Open Drain Output */
 136 /* legacy bit mask (below) provided for backwards code compatibility */
 137 #define                 SD_CMD_OD  RSI_CMD_OD           /* Open Drain Output */
 138 /* legacy bit mask (below) provided for backwards code compatibility */
 139 #define                nSD_CMD_OD  0x0
 140 /* legacy bit mask (below) provided for backwards code compatibility */
 141 #if 0
 142 #define                       TBD  0x3c                 /* TBD */
 143 #endif
 144 /* legacy bit mask (below) provided for backwards code compatibility */
 145 #define                   ROD_CTL  0x80
 146 /* legacy bit mask (below) provided for backwards code compatibility */
 147 #define                  nROD_CTL  0x80
 148
 149
 150 /* Bit masks for RSI_CLK_CONTROL */
 151 #define                    CLKDIV  0xff                 /* MC_CLK Divisor */
 152 #define                    CLK_EN  0x100                /* MC_CLK Bus Clock Enable */
 153 /* legacy bit mask (below) provided for backwards code compatibility */
 154 #define                     CLK_E  CLK_EN               /* MC_CLK Bus Clock Enable */
 155 /* legacy bit mask (below) provided for backwards code compatibility */
 156 #define                    nCLK_E  0x0
 157 #define                 PWR_SV_EN  0x200                /* Power Save Enable */
 158 /* legacy bit mask (below) provided for backwards code compatibility */
 159 #define                  PWR_SV_E  PWR_SV_EN            /* Power Save Enable */
 160 /* legacy bit mask (below) provided for backwards code compatibility */
 161 #define                 nPWR_SV_E  0x0
 162 #define             CLKDIV_BYPASS  0x400                /* Bypass Divisor */
 163 /* legacy bit mask (below) provided for backwards code compatibility */
 164 #define            nCLKDIV_BYPASS  0x0
 165 #define                  BUS_MODE  0x1800           /* Bus width selection */
 166 /* legacy bit mask (below) provided for backwards code compatibility */
 167 #define                  WIDE_BUS  0x0800       /* Wide Bus Mode Enable */
 168 /* legacy bit mask (below) provided for backwards code compatibility */
 169 #define                 nWIDE_BUS  0x0
 170
 171
 172 /* Bit masks for RSI_COMMAND */
 173 #define                   CMD_IDX  0x3f                 /* Command Index */
 174 #define                CMD_RSP_EN  0x40                 /* Response */
 175 /* legacy bit mask (below) provided for backwards code compatibility */
 176 #define                   CMD_RSP  CMD_RSP_EN           /* Response */
 177 /* legacy bit mask (below) provided for backwards code compatibility */
 178 #define                  nCMD_RSP  0x0
 179 #define               CMD_LRSP_EN  0x80                 /* Long Response */
 180 /* legacy bit mask (below) provided for backwards code compatibility */
 181 #define                 CMD_L_RSP  CMD_LRSP_EN          /* Long Response */
 182 /* legacy bit mask (below) provided for backwards code compatibility */
 183 #define                nCMD_L_RSP  0x0
 184 #define                CMD_INT_EN  0x100                /* Command Interrupt */
 185 /* legacy bit mask (below) provided for backwards code compatibility */
 186 #define                 CMD_INT_E  CMD_INT_EN           /* Command Interrupt */
 187 /* legacy bit mask (below) provided for backwards code compatibility */
 188 #define                nCMD_INT_E  0x0
 189 #define               CMD_PEND_EN  0x200                /* Command Pending */
 190 /* legacy bit mask (below) provided for backwards code compatibility */
 191 #define                CMD_PEND_E  CMD_PEND_EN          /* Command Pending */
 192 /* legacy bit mask (below) provided for backwards code compatibility */
 193 #define               nCMD_PEND_E  0x0
 194 #define                    CMD_EN  0x400                        /* Command Enable */
 195 /* legacy bit mask (below) provided for backwards code compatibility */
 196 #define                     CMD_E  CMD_EN               /* Command Enable */
 197 /* legacy bit mask (below) provided for backwards code compatibility */
 198 #define                    nCMD_E  0x0
 199
 200
 201 /* Bit masks for RSI_RESP_CMD */
 202 #define                  RESP_CMD  0x3f                 /* Response Command */
 203
 204 /* Bit masks for RSI_DATA_LGTH */
 205 #define               DATA_LENGTH  0xffff               /* Data Length */
 206
 207
 208 /* Bit masks for RSI_DATA_CONTROL */
 209 #define                   DATA_EN  0x1                  /* Data Transfer Enable */
 210 /* legacy bit mask (below) provided for backwards code compatibility */
 211 #define                     DTX_E  DATA_EN              /* Data Transfer Enable */
 212 /* legacy bit mask (below) provided for backwards code compatibility */
 213 #define                    nDTX_E  0x0
 214 #define                  DATA_DIR  0x2                  /* Data Transfer Direction */
 215 /* legacy bit mask (below) provided for backwards code compatibility */
 216 #define                   DTX_DIR  DATA_DIR             /* Data Transfer Direction */
 217 /* legacy bit mask (below) provided for backwards code compatibility */
 218 #define                  nDTX_DIR  0x0
 219 #define                 DATA_MODE  0x4                  /* Data Transfer Mode */
 220 /* legacy bit mask (below) provided for backwards code compatibility */
 221 #define                  DTX_MODE  DATA_MODE            /* Data Transfer Mode */
 222 /* legacy bit mask (below) provided for backwards code compatibility */
 223 #define                 nDTX_MODE  0x0
 224 #define               DATA_DMA_EN  0x8                  /* Data Transfer DMA Enable */
 225 /* legacy bit mask (below) provided for backwards code compatibility */
 226 #define                 DTX_DMA_E  0x8                  /* Data Transfer DMA Enable */
 227 /* legacy bit mask (below) provided for backwards code compatibility */
 228 #define                nDTX_DMA_E  0x0
 229 #define             DATA_BLK_LGTH  0xf0                 /* Data Transfer Block Length */
 230 /* legacy bit mask (below) provided for backwards code compatibility */
 231 #define              DTX_BLK_LGTH  0xf0                 /* Data Transfer Block Length */
 232 #define                              CEATA_EN  0x100          /* CE-ATA operation mode enable */
 233 #define                          CEATA_CCS_EN  0x200          /* CE-ATA CCS mode enable */
 234
 235 /* Bit masks for RSI_DATA_CNT */
 236 #define               DATA_COUNT  0xffff                /* Data Count */
 237
 238 /* Bit masks for RSI_STATUS */
 239 #define              CMD_CRC_FAIL  0x1                  /* CMD CRC Fail */
 240 /* legacy bit mask (below) provided for backwards code compatibility */
 241 #define             nCMD_CRC_FAIL  0x0
 242 #define              DAT_CRC_FAIL  0x2                  /* Data CRC Fail */
 243 /* legacy bit mask (below) provided for backwards code compatibility */
 244 #define             nDAT_CRC_FAIL  0x0
 245 #define               CMD_TIMEOUT  0x4                  /* CMD Time Out */
 246 /* legacy bit mask (below) provided for backwards code compatibility */
 247 #define              nCMD_TIMEOUT  0x0
 248 #define               DAT_TIMEOUT  0x8                  /* Data Time Out */
 249 /* legacy bit mask (below) provided for backwards code compatibility */
 250 #define              nDAT_TIMEOUT  0x0
 251 #define               TX_UNDERRUN  0x10                 /* Transmit Underrun */
 252 /* legacy bit mask (below) provided for backwards code compatibility */
 253 #define              nTX_UNDERRUN  0x0
 254 #define                RX_OVERRUN  0x20                 /* Receive Overrun */
 255 /* legacy bit mask (below) provided for backwards code compatibility */
 256 #define               nRX_OVERRUN  0x0
 257 #define              CMD_RESP_END  0x40                 /* CMD Response End */
 258 /* legacy bit mask (below) provided for backwards code compatibility */
 259 #define             nCMD_RESP_END  0x0
 260 #define                  CMD_SENT  0x80                 /* CMD Sent */
 261 /* legacy bit mask (below) provided for backwards code compatibility */
 262 #define                 nCMD_SENT  0x0
 263 #define                   DAT_END  0x100                /* Data End */
 264 /* legacy bit mask (below) provided for backwards code compatibility */
 265 #define                  nDAT_END  0x0
 266 #define             START_BIT_ERR  0x200                /* Start Bit Error */
 267 /* legacy bit mask (below) provided for backwards code compatibility */
 268 #define            nSTART_BIT_ERR  0x0
 269 #define               DAT_BLK_END  0x400                /* Data Block End */
 270 /* legacy bit mask (below) provided for backwards code compatibility */
 271 #define              nDAT_BLK_END  0x0
 272 #define                   CMD_ACT  0x800                /* CMD Active */
 273 /* legacy bit mask (below) provided for backwards code compatibility */
 274 #define                  nCMD_ACT  0x0
 275 #define                    TX_ACT  0x1000               /* Transmit Active */
 276 /* legacy bit mask (below) provided for backwards code compatibility */
 277 #define                   nTX_ACT  0x0
 278 #define                    RX_ACT  0x2000               /* Receive Active */
 279 /* legacy bit mask (below) provided for backwards code compatibility */
 280 #define                   nRX_ACT  0x0
 281 #define              TX_FIFO_STAT  0x4000               /* Transmit FIFO Status */
 282 /* legacy bit mask (below) provided for backwards code compatibility */
 283 #define             nTX_FIFO_STAT  0x0
 284 #define              RX_FIFO_STAT  0x8000               /* Receive FIFO Status */
 285 /* legacy bit mask (below) provided for backwards code compatibility */
 286 #define             nRX_FIFO_STAT  0x0
 287 #define              TX_FIFO_FULL  0x10000              /* Transmit FIFO Full */
 288 /* legacy bit mask (below) provided for backwards code compatibility */
 289 #define             nTX_FIFO_FULL  0x0
 290 #define              RX_FIFO_FULL  0x20000              /* Receive FIFO Full */
 291 /* legacy bit mask (below) provided for backwards code compatibility */
 292 #define             nRX_FIFO_FULL  0x0
 293 #define              TX_FIFO_ZERO  0x40000              /* Transmit FIFO Empty */
 294 /* legacy bit mask (below) provided for backwards code compatibility */
 295 #define             nTX_FIFO_ZERO  0x0
 296 #define               RX_DAT_ZERO  0x80000              /* Receive FIFO Empty */
 297 /* legacy bit mask (below) provided for backwards code compatibility */
 298 #define              nRX_DAT_ZERO  0x0
 299 #define                TX_DAT_RDY  0x100000             /* Transmit Data Available */
 300 /* legacy bit mask (below) provided for backwards code compatibility */
 301 #define               nTX_DAT_RDY  0x0
 302 #define               RX_FIFO_RDY  0x200000             /* Receive Data Available */
 303 /* legacy bit mask (below) provided for backwards code compatibility */
 304 #define              nRX_FIFO_RDY  0x0
 305
 306 /* Bit masks for RSI_STATCL */
 307 #define         CMD_CRC_FAIL_STAT  0x1                  /* CMD CRC Fail Status */
 308 /* legacy bit mask (below) provided for backwards code compatibility */
 309 #define        nCMD_CRC_FAIL_STAT  0x0
 310 #define         DAT_CRC_FAIL_STAT  0x2                  /* Data CRC Fail Status */
 311 /* legacy bit mask (below) provided for backwards code compatibility */
 312 #define        nDAT_CRC_FAIL_STAT  0x0
 313 #define          CMD_TIMEOUT_STAT  0x4                  /* CMD Time Out Status */
 314 /* legacy bit mask (below) provided for backwards code compatibility */
 315 #define         nCMD_TIMEOUT_STAT  0x0
 316 #define          DAT_TIMEOUT_STAT  0x8                  /* Data Time Out status */
 317 /* legacy bit mask (below) provided for backwards code compatibility */
 318 #define         nDAT_TIMEOUT_STAT  0x0
 319 #define          TX_UNDERRUN_STAT  0x10                 /* Transmit Underrun Status */
 320 /* legacy bit mask (below) provided for backwards code compatibility */
 321 #define         nTX_UNDERRUN_STAT  0x0
 322 #define           RX_OVERRUN_STAT  0x20                 /* Receive Overrun Status */
 323 /* legacy bit mask (below) provided for backwards code compatibility */
 324 #define          nRX_OVERRUN_STAT  0x0
 325 #define         CMD_RESP_END_STAT  0x40                 /* CMD Response End Status */
 326 /* legacy bit mask (below) provided for backwards code compatibility */
 327 #define        nCMD_RESP_END_STAT  0x0
 328 #define             CMD_SENT_STAT  0x80                 /* CMD Sent Status */
 329 /* legacy bit mask (below) provided for backwards code compatibility */
 330 #define            nCMD_SENT_STAT  0x0
 331 #define              DAT_END_STAT  0x100                /* Data End Status */
 332 /* legacy bit mask (below) provided for backwards code compatibility */
 333 #define             nDAT_END_STAT  0x0
 334 #define        START_BIT_ERR_STAT  0x200                /* Start Bit Error Status */
 335 /* legacy bit mask (below) provided for backwards code compatibility */
 336 #define       nSTART_BIT_ERR_STAT  0x0
 337 #define          DAT_BLK_END_STAT  0x400                /* Data Block End Status */
 338 /* legacy bit mask (below) provided for backwards code compatibility */
 339 #define         nDAT_BLK_END_STAT  0x0
 340
 341 /* Bit masks for RSI_MASKx */
 342 #define         CMD_CRC_FAIL_MASK  0x1                  /* CMD CRC Fail Mask */
 343 /* legacy bit mask (below) provided for backwards code compatibility */
 344 #define        nCMD_CRC_FAIL_MASK  0x0
 345 #define         DAT_CRC_FAIL_MASK  0x2                  /* Data CRC Fail Mask */
 346 /* legacy bit mask (below) provided for backwards code compatibility */
 347 #define        nDAT_CRC_FAIL_MASK  0x0
 348 #define          CMD_TIMEOUT_MASK  0x4                  /* CMD Time Out Mask */
 349 /* legacy bit mask (below) provided for backwards code compatibility */
 350 #define         nCMD_TIMEOUT_MASK  0x0
 351 #define          DAT_TIMEOUT_MASK  0x8                  /* Data Time Out Mask */
 352 /* legacy bit mask (below) provided for backwards code compatibility */
 353 #define         nDAT_TIMEOUT_MASK  0x0
 354 #define          TX_UNDERRUN_MASK  0x10                 /* Transmit Underrun Mask */
 355 /* legacy bit mask (below) provided for backwards code compatibility */
 356 #define         nTX_UNDERRUN_MASK  0x0
 357 #define           RX_OVERRUN_MASK  0x20                 /* Receive Overrun Mask */
 358 /* legacy bit mask (below) provided for backwards code compatibility */
 359 #define          nRX_OVERRUN_MASK  0x0
 360 #define         CMD_RESP_END_MASK  0x40                 /* CMD Response End Mask */
 361 /* legacy bit mask (below) provided for backwards code compatibility */
 362 #define        nCMD_RESP_END_MASK  0x0
 363 #define             CMD_SENT_MASK  0x80                 /* CMD Sent Mask */
 364 /* legacy bit mask (below) provided for backwards code compatibility */
 365 #define            nCMD_SENT_MASK  0x0
 366 #define              DAT_END_MASK  0x100                /* Data End Mask */
 367 /* legacy bit mask (below) provided for backwards code compatibility */
 368 #define             nDAT_END_MASK  0x0
 369 #define        START_BIT_ERR_MASK  0x200                /* Start Bit Error Mask */
 370 /* legacy bit mask (below) provided for backwards code compatibility */
 371 #define       nSTART_BIT_ERR_MASK  0x0
 372 #define          DAT_BLK_END_MASK  0x400                /* Data Block End Mask */
 373 /* legacy bit mask (below) provided for backwards code compatibility */
 374 #define         nDAT_BLK_END_MASK  0x0
 375 #define              CMD_ACT_MASK  0x800                /* CMD Active Mask */
 376 /* legacy bit mask (below) provided for backwards code compatibility */
 377 #define             nCMD_ACT_MASK  0x0
 378 #define               TX_ACT_MASK  0x1000               /* Transmit Active Mask */
 379 /* legacy bit mask (below) provided for backwards code compatibility */
 380 #define              nTX_ACT_MASK  0x0
 381 #define               RX_ACT_MASK  0x2000               /* Receive Active Mask */
 382 /* legacy bit mask (below) provided for backwards code compatibility */
 383 #define              nRX_ACT_MASK  0x0
 384 #define         TX_FIFO_STAT_MASK  0x4000               /* Transmit FIFO Status Mask */
 385 /* legacy bit mask (below) provided for backwards code compatibility */
 386 #define        nTX_FIFO_STAT_MASK  0x0
 387 #define         RX_FIFO_STAT_MASK  0x8000               /* Receive FIFO Status Mask */
 388 /* legacy bit mask (below) provided for backwards code compatibility */
 389 #define        nRX_FIFO_STAT_MASK  0x0
 390 #define         TX_FIFO_FULL_MASK  0x10000              /* Transmit FIFO Full Mask */
 391 /* legacy bit mask (below) provided for backwards code compatibility */
 392 #define        nTX_FIFO_FULL_MASK  0x0
 393 #define         RX_FIFO_FULL_MASK  0x20000              /* Receive FIFO Full Mask */
 394 /* legacy bit mask (below) provided for backwards code compatibility */
 395 #define        nRX_FIFO_FULL_MASK  0x0
 396 #define         TX_FIFO_ZERO_MASK  0x40000              /* Transmit FIFO Empty Mask */
 397 /* legacy bit mask (below) provided for backwards code compatibility */
 398 #define        nTX_FIFO_ZERO_MASK  0x0
 399 #define          RX_DAT_ZERO_MASK  0x80000              /* Receive FIFO Empty Mask */
 400 /* legacy bit mask (below) provided for backwards code compatibility */
 401 #define         nRX_DAT_ZERO_MASK  0x0
 402 #define           TX_DAT_RDY_MASK  0x100000             /* Transmit Data Available Mask */
 403 /* legacy bit mask (below) provided for backwards code compatibility */
 404 #define          nTX_DAT_RDY_MASK  0x0
 405 #define          RX_FIFO_RDY_MASK  0x200000             /* Receive Data Available Mask */
 406 /* legacy bit mask (below) provided for backwards code compatibility */
 407 #define         nRX_FIFO_RDY_MASK  0x0
 408
 409 /* Bit masks for RSI_FIFO_CNT */
 410 #define                FIFO_COUNT  0x7fff               /* FIFO Count */
 411
 412 /* Bit masks for RSI_CEATA_CONTROL */
 413 #define           CEATA_TX_CCSD  0x1                    /* Send CE-ATA CCSD sequence */
 414
 415 /* Bit masks for RSI_ESTAT */
 416 #define              SDIO_INT_DET  0x2                  /* SDIO Int Detected */
 417 /* legacy bit mask (below) provided for backwards code compatibility */
 418 #define             nSDIO_INT_DET  0x0
 419 #define               SD_CARD_DET  0x10                 /* SD Card Detect */
 420 /* legacy bit mask (below) provided for backwards code compatibility */
 421 #define              nSD_CARD_DET  0x0
 422 #define             CEATA_INT_DET  0x20
 423
 424 /* Bit masks for RSI_EMASK */
 425 #define         SDIO_INT_DET_MASK  0x2                /* Mask SDIO Int Detected */
 426 /* legacy bit mask (below) provided for backwards code compatibility */
 427 #define                  SDIO_MSK  SDIO_INT_DET_MASK  /* Mask SDIO Int Detected */
 428 /* legacy bit mask (below) provided for backwards code compatibility */
 429 #define                 nSDIO_MSK  0x0
 430 #define          SD_CARD_DET_MASK  0x10               /* Mask Card Detect */
 431 /* legacy bit mask (below) provided for backwards code compatibility */
 432 #define                  SCD_MASK  SD_CARD_DET_MASK   /* Mask Card Detect */
 433 /* legacy bit mask (below) provided for backwards code compatibility */
 434 #define                  nSCD_MSK  0x0
 435 #define        CEATA_INT_DET_MASK  0x20
 436
 437
 438 /* Bit masks for RSI_CFG */
 439 /* Left in for backwards compatibility */
 440 #define                RSI_CLK_EN  0x1
 441 /* legacy bit mask (below) provided for backwards code compatibility */
 442 #define                   CLKS_EN  RSI_CLK_EN           /* Clocks Enable */
 443 /* legacy bit mask (below) provided for backwards code compatibility */
 444 #define                  nCLKS_EN  0x0
 445 #define                  SDIO4_EN  0x4                  /* SDIO 4-Bit Enable */
 446 /* legacy bit mask (below) provided for backwards code compatibility */
 447 #define                      SD4E  SDIO4_EN             /* SDIO 4-Bit Enable */
 448 /* legacy bit mask (below) provided for backwards code compatibility */
 449 #define                     nSD4E  0x0
 450 #define                     MW_EN  0x8                  /* Moving Window Enable */
 451 /* legacy bit mask (below) provided for backwards code compatibility */
 452 #define                       MWE  MW_EN                /* Moving Window Enable */
 453 /* legacy bit mask (below) provided for backwards code compatibility */
 454 #define                      nMWE  0x0
 455 #define                   RSI_RST  0x10                 /* SDMMC Reset */
 456 /* legacy bit mask (below) provided for backwards code compatibility */
 457 #define                    SD_RST  RSI_RST              /* SDMMC Reset */
 458 /* legacy bit mask (below) provided for backwards code compatibility */
 459 #define                   nSD_RST  0x0
 460 #define                    PU_DAT  0x20                 /* Pull-up SD_DAT */
 461 /* legacy bit mask (below) provided for backwards code compatibility */
 462 #define                 PUP_SDDAT  PU_DAT               /* Pull-up SD_DAT */
 463 /* legacy bit mask (below) provided for backwards code compatibility */
 464 #define                nPUP_SDDAT  0x0
 465 #define                   PU_DAT3  0x40                 /* Pull-up SD_DAT3 */
 466 /* legacy bit mask (below) provided for backwards code compatibility */
 467 #define                PUP_SDDAT3  PU_DAT3              /* Pull-up SD_DAT3 */
 468 /* legacy bit mask (below) provided for backwards code compatibility */
 469 #define               nPUP_SDDAT3  0x0
 470 #define                   PD_DAT3  0x80                 /* Pull-down SD_DAT3 */
 471 /* legacy bit mask (below) provided for backwards code compatibility */
 472 #define                 PD_SDDAT3  PD_DAT3              /* Pull-down SD_DAT3 */
 473 /* legacy bit mask (below) provided for backwards code compatibility */
 474 #define                nPD_SDDAT3  0x0
 475
 476
 477 /* Bit masks for RSI_RD_WAIT_EN */
 478 #define                  SDIO_RWR  0x1                  /* Read Wait Request */
 479 /* legacy bit mask (below) provided for backwards code compatibility */
 480 #define                       RWR  SDIO_RWR             /* Read Wait Request */
 481 /* legacy bit mask (below) provided for backwards code compatibility */
 482 #define                      nRWR  0x0
 483
 484 /* Bit masks for RSI_PIDx */
 485 #define                   RSI_PID  0xff                 /* RSI Peripheral ID */
 486 #ifdef _MISRA_RULES
 487 #pragma diag(pop)
 488 #endif /* _MISRA_RULES */
 489
 490 #endif /* _DEF_BF514_H */