[glibc.git] / sysdeps / powerpc / bits / fenv.h

/* Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   This file is part of the GNU C Library.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Library General Public License as
   published by the Free Software Foundation; either version 2 of the
   License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Library General Public License for more details.

   You should have received a copy of the GNU Library General Public
   License along with the GNU C Library; see the file COPYING.LIB.  If not,
   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#ifndef _FENV_H
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif


/* Define bits representing the exception.  We use the bit positions of
   the appropriate bits in the FPSCR...  */
enum
  {
    FE_INEXACT = 1 << (31 - 6),
#define FE_INEXACT	FE_INEXACT
    FE_DIVBYZERO = 1 << (31 - 5),
#define FE_DIVBYZERO	FE_DIVBYZERO
    FE_UNDERFLOW = 1 << (31 - 4),
#define FE_UNDERFLOW	FE_UNDERFLOW
    FE_OVERFLOW = 1 << (31 - 3),
#define FE_OVERFLOW	FE_OVERFLOW

    /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
       actually corresponds to bits 7 through 12 and 21 through 23
       in the FPSCR, but we can't use that because the current draft
       says that it must be a power of 2.  Instead we use bit 2 which
       is the summary bit for all the FE_INVALID exceptions, which
       kind of makes sense.  */
    FE_INVALID = 1 << (31 - 2),
#define FE_INVALID	FE_INVALID

#ifdef __USE_GNU
    /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
       input to a routine is equivalent to setting all of these bits;
       FE_INVALID will be set on output from a routine iff one of
       these bits is set.  Note, though, that you can't disable or
       enable these exceptions individually.  */

    /* Operation with SNaN. */
    FE_INVALID_SNAN = 1 << (31 - 7),
# define FE_INVALID_SNAN	FE_INVALID_SNAN

    /* Inf - Inf */
    FE_INVALID_ISI = 1 << (31 - 8),
# define FE_INVALID_ISI		FE_INVALID_ISI

    /* Inf / Inf */
    FE_INVALID_IDI = 1 << (31 - 9),
# define FE_INVALID_IDI		FE_INVALID_IDI

    /* 0 / 0 */
    FE_INVALID_ZDZ = 1 << (31 - 10),
# define FE_INVALID_ZDZ		FE_INVALID_ZDZ

    /* Inf * 0 */
    FE_INVALID_IMZ = 1 << (31 - 11),
# define FE_INVALID_IMZ		FE_INVALID_IMZ

    /* Comparison with NaN or SNaN.  */
    FE_INVALID_COMPARE = 1 << (31 - 12),
# define FE_INVALID_COMPARE	FE_INVALID_COMPARE

    /* Invalid operation flag for software (not set by hardware).  */
    /* Note that some chips don't have this implemented, presumably
       because no-one expected anyone to write software for them %-).  */
    FE_INVALID_SOFTWARE = 1 << (31 - 21),
# define FE_INVALID_SOFTWARE	FE_INVALID_SOFTWARE

    /* Square root of negative number (including -Inf).  */
    /* Note that some chips don't have this implemented.  */
    FE_INVALID_SQRT = 1 << (31 - 22),
# define FE_INVALID_SQRT	FE_INVALID_SQRT

    /* Conversion-to-integer of a NaN or a number too large or too small.  */
    FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23),
# define FE_INVALID_INTEGER_CONVERSION	FE_INVALID_INTEGER_CONVERSION

# define FE_ALL_INVALID \
        (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
	 | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
	 | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
#endif
  };

#define FE_ALL_EXCEPT \
	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)

/* PowerPC chips support all of the four defined rounding modes.  We
   use the bit pattern in the FPSCR as the values for the
   appropriate macros.  */
enum
  {
    FE_TONEAREST = 0,
#define FE_TONEAREST	FE_TONEAREST
    FE_TOWARDZERO = 1,
#define FE_TOWARDZERO	FE_TOWARDZERO
    FE_UPWARD = 2,
#define FE_UPWARD	FE_UPWARD
    FE_DOWNWARD = 3,
#define FE_DOWNWARD	FE_DOWNWARD
  };

/* Type representing exception flags.  */
typedef unsigned int fexcept_t;

/* Type representing floating-point environment.  We leave it as 'double'
   for efficiency reasons (rather than writing it to a 32-bit integer). */
typedef double fenv_t;

/* If the default argument is used we use this value.  */
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV	(&__fe_dfl_env)

#ifdef __USE_GNU
/* Floating-point environment where all exceptions are enabled.  Note that
   this is not sufficient to give you SIGFPE.  */
extern const fenv_t __fe_enabled_env;
# define FE_ENABLED_ENV	(&__fe_enabled_env)

/* Floating-point environment with (processor-dependent) non-IEEE floating
   point.  */
extern const fenv_t __fe_nonieee_env;
# define FE_NONIEEE_ENV	(&__fe_nonieee_env)

/* Floating-point environment with all exceptions enabled.  Note that
   just evaluating this value will set the processor into 'FPU
   exceptions imprecise recoverable' mode, which may cause a significant
   performance penalty (but have no other visible effect).  */
extern const fenv_t *__fe_nomask_env __P ((void));
# define FE_NOMASK_ENV	(__fe_nomask_env ())
#endif

#if defined __OPTIMIZE__ && !defined _SOFT_FLOAT
/* Inline definition for fegetround.  */
# define fegetround() \
  (__extension__  ({ int __fegetround_result;				      \
		     __asm__ ("mcrfs 7,7 ; mfcr %0"			      \
			     : "=r"(__fegetround_result) : : "cr7");	      \
		     __fegetround_result & 3; }))

/* Inline definition for feraiseexcept.  */
# define feraiseexcept(__excepts) \
  (__extension__ ({ if (__builtin_constant_p (__excepts)		      \
			&& ((__excepts) & -(__excepts)) == 0		      \
			&& (__excepts) != FE_INVALID) {			      \
		      if ((__excepts) != 0)				      \
			__asm__ __volatile__				      \
			  ("mtfsb1 %0"					      \
			   : : "i"(32 - __builtin_ffs (__excepts)));	      \
		    } else						      \
		      (feraiseexcept) (__excepts); }))

/* Inline definition for feclearexcept.  */
# define feclearexcept(__excepts) \
  (__extension__  ({ if (__builtin_constant_p (__excepts)		      \
			 && ((__excepts) & -(__excepts)) == 0		      \
			 && (__excepts) != FE_INVALID) {		      \
		       if ((__excepts) != 0)				      \
			 __asm__ __volatile__				      \
			   ("mtfsb0 %0"					      \
			    : : "i"(32 - __builtin_ffs (__excepts)));	      \
		     } else						      \
		       (feclearexcept) (__excepts); }))
#endif /* __OPTIMIZE__ && !_SOFT_FLOAT */
Commit	Line	Data
d111572f	1	/* Copyright (C) 1997, 1998 Free Software Foundation, Inc.
1f205a47 UD	2	This file is part of the GNU C Library.
	3
	4	The GNU C Library is free software; you can redistribute it and/or
	5	modify it under the terms of the GNU Library General Public License as
	6	published by the Free Software Foundation; either version 2 of the
	7	License, or (at your option) any later version.
	8
	9	The GNU C Library is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	Library General Public License for more details.
	13
	14	You should have received a copy of the GNU Library General Public
	15	License along with the GNU C Library; see the file COPYING.LIB. If not,
	16	write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
	17	Boston, MA 02111-1307, USA. */
	18
5107cf1d UD	19	#ifndef _FENV_H
	20	# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
	21	#endif
1f205a47	22
1f205a47 UD	23
	24	/* Define bits representing the exception. We use the bit positions of
	25	the appropriate bits in the FPSCR... */
	26	enum
	27	{
adac8450	28	FE_INEXACT = 1 << (31 - 6),
1f205a47	29	#define FE_INEXACT FE_INEXACT
adac8450	30	FE_DIVBYZERO = 1 << (31 - 5),
1f205a47	31	#define FE_DIVBYZERO FE_DIVBYZERO
adac8450	32	FE_UNDERFLOW = 1 << (31 - 4),
1f205a47	33	#define FE_UNDERFLOW FE_UNDERFLOW
adac8450	34	FE_OVERFLOW = 1 << (31 - 3),
1f205a47 UD	35	#define FE_OVERFLOW FE_OVERFLOW
	36
	37	/* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
	38	actually corresponds to bits 7 through 12 and 21 through 23
	39	in the FPSCR, but we can't use that because the current draft
0413b54c UD	40	says that it must be a power of 2. Instead we use bit 2 which
	41	is the summary bit for all the FE_INVALID exceptions, which
	42	kind of makes sense. */
adac8450	43	FE_INVALID = 1 << (31 - 2),
1f205a47 UD	44	#define FE_INVALID FE_INVALID
	45
	46	#ifdef __USE_GNU
	47	/* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
	48	input to a routine is equivalent to setting all of these bits;
	49	FE_INVALID will be set on output from a routine iff one of
	50	these bits is set. Note, though, that you can't disable or
	51	enable these exceptions individually. */
	52
	53	/* Operation with SNaN. */
adac8450	54	FE_INVALID_SNAN = 1 << (31 - 7),
f4017d20	55	# define FE_INVALID_SNAN FE_INVALID_SNAN
1f205a47 UD	56
1f205a47 UD	57	/* Inf - Inf */
adac8450	58	FE_INVALID_ISI = 1 << (31 - 8),
f4017d20	59	# define FE_INVALID_ISI FE_INVALID_ISI
1f205a47 UD	60
1f205a47 UD	61	/* Inf / Inf */
adac8450	62	FE_INVALID_IDI = 1 << (31 - 9),
f4017d20	63	# define FE_INVALID_IDI FE_INVALID_IDI
1f205a47 UD	64
1f205a47 UD	65	/* 0 / 0 */
adac8450	66	FE_INVALID_ZDZ = 1 << (31 - 10),
f4017d20	67	# define FE_INVALID_ZDZ FE_INVALID_ZDZ
1f205a47 UD	68
1f205a47 UD	69	/* Inf * 0 */
adac8450	70	FE_INVALID_IMZ = 1 << (31 - 11),
f4017d20	71	# define FE_INVALID_IMZ FE_INVALID_IMZ
1f205a47	72
0413b54c	73	/* Comparison with NaN or SNaN. */
adac8450	74	FE_INVALID_COMPARE = 1 << (31 - 12),
f4017d20	75	# define FE_INVALID_COMPARE FE_INVALID_COMPARE
1f205a47	76
0413b54c UD	77	/* Invalid operation flag for software (not set by hardware). */
	78	/* Note that some chips don't have this implemented, presumably
	79	because no-one expected anyone to write software for them %-). */
adac8450	80	FE_INVALID_SOFTWARE = 1 << (31 - 21),
f4017d20	81	# define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE
1f205a47	82
0413b54c UD	83	/* Square root of negative number (including -Inf). */
0413b54c UD	84	/* Note that some chips don't have this implemented. */
adac8450	85	FE_INVALID_SQRT = 1 << (31 - 22),
f4017d20	86	# define FE_INVALID_SQRT FE_INVALID_SQRT
1f205a47	87
0413b54c	88	/* Conversion-to-integer of a NaN or a number too large or too small. */
adac8450	89	FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23),
f4017d20	90	# define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION
1f205a47	91
f4017d20	92	# define FE_ALL_INVALID \
1f205a47 UD	93	(FE_INVALID_SNAN \| FE_INVALID_ISI \| FE_INVALID_IDI \| FE_INVALID_ZDZ \
	94	\| FE_INVALID_IMZ \| FE_INVALID_COMPARE \| FE_INVALID_SOFTWARE \
	95	\| FE_INVALID_SQRT \| FE_INVALID_INTEGER_CONVERSION)
	96	#endif
	97	};
	98
	99	#define FE_ALL_EXCEPT \
	100	(FE_INEXACT \| FE_DIVBYZERO \| FE_UNDERFLOW \| FE_OVERFLOW \| FE_INVALID)
	101
	102	/* PowerPC chips support all of the four defined rounding modes. We
	103	use the bit pattern in the FPSCR as the values for the
	104	appropriate macros. */
	105	enum
	106	{
	107	FE_TONEAREST = 0,
	108	#define FE_TONEAREST FE_TONEAREST
d111572f UD	109	FE_TOWARDZERO = 1,
d111572f UD	110	#define FE_TOWARDZERO FE_TOWARDZERO
1f205a47 UD	111	FE_UPWARD = 2,
	112	#define FE_UPWARD FE_UPWARD
	113	FE_DOWNWARD = 3,
	114	#define FE_DOWNWARD FE_DOWNWARD
	115	};
	116
	117	/* Type representing exception flags. */
	118	typedef unsigned int fexcept_t;
	119
	120	/* Type representing floating-point environment. We leave it as 'double'
	121	for efficiency reasons (rather than writing it to a 32-bit integer). */
	122	typedef double fenv_t;
	123
	124	/* If the default argument is used we use this value. */
	125	extern const fenv_t __fe_dfl_env;
55c14926	126	#define FE_DFL_ENV (&__fe_dfl_env)
1f205a47 UD	127
1f205a47 UD	128	#ifdef __USE_GNU
0413b54c UD	129	/* Floating-point environment where all exceptions are enabled. Note that
	130	this is not sufficient to give you SIGFPE. */
	131	extern const fenv_t __fe_enabled_env;
	132	# define FE_ENABLED_ENV (&__fe_enabled_env)
	133
	134	/* Floating-point environment with (processor-dependent) non-IEEE floating
	135	point. */
	136	extern const fenv_t __fe_nonieee_env;
	137	# define FE_NONIEEE_ENV (&__fe_nonieee_env)
	138
	139	/* Floating-point environment with all exceptions enabled. Note that
	140	just evaluating this value will set the processor into 'FPU
	141	exceptions imprecise recoverable' mode, which may cause a significant
	142	performance penalty (but have no other visible effect). */
	143	extern const fenv_t *__fe_nomask_env __P ((void));
	144	# define FE_NOMASK_ENV (__fe_nomask_env ())
1f205a47	145	#endif
0413b54c	146
af6f3906	147	#if defined __OPTIMIZE__ && !defined _SOFT_FLOAT
0413b54c UD	148	/* Inline definition for fegetround. */
	149	# define fegetround() \
	150	(__extension__ ({ int __fegetround_result; \
	151	__asm__ ("mcrfs 7,7 ; mfcr %0" \
	152	: "=r"(__fegetround_result) : : "cr7"); \
	153	__fegetround_result & 3; }))
	154
	155	/* Inline definition for feraiseexcept. */
	156	# define feraiseexcept(__excepts) \
	157	(__extension__ ({ if (__builtin_constant_p (__excepts) \
	158	&& ((__excepts) & -(__excepts)) == 0 \
	159	&& (__excepts) != FE_INVALID) { \
	160	if ((__excepts) != 0) \
	161	__asm__ __volatile__ \
	162	("mtfsb1 %0" \
	163	: : "i"(32 - __builtin_ffs (__excepts))); \
	164	} else \
	165	(feraiseexcept) (__excepts); }))
	166
	167	/* Inline definition for feclearexcept. */
	168	# define feclearexcept(__excepts) \
	169	(__extension__ ({ if (__builtin_constant_p (__excepts) \
	170	&& ((__excepts) & -(__excepts)) == 0 \
	171	&& (__excepts) != FE_INVALID) { \
	172	if ((__excepts) != 0) \
	173	__asm__ __volatile__ \
	174	("mtfsb0 %0" \
	175	: : "i"(32 - __builtin_ffs (__excepts))); \
	176	} else \
	177	(feclearexcept) (__excepts); }))
af6f3906	178	#endif /* __OPTIMIZE__ && !_SOFT_FLOAT */