[glibc.git] / ports / sysdeps / mips / mips64 / soft-fp / sfp-machine.h

#include <fenv.h>
#include <fpu_control.h>

#define _FP_W_TYPE_SIZE		64
#define _FP_W_TYPE		unsigned long long
#define _FP_WS_TYPE		signed long long
#define _FP_I_TYPE		long long

#define _FP_MUL_MEAT_S(R,X,Y)					\
  _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
#define _FP_MUL_MEAT_D(R,X,Y)					\
  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
#define _FP_MUL_MEAT_Q(R,X,Y)					\
  _FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)

#define _FP_MUL_MEAT_DW_S(R,X,Y)				\
  _FP_MUL_MEAT_DW_1_imm(_FP_WFRACBITS_S,R,X,Y)
#define _FP_MUL_MEAT_DW_D(R,X,Y)				\
  _FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
#define _FP_MUL_MEAT_DW_Q(R,X,Y)				\
  _FP_MUL_MEAT_DW_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)

#define _FP_DIV_MEAT_S(R,X,Y)	_FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
#define _FP_DIV_MEAT_D(R,X,Y)	_FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y)	_FP_DIV_MEAT_2_udiv(Q,R,X,Y)

#define _FP_NANFRAC_S		(_FP_QNANBIT_S - 1)
#define _FP_NANFRAC_D		(_FP_QNANBIT_D - 1)
#define _FP_NANFRAC_Q		(_FP_QNANBIT_Q - 1), -1
#define _FP_NANSIGN_S		0
#define _FP_NANSIGN_D		0
#define _FP_NANSIGN_Q		0

#define _FP_KEEPNANFRACP 1
#define _FP_QNANNEGATEDP 1

/* From my experiments it seems X is chosen unless one of the
   NaNs is sNaN,  in which case the result is NANSIGN/NANFRAC.  */
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
  do {								\
    if ((_FP_FRAC_HIGH_RAW_##fs(X) |				\
	 _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs)		\
      {								\
	R##_s = _FP_NANSIGN_##fs;				\
        _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs);			\
      }								\
    else							\
      {								\
	R##_s = X##_s;						\
        _FP_FRAC_COPY_##wc(R,X);				\
      }								\
    R##_c = FP_CLS_NAN;						\
  } while (0)

#define _FP_DECL_EX		fpu_control_t _fcw

#define FP_ROUNDMODE		(_fcw & 0x3)

#define FP_RND_NEAREST		FE_TONEAREST
#define FP_RND_ZERO		FE_TOWARDZERO
#define FP_RND_PINF		FE_UPWARD
#define FP_RND_MINF		FE_DOWNWARD

#define FP_EX_INVALID		FE_INVALID
#define FP_EX_OVERFLOW		FE_OVERFLOW
#define FP_EX_UNDERFLOW		FE_UNDERFLOW
#define FP_EX_DIVZERO		FE_DIVBYZERO
#define FP_EX_INEXACT		FE_INEXACT

#ifdef __mips_hard_float
#define FP_INIT_ROUNDMODE			\
do {						\
  _FPU_GETCW (_fcw);				\
} while (0)

#define FP_HANDLE_EXCEPTIONS			\
do {						\
  if (__builtin_expect (_fex, 0))		\
    _FPU_SETCW (_fcw | _fex | (_fex << 10));	\
} while (0)
#define FP_TRAPPING_EXCEPTIONS ((_fcw >> 5) & 0x7c)
#else
#define FP_INIT_ROUNDMODE	_fcw = FP_RND_NEAREST
#endif
Commit	Line	Data
384fa30d DJ	1	#include <fenv.h>
	2	#include <fpu_control.h>
	3
1db6393c	4	#define _FP_W_TYPE_SIZE 64
ca2b264c AO	5	#define _FP_W_TYPE unsigned long long
	6	#define _FP_WS_TYPE signed long long
	7	#define _FP_I_TYPE long long
1db6393c AJ	8
	9	#define _FP_MUL_MEAT_S(R,X,Y) \
	10	_FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
	11	#define _FP_MUL_MEAT_D(R,X,Y) \
	12	_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
	13	#define _FP_MUL_MEAT_Q(R,X,Y) \
	14	_FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
	15
77f01ab5 JM	16	#define _FP_MUL_MEAT_DW_S(R,X,Y) \
	17	_FP_MUL_MEAT_DW_1_imm(_FP_WFRACBITS_S,R,X,Y)
	18	#define _FP_MUL_MEAT_DW_D(R,X,Y) \
	19	_FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
	20	#define _FP_MUL_MEAT_DW_Q(R,X,Y) \
	21	_FP_MUL_MEAT_DW_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
	22
1db6393c AJ	23	#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
	24	#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
	25	#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
	26
2848b105 MR	27	#define _FP_NANFRAC_S (_FP_QNANBIT_S - 1)
	28	#define _FP_NANFRAC_D (_FP_QNANBIT_D - 1)
	29	#define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1
1db6393c AJ	30	#define _FP_NANSIGN_S 0
	31	#define _FP_NANSIGN_D 0
	32	#define _FP_NANSIGN_Q 0
	33
	34	#define _FP_KEEPNANFRACP 1
2848b105 MR	35	#define _FP_QNANNEGATEDP 1
2848b105 MR	36
1db6393c AJ	37	/* From my experiments it seems X is chosen unless one of the
	38	NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */
	39	#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
	40	do { \
	41	if ((_FP_FRAC_HIGH_RAW_##fs(X) \| \
	42	_FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \
	43	{ \
	44	R##_s = _FP_NANSIGN_##fs; \
	45	_FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \
	46	} \
	47	else \
	48	{ \
	49	R##_s = X##_s; \
	50	_FP_FRAC_COPY_##wc(R,X); \
	51	} \
	52	R##_c = FP_CLS_NAN; \
	53	} while (0)
	54
384fa30d DJ	55	#define _FP_DECL_EX fpu_control_t _fcw
	56
	57	#define FP_ROUNDMODE (_fcw & 0x3)
	58
	59	#define FP_RND_NEAREST FE_TONEAREST
	60	#define FP_RND_ZERO FE_TOWARDZERO
	61	#define FP_RND_PINF FE_UPWARD
	62	#define FP_RND_MINF FE_DOWNWARD
	63
	64	#define FP_EX_INVALID FE_INVALID
	65	#define FP_EX_OVERFLOW FE_OVERFLOW
	66	#define FP_EX_UNDERFLOW FE_UNDERFLOW
	67	#define FP_EX_DIVZERO FE_DIVBYZERO
	68	#define FP_EX_INEXACT FE_INEXACT
	69
	70	#ifdef __mips_hard_float
	71	#define FP_INIT_ROUNDMODE \
	72	do { \
	73	_FPU_GETCW (_fcw); \
	74	} while (0)
	75
	76	#define FP_HANDLE_EXCEPTIONS \
	77	do { \
	78	if (__builtin_expect (_fex, 0)) \
	79	_FPU_SETCW (_fcw \| _fex \| (_fex << 10)); \
	80	} while (0)
6334191e	81	#define FP_TRAPPING_EXCEPTIONS ((_fcw >> 5) & 0x7c)
384fa30d DJ	82	#else
	83	#define FP_INIT_ROUNDMODE _fcw = FP_RND_NEAREST
	84	#endif