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libgloss: bfin: sync headers to VDSP 5.0 Update 8
[newlib-cygwin.git] / libgloss / bfin / include / defblackfin.h
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84132c9d
JJ		 1/*
2 * The authors hereby grant permission to use, copy, modify, distribute,
3 * and license this software and its documentation for any purpose, provided
4 * that existing copyright notices are retained in all copies and that this
5 * notice is included verbatim in any distributions. No written agreement,
6 * license, or royalty fee is required for any of the authorized uses.
7 * Modifications to this software may be copyrighted by their authors
8 * and need not follow the licensing terms described here, provided that
9 * the new terms are clearly indicated on the first page of each file where
10 * they apply.
11 */
12
13/************************************************************************
14 *
15 * defblackfin.h
16 *
1cfc2fea 17 * (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
84132c9d
JJ		 18 *
19 ************************************************************************/
20
21/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
22
23#ifndef _DEF_BLACKFIN_H
24#define _DEF_BLACKFIN_H
25
26#ifdef _MISRA_RULES
27#pragma diag(push)
28#pragma diag(suppress:misra_rule_19_4)
29#pragma diag(suppress:misra_rule_19_7)
30#endif /* _MISRA_RULES */
31
32
33#if defined(__ADSPLPBLACKFIN__)
34#warning defblackfin.h should only be included for 535 compatible chips.
35#endif
4834826e
JJ		 36/* Macro parameters should be enclosed in parentheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
37#ifdef _MISRA_RULES
38#define MK_BMSK_( x ) (1ul<<(x)) /* Make a bit mask from a bit position */
39#else
84132c9d 40#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
4834826e 41#endif /* _MISRA_RULES */
84132c9d
JJ		 42
43/*********************************************************************************** */
44/* System Register Bits */
45/*********************************************************************************** */
46
47/*************************************************** */
48/* ASTAT register */
49/*************************************************** */
50
51#if !defined(__ADSPLPBLACKFIN__)
52/* ** Bit Positions */
53#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
54#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
55#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
56#define ASTAT_V_COPY_P 0x00000003 /* Result of last DAG operation overflowed */
57#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
58#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
59#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
60
61#else /* !__ADSPLPBLACKFIN__ */
62
63/* definitions of ASTAT bit positions for next revision of BLACKFIN */
64#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
65#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
66#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
67#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
68#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
69#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
70#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
71#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
72#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0_P */
73#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
74#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1_P */
75#define ASTAT_V_P 0x00000018 /* Result of last op written to data register file. */
76#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V_P */
77#endif /* !__ADSPLPBLACKFIN__ */
78
79/* ** Masks */
80#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
81#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
82#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
83#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
84#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
85
86#if !defined(__ADSPLPBLACKFIN__)
87
88#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
89#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Result of last DAG operation overflowed */
90
91#else /* !__ADSPLPBLACKFIN__ */
92
93#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
94#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
95#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
96#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU1 operation generated a carry */
97#define ASTAT_AV0S MK_BMSK_(ASTAT_AV0S_P) /* Sticky version of ASTAT_AV0_P */
98#define ASTAT_AV1S MK_BMSK_(ASTAT_AV1S_P) /* Sticky version of ASTAT_AV1_P */
99#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Result of last op written to data register file. */
100#define ASTAT_VS MK_BMSK_(ASTAT_VS_P) /* Sticky version of ASTAT_V_P */
101
102#endif /* !__ADSPLPBLACKFIN__ */
103
104/*************************************************** */
105/* SEQSTAT register */
106/*************************************************** */
107
108/* ** Bit Positions */
109#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
110#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
111#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
112#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
113#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
114#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
115#define SEQSTAT_OMODE0_P 0x0000000A /* Operating mode: 00 user, 01 supervisor, 1x debug */
116#define SEQSTAT_OMODE1_P 0x0000000B /* Operating mode: 00 user, 01 supervisor, 1x debug */
117#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
118#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
119#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
120#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
121#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
122#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
123#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
124
125/* ** Masks */
126/* Exception cause */
127#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
128 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
129 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
130 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
131 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
132 MK_BMSK_(SEQSTAT_EXCAUSE5_P) )
133
134/* Operating mode: 00 user, 01 supervisor, 1x debug */
135#define SEQSTAT_OMODE ( MK_BMSK_(SEQSTAT_OMODE0_P) | \
136 MK_BMSK_(SEQSTAT_OMODE1_P) )
137
138/* Pending idle mode request, set by IDLE instruction */
139#define SEQSTAT_IDLE_REQ MK_BMSK_(SEQSTAT_IDLE_REQ_P)
140
141/* Indicates whether the last reset was a software reset (=1) */
142#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P)
143
144/* Last hw error cause */
145#define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
146 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
147 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
148 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
149 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) )
150
151/*************************************************** */
152/* SYSCFG register */
153/*************************************************** */
154
155/* ** Bit Positions */
156#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
157#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
158#define SYSCFG_SNEN_P 0x00000002 /* Enable self-nesting interrupts (=1) */
159
160/* ** Masks */
161#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */
162#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */
163#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Enable self-nesting interrupts (=1) */
164/* Backward-compatibility for typos in prior releases */
165#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
166#define SYSCFG_CCCEN SYSCFG_CCEN
167
168
169/*********************************************************************************** */
170/* Core MMR Register Map */
171/*********************************************************************************** */
172
173/* Cache & SRAM Memory */
174#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address (Read Only) */
175#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
176#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
177#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
178#define MMR_TIMEOUT 0xFFE00010 /* Memory-Mapped Register Timeout Register */
179#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
180#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
181#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
182#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
183#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
184#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
185#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
186#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
187#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
188#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
189#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
190#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
191#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
192#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
193#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
194#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
195#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
196#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
197#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
198#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
199#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
200#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
201#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
202#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
203#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
204#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
205#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
206#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
207#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
208#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
209#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
210#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
211#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
212#define DTEST_INDEX 0xFFE00304 /* Data Test Index Register */
213#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
214#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
215#define DTEST_DATA2 0xFFE00408 /* Data Test Data Register */
216#define DTEST_DATA3 0xFFE0040C /* Data Test Data Register */
217#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
218#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
219#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
220#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cache Protection Lookaside Buffer 0 */
221#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cache Protection Lookaside Buffer 1 */
222#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cache Protection Lookaside Buffer 2 */
223#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cache Protection Lookaside Buffer 3 */
224#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cache Protection Lookaside Buffer 4 */
225#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cache Protection Lookaside Buffer 5 */
226#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cache Protection Lookaside Buffer 6 */
227#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cache Protection Lookaside Buffer 7 */
228#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cache Protection Lookaside Buffer 8 */
229#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cache Protection Lookaside Buffer 9 */
230#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cache Protection Lookaside Buffer 10 */
231#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cache Protection Lookaside Buffer 11 */
232#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cache Protection Lookaside Buffer 12 */
233#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cache Protection Lookaside Buffer 13 */
234#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cache Protection Lookaside Buffer 14 */
235#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cache Protection Lookaside Buffer 15 */
236#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
237#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
238#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
239#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
240#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
241#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
242#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
243#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
244#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
245#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
246#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
247#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
248#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
249#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
250#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
251#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
252#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
253#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
254#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
255#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
256
257/* Event/Interrupt Registers */
258#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
259#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
260#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
261#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
262#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
263#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
264#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
265#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
266#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
267#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
268#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
269#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
270#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
271#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
272#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
273#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
274#define IMASK 0xFFE02104 /* Interrupt Mask Register */
275#define IPEND 0xFFE02108 /* Interrupt Pending Register */
276#define ILAT 0xFFE0210C /* Interrupt Latch Register */
277
278/* Core Timer Registers */
279#define TCNTL 0xFFE03000 /* Core Timer Control Register */
280#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
281#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
282#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
283
284/* Debug/MP/Emulation Registers */
285#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
286#define DBGCTL 0xFFE05004 /* Debug Control Register */
287#define DBGSTAT 0xFFE05008 /* Debug Status Register */
288#define EMUDAT 0xFFE0500C /* Emulator Data Register */
289
290/* Trace Buffer Registers */
291#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
292#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
293#define TBUF 0xFFE06100 /* Trace Buffer */
294
295/* Watch Point Control Registers */
296#define WPIACTL 0xFFE07000 /* Instruction Watch Point Control Register */
297#define WPIA0 0xFFE07040 /* Instruction Watch Point Address 0 */
298#define WPIA1 0xFFE07044 /* Instruction Watch Point Address 1 */
299#define WPIA2 0xFFE07048 /* Instruction Watch Point Address 2 */
300#define WPIA3 0xFFE0704C /* Instruction Watch Point Address 3 */
301#define WPIA4 0xFFE07050 /* Instruction Watch Point Address 4 */
302#define WPIA5 0xFFE07054 /* Instruction Watch Point Address 5 */
303#define WPIACNT0 0xFFE07080 /* Instruction Watch Point Counter 0 */
304#define WPIACNT1 0xFFE07084 /* Instruction Watch Point Counter 1 */
305#define WPIACNT2 0xFFE07088 /* Instruction Watch Point Counter 2 */
306#define WPIACNT3 0xFFE0708C /* Instruction Watch Point Counter 3 */
307#define WPIACNT4 0xFFE07090 /* Instruction Watch Point Counter 4 */
308#define WPIACNT5 0xFFE07094 /* Instruction Watch Point Counter 5 */
309#define WPDACTL 0xFFE07100 /* Data Watch Point Control Register */
310#define WPDA0 0xFFE07140 /* Data Watch Point Address 0 */
311#define WPDA1 0xFFE07144 /* Data Watch Point Address 1 */
312#define WPDACNT0 0xFFE07180 /* Data Watch Point Counter 0 */
313#define WPDACNT1 0xFFE07184 /* Data Watch Point Counter 1 */
314#define WPSTAT 0xFFE07200 /* Watch Point Status Register */
315
316/* Performance Monitor Registers */
317#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
318#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
319#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
320
321
322/*********************************************************************************** */
323/* Core MMR Register Bits */
324/*********************************************************************************** */
325
326/*************************************************** */
327/* EVT registers (ILAT, IMASK, and IPEND). */
328/*************************************************** */
329
330/* ** Bit Positions */
331#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
332#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
333#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
334#define EVT_EVX_P 0x00000003 /* Exception bit position */
335#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
336#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
337#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
338#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
339#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
340#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
341#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
342#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
343#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
344#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
345#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
346#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
347
348/* ** Masks */
349#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
350#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
351#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
352#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
353#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
354#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
355#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
356#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
357#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
358#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
359#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
360#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
361#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
362#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
363#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
364#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
365
366/*************************************************** */
367/* DMEM_CONTROL register */
368/*************************************************** */
369/* ** Bit Positions */
370#define ENDM_P 0x00 /* Enable Data Memory L1 */
371#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
372#define ENDCPLB_P 0x01 /* Enable DCPLBS */
373#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
374#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
375#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
376#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
377#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
378
379/* ** Masks */
380#define ENDM MK_BMSK_(DMCTL_ENDM_P) /* Enable Data Memory L1 */
381
382/* Bank A set as SRAM, Bank B set as SRAM */
383#define ASRAM_BSRAM 0x00000000
384
385/* Enable DCPLB */
386#define ENDCPLB MK_BMSK_(DMCTL_ENDCPLB_P)
387
388/* Bank A set as CACHE, Bank B set as SRAM */
389#define ACACHE_BSRAM 0x00000008
390/* Bank A set as CACHE, Bank B set as CACHE */
391#define ACACHE_BCACHE 0x0000000C
392#define DCBS 0x00000010 /* If HIGHBIT is 1, select L1 data memory B */
393 /* If HIGHBIT is 0, select L1 data memory A */
394 /* If LOWBIT is 1, select L1 memory bank B */
395 /* If LOWBIT is 0, select L1 memory bank A */
396
397/* IMEM_CONTROL Masks */
398#define ENIM 0x00000001 /* Enable L1 Code Memory */
399#define ENICPLB 0x00000002 /* Enable ICPLB */
400#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
401
402/* TCNTL Masks */
403#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
404#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
405#define TAUTORLD 0x00000004 /* Timer auto reload */
406#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
407
408/* TCNTL Bit Positions */
409#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
410#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
411#define TAUTORLD_P 0x00000002 /* Timer auto reload */
412#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
413
414/* DCPLB_DATA and ICPLB_DATA Masks */
415#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
416#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
417#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
418#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
419 /* only applies to L1 data memory */
420#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
421#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
422#define CPLB_DA0ACC 0x00000040 /* 0=access allowed from either DAG, 1=access from DAG0 only */
423 /* only applies in L1 data memory controller */
424#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
425 /* only applies in L1 data memory controller */
426#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
427#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
428 /* only applies in L1 data memory controller in cache mode */
429#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
430#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
431#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
432#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
433
434
435/* DCPLB_DATA and ICPLB_DATA Bit Positions */
4834826e
JJ		 436#define CPLB_VALID_P 0 /* 0=invalid entry, 1=valid entry */
437#define CPLB_LOCK_P 1 /* 0=entry may be replaced, 1=entry locked */
438#define CPLB_USER_RD_P 2 /* 0=no read access, 1=read access allowed (user mode) */
439/*** DCPLB_DATA only */
440#define CPLB_USER_WR_P 3 /* 0=no write access, 0=write access allowed (user mode) */
441#define CPLB_SUPV_WR_P 4 /* 0=no write access, 0=write access allowed (supervisor mode) */
442#define CPLB_L1SRAM_P 5 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
443#define CPLB_DA0ACC_P 6 /* 0=access allowed from either DAG, 1=access from DAG0 only */
444#define CPLB_DIRTY_P 7 /* 1=dirty, 0=clean */
445#define CPLB_L1_CHBL_P 12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
446#define CPLB_WT_P 14 /* 0=write-back, 1=write-through */
447
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JJ		 448
449/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
450#if !defined(__ADSPLPBLACKFIN__)
451#define ASTAT_AC0_P ASTAT_AC0_COPY_P
452#define ASTAT_AC_P ASTAT_AC0_COPY_P
453#define ASTAT_AV0_P ASTAT_V_COPY_P
454#define ASTAT_AC MK_BMSK_(ASTAT_AC0_COPY_P)
455#define ASTAT_AV1 MK_BMSK_(ASTAT_V_COPY_P)
456#endif
457
458#ifdef _MISRA_RULES
459#pragma diag(pop)
460#endif /* _MISRA_RULES */
461
462#endif /* _DEF_BLACKFIN_H */
newlib and cygwin
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