]> sourceware.org Git - newlib-cygwin.git/blame - libgloss/bfin/include/defBF534.h
git://sourceware.org / newlib-cygwin.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libgloss: bfin: sync headers to VDSP 5.0 Update 8
[newlib-cygwin.git] / libgloss / bfin / include / defBF534.h
CommitLineData
84132c9d
JJ		 1/*
2 * The authors hereby grant permission to use, copy, modify, distribute,
3 * and license this software and its documentation for any purpose, provided
4 * that existing copyright notices are retained in all copies and that this
5 * notice is included verbatim in any distributions. No written agreement,
6 * license, or royalty fee is required for any of the authorized uses.
7 * Modifications to this software may be copyrighted by their authors
8 * and need not follow the licensing terms described here, provided that
9 * the new terms are clearly indicated on the first page of each file where
10 * they apply.
11 */
12
13/*
1cfc2fea 14** Copyright (C) 2004-2009 Analog Devices Inc., All Rights Reserved.
84132c9d
JJ		 15**
16************************************************************************************
17**
18** This include file contains a list of macro "defines" to enable the programmer
19** to use symbolic names for register-access and bit-manipulation.
20**
21**/
22#ifndef _DEF_BF534_H
23#define _DEF_BF534_H
24
25/* Include all Core registers and bit definitions */
26#include <def_LPBlackfin.h>
27
28#ifdef _MISRA_RULES
29#pragma diag(push)
4834826e
JJ		 30#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution")
31#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
1cfc2fea 32#include <stdint.h>
84132c9d
JJ		 33#endif /* _MISRA_RULES */
34
35/************************************************************************************
36** System MMR Register Map
37*************************************************************************************/
38/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
39#define PLL_CTL 0xFFC00000 /* PLL Control Register */
40#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
41#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
42#define PLL_STAT 0xFFC0000C /* PLL Status Register */
43#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
44#define CHIPID 0xFFC00014 /* Device ID Register */
45
46
47/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
48#define SWRST 0xFFC00100 /* Software Reset Register */
49#define SYSCR 0xFFC00104 /* System Configuration Register */
84132c9d
JJ		 50#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
51#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
52#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
53#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
54#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
55#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
56#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
57
58
59/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
60#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
61#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
62#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
63
64
65/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
66#define RTC_STAT 0xFFC00300 /* RTC Status Register */
67#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
68#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
69#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
70#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
71#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
72#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
73
74
75/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
76#define UART0_THR 0xFFC00400 /* Transmit Holding register */
77#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
78#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
79#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
80#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
81#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
82#define UART0_LCR 0xFFC0040C /* Line Control Register */
83#define UART0_MCR 0xFFC00410 /* Modem Control Register */
84#define UART0_LSR 0xFFC00414 /* Line Status Register */
84132c9d
JJ		 85#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87
88
89/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
92#define SPI_STAT 0xFFC00508 /* SPI Status register */
93#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
94#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
95#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
96#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
97
98
99/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
100#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
101#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
102#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
103#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
104
105#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
106#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
107#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
108#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
109
110#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
111#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
112#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
113#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
114
115#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
116#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
117#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
118#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
119
120#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
121#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
122#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
123#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
124
125#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
126#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
127#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
128#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
129
130#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
131#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
132#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
133#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
134
135#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
136#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
137#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
138#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
139
140#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
141#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
142#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
143
144
145/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
146#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
147#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
148#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
149#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
150#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
151#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
152#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
153#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
154#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
155#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
156#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
157#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
158#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
159#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
160#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
161#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
162#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
163
164
165/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
166#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
167#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
168#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
169#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
170#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
171#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
172#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
173#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
174#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
175#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
176#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
177#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
178#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
179#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
180#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
181#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
182#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
183#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
184#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
185#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
186#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
187#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
188
189
190/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
191#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
192#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
193#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
194#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
195#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
196#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
197#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
198#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
199#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
200#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
201#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
202#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
203#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
204#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
205#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
206#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
207#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
208#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
209#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
210#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
211#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
212#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
213
214
215/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
216#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
217#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
218#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
219#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
220#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
221#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
222#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
223
224
225/* DMA Traffic Control Registers */
226#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
227#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
228
229/* Alternate deprecated register names (below) provided for backwards code compatibility */
230#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
231#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
232
233/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
234#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
235#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
236#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
237#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
238#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
239#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
240#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
241#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
242#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
243#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
244#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
245#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
246#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
247
248#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
249#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
250#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
251#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
252#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
253#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
254#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
255#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
256#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
257#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
258#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
259#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
260#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
261
262#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
263#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
264#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
265#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
266#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
267#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
268#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
269#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
270#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
271#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
272#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
273#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
274#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
275
276#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
277#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
278#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
279#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
280#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
281#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
282#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
283#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
284#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
285#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
286#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
287#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
288#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
289
290#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
291#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
292#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
293#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
294#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
295#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
296#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
297#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
298#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
299#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
300#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
301#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
302#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
303
304#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
305#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
306#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
307#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
308#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
309#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
310#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
311#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
312#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
313#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
314#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
315#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
316#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
317
318#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
319#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
320#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
321#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
322#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
323#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
324#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
325#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
326#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
327#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
328#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
329#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
330#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
331
332#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
333#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
334#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
335#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
336#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
337#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
338#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
339#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
340#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
341#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
342#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
343#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
344#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
345
346#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
347#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
348#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
349#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
350#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
351#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
352#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
353#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
354#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
355#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
356#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
357#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
358#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
359
360#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
361#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
362#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
363#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
364#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
365#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
366#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
367#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
368#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
369#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
370#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
371#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
372#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
373
374#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
375#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
376#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
377#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
378#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
379#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
380#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
381#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
382#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
383#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
384#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
385#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
386#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
387
388#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
389#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
390#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
391#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
392#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
393#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
394#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
395#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
396#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
397#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
398#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
399#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
400#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
401
402#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
403#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
404#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
405#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
406#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
407#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
408#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
409#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
410#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
411#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
412#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
413#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
414#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
415
416#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
417#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
418#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
419#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
420#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
421#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
422#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
423#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
424#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
425#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
426#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
427#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
428#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
429
430#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
431#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
432#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
433#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
434#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
435#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
436#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
437#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
438#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
439#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
440#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
441#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
442#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
443
444#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
445#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
446#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
447#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
448#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
449#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
450#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
451#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
452#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
453#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
454#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
455#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
456#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
457
458
459/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
460#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
461#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
462#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
463#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
464#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
465
466
467/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
468#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
469#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
470#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
471#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
472#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
473#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
474#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
475#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
476#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
477#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
478#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
479#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
480#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
481#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
482#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
483#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
484
485
486/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
487#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
488#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
489#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
490#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
491#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
492#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
493#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
494#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
495#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
496#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
497#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
498#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
499#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
500#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
501#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
502#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
503#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
504
505
506/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
507#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
508#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
509#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
510#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
511#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
512#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
513#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
514#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
515#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
516#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
517#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
518#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
519#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
520#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
521#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
522#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
523#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
524
525
526/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
527#define UART1_THR 0xFFC02000 /* Transmit Holding register */
528#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
529#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
530#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
531#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
532#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
533#define UART1_LCR 0xFFC0200C /* Line Control Register */
534#define UART1_MCR 0xFFC02010 /* Modem Control Register */
535#define UART1_LSR 0xFFC02014 /* Line Status Register */
84132c9d
JJ		 536#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
537#define UART1_GCTL 0xFFC02024 /* Global Control Register */
538
539
540/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
541/* For Mailboxes 0-15 */
542#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
543#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
544#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
545#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
546#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
547#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
548#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
549#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
550#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
551#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
552#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
553#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
554#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
555
556/* For Mailboxes 16-31 */
557#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
558#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
559#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
560#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
561#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
562#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
563#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
564#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
565#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
566#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
567#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
568#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
569#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
570
571/* CAN Configuration, Control, and Status Registers */
572#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
573#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
574#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
575#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
576#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
577#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
578#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
579#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
580#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
581#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
582#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
583#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
584#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
84132c9d 585#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
4834826e 586#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
84132c9d
JJ		 587#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
588
589/* Mailbox Acceptance Masks */
590#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
591#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
592#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
593#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
594#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
595#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
596#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
597#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
598#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
599#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
600#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
601#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
602#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
603#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
604#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
605#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
606#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
607#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
608#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
609#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
610#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
611#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
612#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
613#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
614#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
615#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
616#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
617#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
618#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
619#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
620#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
621#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
622
623#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
624#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
625#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
626#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
627#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
628#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
629#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
630#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
631#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
632#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
633#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
634#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
635#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
636#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
637#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
638#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
639#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
640#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
641#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
642#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
643#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
644#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
645#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
646#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
647#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
648#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
649#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
650#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
651#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
652#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
653#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
654#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
655
656/* CAN Acceptance Mask Macros */
657#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
658#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
659
660/* Mailbox Registers */
661#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
662#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
663#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
664#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
665#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
666#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
667#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
668#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
669
670#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
671#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
672#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
673#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
674#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
675#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
676#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
677#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
678
679#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
680#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
681#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
682#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
683#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
684#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
685#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
686#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
687
688#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
689#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
690#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
691#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
692#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
693#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
694#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
695#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
696
697#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
698#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
699#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
700#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
701#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
702#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
703#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
704#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
705
706#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
707#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
708#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
709#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
710#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
711#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
712#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
713#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
714
715#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
716#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
717#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
718#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
719#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
720#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
721#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
722#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
723
724#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
725#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
726#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
727#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
728#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
729#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
730#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
731#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
732
733#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
734#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
735#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
736#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
737#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
738#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
739#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
740#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
741
742#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
743#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
744#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
745#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
746#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
747#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
748#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
749#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
750
751#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
752#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
753#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
754#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
755#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
756#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
757#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
758#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
759
760#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
761#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
762#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
763#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
764#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
765#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
766#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
767#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
768
769#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
770#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
771#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
772#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
773#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
774#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
775#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
776#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
777
778#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
779#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
780#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
781#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
782#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
783#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
784#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
785#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
786
787#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
788#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
789#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
790#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
791#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
792#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
793#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
794#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
795
796#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
797#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
798#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
799#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
800#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
801#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
802#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
803#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
804
805#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
806#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
807#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
808#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
809#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
810#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
811#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
812#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
813
814#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
815#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
816#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
817#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
818#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
819#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
820#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
821#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
822
823#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
824#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
825#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
826#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
827#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
828#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
829#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
830#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
831
832#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
833#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
834#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
835#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
836#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
837#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
838#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
839#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
840
841#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
842#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
843#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
844#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
845#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
846#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
847#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
848#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
849
850#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
851#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
852#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
853#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
854#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
855#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
856#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
857#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
858
859#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
860#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
861#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
862#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
863#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
864#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
865#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
866#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
867
868#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
869#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
870#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
871#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
872#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
873#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
874#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
875#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
876
877#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
878#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
879#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
880#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
881#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
882#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
883#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
884#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
885
886#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
887#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
888#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
889#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
890#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
891#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
892#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
893#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
894
895#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
896#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
897#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
898#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
899#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
900#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
901#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
902#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
903
904#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
905#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
906#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
907#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
908#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
909#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
910#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
911#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
912
913#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
914#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
915#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
916#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
917#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
918#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
919#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
920#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
921
922#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
923#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
924#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
925#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
926#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
927#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
928#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
929#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
930
931#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
932#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
933#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
934#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
935#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
936#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
937#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
938#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
939
940#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
941#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
942#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
943#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
944#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
945#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
946#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
947#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
948
949/* CAN Mailbox Area Macros */
950#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
951#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
952#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
953#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
954#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
955#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
956#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
957#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
958
959
960/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
961#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
962#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
963#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
964#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
965
966
967/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
968#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
969#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
970#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
971#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
972#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
973#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
974#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
975
976#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
977#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
978#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
979#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
980#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
981#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
982#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
983
984
985/***********************************************************************************
986** System MMR Register Bits And Macros
987**
988** Disclaimer: All macros are intended to make C and Assembly code more readable.
989** Use these macros carefully, as any that do left shifts for field
990** depositing will result in the lower order bits being destroyed. Any
991** macro that shifts left to properly position the bit-field should be
992** used as part of an OR to initialize a register and NOT as a dynamic
993** modifier UNLESS the lower order bits are saved and ORed back in when
994** the macro is used.
995*************************************************************************************/
996/*
997** ********************* PLL AND RESET MASKS ****************************************/
998/* PLL_CTL Masks */
999#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1000#define PLL_OFF 0x0002 /* PLL Not Powered */
1001#define STOPCK 0x0008 /* Core Clock Off */
1002#define PDWN 0x0020 /* Enter Deep Sleep Mode */
1003#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
1004#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
1005#define BYPASS 0x0100 /* Bypass the PLL */
1006#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
4834826e 1007#define SPORT_HYS 0x8000 /* Add 250mV of Hysteresis to SPORT Inputs */
84132c9d 1008/* PLL_CTL Macros */
4834826e
JJ		 1009#ifdef _MISRA_RULES
1010#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1011#else
84132c9d 1012#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
4834826e 1013#endif /* _MISRA_RULES */
84132c9d
JJ		 1014
1015/* PLL_DIV Masks */
1016#define SSEL 0x000F /* System Select */
1017#define CSEL 0x0030 /* Core Select */
1018#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1019#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1020#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1021#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1022/* PLL_DIV Macros */
4834826e
JJ		 1023#ifdef _MISRA_RULES
1024#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1025#else
84132c9d 1026#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
4834826e 1027#endif /* _MISRA_RULES */
84132c9d
JJ		 1028
1029/* VR_CTL Masks */
1030#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1031#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1032#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1033#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1034#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1035
1036#define GAIN 0x000C /* Voltage Level Gain */
1037#define GAIN_5 0x0000 /* GAIN = 5 */
1038#define GAIN_10 0x0004 /* GAIN = 10 */
1039#define GAIN_20 0x0008 /* GAIN = 20 */
1040#define GAIN_50 0x000C /* GAIN = 50 */
1041
1042#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1043#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
1044#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
1045#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
1046#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1047#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1048#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1049#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1050#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1051#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1052#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1053
1054#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1055#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1056#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1057#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1058#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1059#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1060
1061/* PLL_STAT Masks */
1062#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1063#define FULL_ON 0x0002 /* Processor In Full On Mode */
1064#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1065#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1066
1067/* SWRST Masks */
1068#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1069#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1070#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1071#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1072#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1073
1074/* SYSCR Masks */
4834826e
JJ		 1075/* SYSCR Masks */
1076#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
1077#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
1078#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
1079#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
1080#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
1081#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
1082#define BMODE_UARTHOST 0x0007 /* Boot from UART0 host */
84132c9d
JJ		 1083#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
1084#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1085
1086
1087/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1088/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
1089#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
1090
1091#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
1092#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
1093#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
1094#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
1095#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
1096#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
1097#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
1098
1099#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
1100#define IRQ_TWI 0x00000200 /* TWI Interrupt */
1101#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
1102#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
1103#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
1104#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
1105#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
1106#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
1107
1108#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
1109#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
1110#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
1111#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
1112#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
1113#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
1114#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
1115#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
1116#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
1117#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
1118
1119#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
1120#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
1121#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
1122#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
1123#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
1124#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
1125#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
1126#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
1127#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
1128#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
1129#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
1130
4834826e
JJ		 1131#ifdef _MISRA_RULES
1132#define _MF15 0xFu
1133#define _MF7 7u
1134#else
1135#define _MF15 0xF
1136#define _MF7 7
1137#endif /* _MISRA_RULES */
1138
84132c9d 1139/* SIC_IAR0 Macros */
4834826e
JJ		 1140#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
1141#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
1142#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
1143#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
1144#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
1145#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
1146#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
1147#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
84132c9d
JJ		 1148
1149/* SIC_IAR1 Macros */
4834826e
JJ		 1150#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
1151#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
1152#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #10 assigned IVG #x */
1153#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #11 assigned IVG #x */
1154#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #12 assigned IVG #x */
1155#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #13 assigned IVG #x */
1156#define P14_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #14 assigned IVG #x */
1157#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #15 assigned IVG #x */
84132c9d
JJ		 1158
1159/* SIC_IAR2 Macros */
4834826e
JJ		 1160#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
1161#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #17 assigned IVG #x */
1162#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #18 assigned IVG #x */
1163#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #19 assigned IVG #x */
1164#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #20 assigned IVG #x */
1165#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #21 assigned IVG #x */
1166#define P22_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #22 assigned IVG #x */
1167#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #23 assigned IVG #x */
84132c9d
JJ		 1168
1169/* SIC_IAR3 Macros */
4834826e
JJ		 1170#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
1171#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #25 assigned IVG #x */
1172#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #26 assigned IVG #x */
1173#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #27 assigned IVG #x */
1174#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #28 assigned IVG #x */
1175#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #29 assigned IVG #x */
1176#define P30_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #30 assigned IVG #x */
1177#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #31 assigned IVG #x */
84132c9d 1178
1cfc2fea
MF		 1179/* SIC_IMASK Masks*/
1180#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1181#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
4834826e 1182#ifdef _MISRA_RULES
1cfc2fea
MF		 1183#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
1184#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
4834826e 1185#else
1cfc2fea
MF		 1186#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1187#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
4834826e 1188#endif /* _MISRA_RULES */
84132c9d 1189
1cfc2fea
MF		 1190/* SIC_IWR Masks*/
1191#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1192#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
4834826e 1193#ifdef _MISRA_RULES
1cfc2fea
MF		 1194#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
1195#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
4834826e 1196#else
1cfc2fea
MF		 1197#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1198#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
4834826e 1199#endif /* _MISRA_RULES */
84132c9d
JJ		 1200
1201
1202/* ********* WATCHDOG TIMER MASKS ******************** */
1203
1204/* Watchdog Timer WDOG_CTL Register Masks */
1205
4834826e
JJ		 1206#ifdef _MISRA_RULES
1207#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
1208#else
84132c9d 1209#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
4834826e 1210#endif /* _MISRA_RULES */
84132c9d
JJ		 1211#define WDEV_RESET 0x0000 /* generate reset event on roll over */
1212#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
1213#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
1214#define WDEV_NONE 0x0006 /* no event on roll over */
1215#define WDEN 0x0FF0 /* enable watchdog */
1216#define WDDIS 0x0AD0 /* disable watchdog */
1217#define WDRO 0x8000 /* watchdog rolled over latch */
1218
1219/* depreciated WDOG_CTL Register Masks for legacy code */
1220
1221
1222#define ICTL WDEV
1223#define ENABLE_RESET WDEV_RESET
1224#define WDOG_RESET WDEV_RESET
1225#define ENABLE_NMI WDEV_NMI
1226#define WDOG_NMI WDEV_NMI
1227#define ENABLE_GPI WDEV_GPI
1228#define WDOG_GPI WDEV_GPI
1229#define DISABLE_EVT WDEV_NONE
1230#define WDOG_NONE WDEV_NONE
1231
1232#define TMR_EN WDEN
1233#define WDOG_DISABLE WDDIS
1234#define TRO WDRO
1235#define ICTL_P0 0x01
1236 #define ICTL_P1 0x02
1237#define TRO_P 0x0F
1238
1239
1240
1241/* *************** REAL TIME CLOCK MASKS **************************/
1242/* RTC_STAT and RTC_ALARM Masks */
1243#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
1244#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
1245#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
1246#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
1247
1248/* RTC_ALARM Macro z=day y=hr x=min w=sec */
4834826e
JJ		 1249#ifdef _MISRA_RULES
1250#define SET_ALARM(z,y,x,w) ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
1251#else
84132c9d 1252#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
4834826e 1253#endif /* _MISRA_RULES */
84132c9d
JJ		 1254
1255/* RTC_ICTL and RTC_ISTAT Masks */
1256#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
1257#define ALARM 0x0002 /* Alarm Interrupt Enable */
1258#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
1259#define MINUTE 0x0008 /* Minutes Interrupt Enable */
1260#define HOUR 0x0010 /* Hours Interrupt Enable */
1261#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
1262#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1263#define WRITE_PENDING 0x4000 /* Write Pending Status */
1264#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
1265
1266/* RTC_FAST / RTC_PREN Mask */
1267#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
1268
1269
1270/* ************** UART CONTROLLER MASKS *************************/
1271/* UARTx_LCR Masks */
4834826e
JJ		 1272#ifdef _MISRA_RULES
1273#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
1274#else
84132c9d 1275#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
4834826e 1276#endif /* _MISRA_RULES */
84132c9d
JJ		 1277#define STB 0x04 /* Stop Bits */
1278#define PEN 0x08 /* Parity Enable */
1279#define EPS 0x10 /* Even Parity Select */
1280#define STP 0x20 /* Stick Parity */
1281#define SB 0x40 /* Set Break */
1282#define DLAB 0x80 /* Divisor Latch Access */
1283
1284/* UARTx_MCR Mask */
1285#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1286#define LOOP_ENA_P 0x04
1287
1288/* UARTx_LSR Masks */
1289#define DR 0x01 /* Data Ready */
1290#define OE 0x02 /* Overrun Error */
1291#define PE 0x04 /* Parity Error */
1292#define FE 0x08 /* Framing Error */
1293#define BI 0x10 /* Break Interrupt */
1294#define THRE 0x20 /* THR Empty */
1295#define TEMT 0x40 /* TSR and UART_THR Empty */
1296
1297/* UARTx_IER Masks */
1298#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1299#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1300#define ELSI 0x04 /* Enable RX Status Interrupt */
1301
1302/* UARTx_IIR Masks */
1303#define NINT 0x01 /* Pending Interrupt */
1304#define STATUS 0x06 /* Highest Priority Pending Interrupt */
1305
1306/* UARTx_GCTL Masks */
1307#define UCEN 0x01 /* Enable UARTx Clocks */
1308#define IREN 0x02 /* Enable IrDA Mode */
1309#define TPOLC 0x04 /* IrDA TX Polarity Change */
1310#define RPOLC 0x08 /* IrDA RX Polarity Change */
1311#define FPE 0x10 /* Force Parity Error On Transmit */
1312#define FFE 0x20 /* Force Framing Error On Transmit */
1313
4834826e
JJ		 1314/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
1315#define UARTDLL 0x00FF /* Divisor Latch Low Byte */
1316#define UARTDLH 0xFF00 /* Divisor Latch High Byte */
1317
84132c9d
JJ		 1318
1319/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1320/* SPI_CTL Masks */
1321#define TIMOD 0x0003 /* Transfer Initiate Mode */
1322#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1323#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1324#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1325#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1326#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1327#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1328#define PSSE 0x0010 /* Slave-Select Input Enable */
1329#define EMISO 0x0020 /* Enable MISO As Output */
1330#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1331#define LSBF 0x0200 /* LSB First */
1332#define CPHA 0x0400 /* Clock Phase */
1333#define CPOL 0x0800 /* Clock Polarity */
1334#define MSTR 0x1000 /* Master/Slave* */
1335#define WOM 0x2000 /* Write Open Drain Master */
1336#define SPE 0x4000 /* SPI Enable */
1337
1338/* SPI_FLG Masks */
1339#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1340#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1341#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1342#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1343#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1344#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1345#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1346#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1347#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1348#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1349#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1350#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1351#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1352#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1353
1354/* SPI_STAT Masks */
1355#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1356#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1357#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1358#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1359#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1360#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1361#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1362
1363
1364/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1365/* TIMER_ENABLE Masks */
1366#define TIMEN0 0x0001 /* Enable Timer 0 */
1367#define TIMEN1 0x0002 /* Enable Timer 1 */
1368#define TIMEN2 0x0004 /* Enable Timer 2 */
1369#define TIMEN3 0x0008 /* Enable Timer 3 */
1370#define TIMEN4 0x0010 /* Enable Timer 4 */
1371#define TIMEN5 0x0020 /* Enable Timer 5 */
1372#define TIMEN6 0x0040 /* Enable Timer 6 */
1373#define TIMEN7 0x0080 /* Enable Timer 7 */
1374
1375/* TIMER_DISABLE Masks */
1376#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1377#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1378#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1379#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1380#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1381#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1382#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1383#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1384
1385/* TIMER_STATUS Masks */
1386#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1387#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1388#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1389#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1390#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1391#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1392#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1393#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1394#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1395#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1396#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1397#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1398#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1399#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1400#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1401#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1402#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1403#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1404#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1405#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1406#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1407#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1408#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1409#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1410
1411/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1412#define TOVL_ERR0 TOVF_ERR0
1413#define TOVL_ERR1 TOVF_ERR1
1414#define TOVL_ERR2 TOVF_ERR2
1415#define TOVL_ERR3 TOVF_ERR3
1416#define TOVL_ERR4 TOVF_ERR4
1417#define TOVL_ERR5 TOVF_ERR5
1418#define TOVL_ERR6 TOVF_ERR6
1419#define TOVL_ERR7 TOVF_ERR7
1420
1421/* TIMERx_CONFIG Masks */
1422#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1423#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1424#define EXT_CLK 0x0003 /* External Clock Mode */
1425#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1426#define PERIOD_CNT 0x0008 /* Period Count */
1427#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1428#define TIN_SEL 0x0020 /* Timer Input Select */
1429#define OUT_DIS 0x0040 /* Output Pad Disable */
1430#define CLK_SEL 0x0080 /* Timer Clock Select */
1431#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1432#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1433#define ERR_TYP 0xC000 /* Error Type */
1434
1435
1436/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1437/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1438/* Port F Masks */
1439#define PF0 0x0001
1440#define PF1 0x0002
1441#define PF2 0x0004
1442#define PF3 0x0008
1443#define PF4 0x0010
1444#define PF5 0x0020
1445#define PF6 0x0040
1446#define PF7 0x0080
1447#define PF8 0x0100
1448#define PF9 0x0200
1449#define PF10 0x0400
1450#define PF11 0x0800
1451#define PF12 0x1000
1452#define PF13 0x2000
1453#define PF14 0x4000
1454#define PF15 0x8000
1455
1456/* Port G Masks */
1457#define PG0 0x0001
1458#define PG1 0x0002
1459#define PG2 0x0004
1460#define PG3 0x0008
1461#define PG4 0x0010
1462#define PG5 0x0020
1463#define PG6 0x0040
1464#define PG7 0x0080
1465#define PG8 0x0100
1466#define PG9 0x0200
1467#define PG10 0x0400
1468#define PG11 0x0800
1469#define PG12 0x1000
1470#define PG13 0x2000
1471#define PG14 0x4000
1472#define PG15 0x8000
1473
1474/* Port H Masks */
1475#define PH0 0x0001
1476#define PH1 0x0002
1477#define PH2 0x0004
1478#define PH3 0x0008
1479#define PH4 0x0010
1480#define PH5 0x0020
1481#define PH6 0x0040
1482#define PH7 0x0080
1483#define PH8 0x0100
1484#define PH9 0x0200
1485#define PH10 0x0400
1486#define PH11 0x0800
1487#define PH12 0x1000
1488#define PH13 0x2000
1489#define PH14 0x4000
1490#define PH15 0x8000
1491
1492
1493/* ******************* SERIAL PORT MASKS **************************************/
1494/* SPORTx_TCR1 Masks */
1495#define TSPEN 0x0001 /* Transmit Enable */
1496#define ITCLK 0x0002 /* Internal Transmit Clock Select */
4834826e 1497#define DTYPE_NORM 0x0000 /* Data Format Normal */
84132c9d
JJ		 1498#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1499#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1500#define TLSBIT 0x0010 /* Transmit Bit Order */
1501#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1502#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1503#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1504#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1505#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1506#define TCKFE 0x4000 /* Clock Falling Edge Select */
1507
1508/* SPORTx_TCR2 Masks and Macro */
4834826e
JJ		 1509#ifdef _MISRA_RULES
1510#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
1511#else
84132c9d 1512#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
4834826e 1513#endif /* _MISRA_RULES */
84132c9d
JJ		 1514#define TXSE 0x0100 /* TX Secondary Enable */
1515#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1516#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1517
1518/* SPORTx_RCR1 Masks */
1519#define RSPEN 0x0001 /* Receive Enable */
1520#define IRCLK 0x0002 /* Internal Receive Clock Select */
4834826e 1521#define DTYPE_NORM 0x0000 /* Data Format Normal */
84132c9d
JJ		 1522#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1523#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1524#define RLSBIT 0x0010 /* Receive Bit Order */
1525#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1526#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1527#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1528#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1529#define RCKFE 0x4000 /* Clock Falling Edge Select */
1530
1531/* SPORTx_RCR2 Masks */
4834826e
JJ		 1532#ifdef _MISRA_RULES
1533#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
1534#else
84132c9d 1535#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
4834826e 1536#endif /* _MISRA_RULES */
84132c9d
JJ		 1537#define RXSE 0x0100 /* RX Secondary Enable */
1538#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1539#define RRFST 0x0400 /* Right-First Data Order */
1540
1541/* SPORTx_STAT Masks */
1542#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1543#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1544#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1545#define TXF 0x0008 /* Transmit FIFO Full Status */
1546#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1547#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1548#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1549
1550/* SPORTx_MCMC1 Macros */
4834826e
JJ		 1551#ifdef _MISRA_RULES
1552#define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
1553
1554/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1555#define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1556#else
84132c9d
JJ		 1557#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1558
1559/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1560#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
4834826e 1561#endif /* _MISRA_RULES */
84132c9d
JJ		 1562
1563/* SPORTx_MCMC2 Masks */
1564#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1565#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1566#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1567#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1568#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1569#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1570#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1571#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1572#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1573#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1574#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1575#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1576#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1577#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1578#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1579#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1580#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1581#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1582#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1583#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1584#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1585#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1586#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1587
1588
1589/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1590/* EBIU_AMGCTL Masks */
1591#define AMCKEN 0x0001 /* Enable CLKOUT */
1592#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1593#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1594#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1595#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1596#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1597#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
1598
1599/* EBIU_AMBCTL0 Masks */
1600#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1601#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1602#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1603#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1604#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1605#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1606#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1607#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1608#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1609#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1610#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1611#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1612#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1613#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1614#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1615#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1616#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1617#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1618#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1619#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1620#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1621#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1622#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1623#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1624#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1625#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1626#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1627#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1628#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1629#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1630#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1631#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1632#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1633#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1634#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1635#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1636#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1637#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1638#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1639#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1640#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1641#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1642#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1643#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1644
1645#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1646#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1647#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1648#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1649#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1650#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1651#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1652#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1653#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1654#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1655#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1656#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1657#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1658#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1659#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1660#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1661#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1662#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1663#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1664#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1665#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1666#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1667#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1668#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1669#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1670#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1671#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1672#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1673#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1674#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1675#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1676#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1677#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1678#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1679#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1680#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1681#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1682#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1683#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1684#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1685#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1686#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1687#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1688#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1689
1690/* EBIU_AMBCTL1 Masks */
1691#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1692#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1693#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1694#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1695#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1696#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1697#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1698#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1699#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1700#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1701#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1702#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1703#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1704#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1705#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1706#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1707#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1708#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1709#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1710#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1711#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1712#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1713#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1714#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1715#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1716#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1717#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1718#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1719#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1720#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1721#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1722#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1723#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1724#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1725#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1726#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1727#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1728#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1729#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1730#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1731#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1732#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1733#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1734#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1735
1736#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1737#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1738#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1739#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1740#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1741#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1742#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1743#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1744#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1745#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1746#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1747#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1748#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1749#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1750#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1751#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1752#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1753#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1754#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1755#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1756#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1757#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1758#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1759#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1760#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1761#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1762#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1763#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1764#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1765#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1766#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1767#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1768#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1769#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1770#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1771#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1772#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1773#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1774#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1775#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1776#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1777#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1778#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1779#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1780
1781
1782/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1783/* EBIU_SDGCTL Masks */
4834826e 1784
84132c9d
JJ		 1785#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1786#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1787#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
4834826e 1788#define CL 0x0000000C /* SDRAM CAS latency */
84132c9d
JJ		 1789#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1790#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1791#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
4834826e 1792#define PASR 0x00000030 /* SDRAM partial array self-refresh */
84132c9d
JJ		 1793#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1794#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1795#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1796#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1797#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1798#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1799#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1800#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1801#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1802#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1803#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1804#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1805#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1806#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1807#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
4834826e 1808#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
84132c9d
JJ		 1809#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1810#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1811#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1812#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1813#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1814#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1815#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
4834826e 1816#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
84132c9d
JJ		 1817#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1818#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1819#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1820#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1821#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1822#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1823#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
4834826e 1824#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
84132c9d
JJ		 1825#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1826#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1827#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
4834826e 1828#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
84132c9d
JJ		 1829#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1830#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1831#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1832#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1833#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1834#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1835#define EMREN 0x10000000 /* Extended Mode Register Enable */
1836#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1837#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1838
1839/* EBIU_SDBCTL Masks */
1840#define EBE 0x0001 /* Enable SDRAM External Bank */
1841#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1842#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1843#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1844#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
4834826e
JJ		 1845#define EBSZ 0x0006 /* SDRAM external bank size */
1846
84132c9d
JJ		 1847#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1848#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1849#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1850#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
4834826e 1851#define EBCAW 0x0030 /* SDRAM external bank column address width */
84132c9d
JJ		 1852
1853/* EBIU_SDSTAT Masks */
1854#define SDCI 0x0001 /* SDRAM Controller Idle */
1855#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1856#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1857#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1858#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1859#define BGSTAT 0x0020 /* Bus Grant Status */
1860
1861
1862/* ************************** DMA CONTROLLER MASKS ********************************/
1863/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1864#define DMAEN 0x0001 /* DMA Channel Enable */
1865#define WNR 0x0002 /* Channel Direction (W/R*) */
1866#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1867#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1868#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1869#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1870#define SYNC 0x0020 /* DMA Buffer Clear */
1871#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1872#define DI_EN 0x0080 /* Data Interrupt Enable */
1873#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1874#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1875#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1876#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1877#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1878#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1879#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1880#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1881#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1882#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1883#define FLOW_STOP 0x0000 /* Stop Mode */
1884#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
1885#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1886#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1887#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1888
1889/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1890#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1891#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1892#define PMAP_PPI 0x0000 /* PPI Port DMA */
1893#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1894#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1895#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1896#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1897#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1898#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1899#define PMAP_SPI 0x7000 /* SPI Port DMA */
1900#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1901#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1902#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1903#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1904
1905/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1906#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1907#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1908#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1909#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1910
1911
1912/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1913/* PPI_CONTROL Masks */
1914#define PORT_EN 0x0001 /* PPI Port Enable */
1915#define PORT_DIR 0x0002 /* PPI Port Direction */
1916#define XFR_TYPE 0x000C /* PPI Transfer Type */
1917#define PORT_CFG 0x0030 /* PPI Port Configuration */
1918#define FLD_SEL 0x0040 /* PPI Active Field Select */
1919#define PACK_EN 0x0080 /* PPI Packing Mode */
1920/* previous versions of defBF534.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1921#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1922#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1923#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1924#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1925#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1926#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1927#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1928#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1929#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1930#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1931#define POLC 0x4000 /* PPI Clock Polarity */
1932#define POLS 0x8000 /* PPI Frame Sync Polarity */
1933
1934/* PPI_STATUS Masks */
1935#define FLD 0x0400 /* Field Indicator */
1936#define FT_ERR 0x0800 /* Frame Track Error */
1937#define OVR 0x1000 /* FIFO Overflow Error */
1938#define UNDR 0x2000 /* FIFO Underrun Error */
1939#define ERR_DET 0x4000 /* Error Detected Indicator */
1940#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1941
1942
1943/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1944/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
4834826e
JJ		 1945#ifdef _MISRA_RULES
1946#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
1947#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
1948#else
84132c9d
JJ		 1949#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1950#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
4834826e 1951#endif /* _MISRA_RULES */
84132c9d
JJ		 1952
1953/* TWI_PRESCALE Masks */
1954#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1955#define TWI_ENA 0x0080 /* TWI Enable */
1956#define SCCB 0x0200 /* SCCB Compatibility Enable */
1957
1958/* TWI_SLAVE_CTRL Masks */
1959#define SEN 0x0001 /* Slave Enable */
1960#define SADD_LEN 0x0002 /* Slave Address Length */
1961#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1962#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1963#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1964
1965/* TWI_SLAVE_STAT Masks */
1966#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1967#define GCALL 0x0002 /* General Call Indicator */
1968
1969/* TWI_MASTER_CTRL Masks */
1970#define MEN 0x0001 /* Master Mode Enable */
1971#define MADD_LEN 0x0002 /* Master Address Length */
1972#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1973#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1974#define STOP 0x0010 /* Issue Stop Condition */
1975#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1976#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1977#define SDAOVR 0x4000 /* Serial Data Override */
1978#define SCLOVR 0x8000 /* Serial Clock Override */
1979
1980/* TWI_MASTER_STAT Masks */
1981#define MPROG 0x0001 /* Master Transfer In Progress */
1982#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1983#define ANAK 0x0004 /* Address Not Acknowledged */
1984#define DNAK 0x0008 /* Data Not Acknowledged */
1985#define BUFRDERR 0x0010 /* Buffer Read Error */
1986#define BUFWRERR 0x0020 /* Buffer Write Error */
1987#define SDASEN 0x0040 /* Serial Data Sense */
1988#define SCLSEN 0x0080 /* Serial Clock Sense */
1989#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1990
1991/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1992#define SINIT 0x0001 /* Slave Transfer Initiated */
1993#define SCOMP 0x0002 /* Slave Transfer Complete */
1994#define SERR 0x0004 /* Slave Transfer Error */
1995#define SOVF 0x0008 /* Slave Overflow */
1996#define MCOMP 0x0010 /* Master Transfer Complete */
1997#define MERR 0x0020 /* Master Transfer Error */
1998#define XMTSERV 0x0040 /* Transmit FIFO Service */
1999#define RCVSERV 0x0080 /* Receive FIFO Service */
2000
2001/* TWI_FIFO_CTRL Masks */
2002#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
2003#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
2004#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
2005#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
2006
2007/* TWI_FIFO_STAT Masks */
2008#define XMTSTAT 0x0003 /* Transmit FIFO Status */
2009#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
2010#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
2011#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
2012
2013#define RCVSTAT 0x000C /* Receive FIFO Status */
2014#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
2015#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
2016#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2017
2018
2019/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
2020/* CAN_CONTROL Masks */
2021#define SRS 0x0001 /* Software Reset */
2022#define DNM 0x0002 /* Device Net Mode */
2023#define ABO 0x0004 /* Auto-Bus On Enable */
2024#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
2025#define SMR 0x0020 /* Sleep Mode Request */
2026#define CSR 0x0040 /* CAN Suspend Mode Request */
2027#define CCR 0x0080 /* CAN Configuration Mode Request */
2028
2029/* CAN_STATUS Masks */
2030#define WT 0x0001 /* TX Warning Flag */
2031#define WR 0x0002 /* RX Warning Flag */
2032#define EP 0x0004 /* Error Passive Mode */
2033#define EBO 0x0008 /* Error Bus Off Mode */
2034#define CSA 0x0040 /* Suspend Mode Acknowledge */
2035#define CCA 0x0080 /* Configuration Mode Acknowledge */
2036#define MBPTR 0x1F00 /* Mailbox Pointer */
2037#define TRM 0x4000 /* Transmit Mode */
2038#define REC 0x8000 /* Receive Mode */
2039
2040/* CAN_CLOCK Masks */
2041#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
2042
2043/* CAN_TIMING Masks */
2044#define TSEG1 0x000F /* Time Segment 1 */
2045#define TSEG2 0x0070 /* Time Segment 2 */
2046#define SAM 0x0080 /* Sampling */
2047#define SJW 0x0300 /* Synchronization Jump Width */
2048
2049/* CAN_DEBUG Masks */
2050#define DEC 0x0001 /* Disable CAN Error Counters */
2051#define DRI 0x0002 /* Disable CAN RX Input */
2052#define DTO 0x0004 /* Disable CAN TX Output */
2053#define DIL 0x0008 /* Disable CAN Internal Loop */
2054#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
2055#define MRB 0x0020 /* Mode Read Back Enable */
2056#define CDE 0x8000 /* CAN Debug Enable */
2057
2058/* CAN_CEC Masks */
2059#define RXECNT 0x00FF /* Receive Error Counter */
2060#define TXECNT 0xFF00 /* Transmit Error Counter */
2061
2062/* CAN_INTR Masks */
2063#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
2064#define MBRIF MBRIRQ /* legacy */
2065#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
2066#define MBTIF MBTIRQ /* legacy */
2067#define GIRQ 0x0004 /* Global Interrupt */
2068#define SMACK 0x0008 /* Sleep Mode Acknowledge */
2069#define CANTX 0x0040 /* CAN TX Bus Value */
2070#define CANRX 0x0080 /* CAN RX Bus Value */
2071
2072/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
2073#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
2074#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
2075#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
2076#define BASEID 0x1FFC /* Base Identifier */
2077#define IDE 0x2000 /* Identifier Extension */
2078#define RTR 0x4000 /* Remote Frame Transmission Request */
2079#define AME 0x8000 /* Acceptance Mask Enable */
2080
2081/* CAN_MBxx_TIMESTAMP Masks */
2082#define TSV 0xFFFF /* Timestamp */
2083
2084/* CAN_MBxx_LENGTH Masks */
2085#define DLC 0x000F /* Data Length Code */
2086
2087/* CAN_AMxxH and CAN_AMxxL Masks */
2088#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
2089#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
2090#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
2091#define BASEID 0x1FFC /* Base Identifier */
2092#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
2093#define FMD 0x4000 /* Full Mask Data Field Enable */
2094#define FDF 0x8000 /* Filter On Data Field Enable */
2095
2096/* CAN_MC1 Masks */
2097#define MC0 0x0001 /* Enable Mailbox 0 */
2098#define MC1 0x0002 /* Enable Mailbox 1 */
2099#define MC2 0x0004 /* Enable Mailbox 2 */
2100#define MC3 0x0008 /* Enable Mailbox 3 */
2101#define MC4 0x0010 /* Enable Mailbox 4 */
2102#define MC5 0x0020 /* Enable Mailbox 5 */
2103#define MC6 0x0040 /* Enable Mailbox 6 */
2104#define MC7 0x0080 /* Enable Mailbox 7 */
2105#define MC8 0x0100 /* Enable Mailbox 8 */
2106#define MC9 0x0200 /* Enable Mailbox 9 */
2107#define MC10 0x0400 /* Enable Mailbox 10 */
2108#define MC11 0x0800 /* Enable Mailbox 11 */
2109#define MC12 0x1000 /* Enable Mailbox 12 */
2110#define MC13 0x2000 /* Enable Mailbox 13 */
2111#define MC14 0x4000 /* Enable Mailbox 14 */
2112#define MC15 0x8000 /* Enable Mailbox 15 */
2113
2114/* CAN_MC2 Masks */
2115#define MC16 0x0001 /* Enable Mailbox 16 */
2116#define MC17 0x0002 /* Enable Mailbox 17 */
2117#define MC18 0x0004 /* Enable Mailbox 18 */
2118#define MC19 0x0008 /* Enable Mailbox 19 */
2119#define MC20 0x0010 /* Enable Mailbox 20 */
2120#define MC21 0x0020 /* Enable Mailbox 21 */
2121#define MC22 0x0040 /* Enable Mailbox 22 */
2122#define MC23 0x0080 /* Enable Mailbox 23 */
2123#define MC24 0x0100 /* Enable Mailbox 24 */
2124#define MC25 0x0200 /* Enable Mailbox 25 */
2125#define MC26 0x0400 /* Enable Mailbox 26 */
2126#define MC27 0x0800 /* Enable Mailbox 27 */
2127#define MC28 0x1000 /* Enable Mailbox 28 */
2128#define MC29 0x2000 /* Enable Mailbox 29 */
2129#define MC30 0x4000 /* Enable Mailbox 30 */
2130#define MC31 0x8000 /* Enable Mailbox 31 */
2131
2132/* CAN_MD1 Masks */
2133#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
2134#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
2135#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
2136#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
2137#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
2138#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
2139#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
2140#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
2141#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
2142#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
2143#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
2144#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
2145#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
2146#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
2147#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
2148#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
2149
2150/* CAN_MD2 Masks */
2151#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
2152#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
2153#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
2154#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
2155#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
2156#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
2157#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
2158#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
2159#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
2160#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
2161#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
2162#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
2163#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
2164#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
2165#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
2166#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
2167
2168/* CAN_RMP1 Masks */
2169#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
2170#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
2171#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
2172#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
2173#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
2174#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
2175#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
2176#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
2177#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
2178#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
2179#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
2180#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
2181#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
2182#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
2183#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
2184#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
2185
2186/* CAN_RMP2 Masks */
2187#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
2188#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
2189#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
2190#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
2191#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
2192#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
2193#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
2194#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
2195#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
2196#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
2197#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
2198#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
2199#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
2200#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
2201#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
2202#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2203
2204/* CAN_RML1 Masks */
2205#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2206#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2207#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2208#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2209#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2210#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2211#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2212#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2213#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2214#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2215#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2216#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2217#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2218#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2219#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2220#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2221
2222/* CAN_RML2 Masks */
2223#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2224#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2225#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2226#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2227#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2228#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2229#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2230#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2231#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2232#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2233#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2234#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2235#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2236#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2237#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2238#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2239
2240/* CAN_OPSS1 Masks */
2241#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2242#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2243#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2244#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2245#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2246#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2247#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2248#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2249#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2250#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2251#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2252#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2253#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2254#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2255#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2256#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2257
2258/* CAN_OPSS2 Masks */
2259#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2260#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2261#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2262#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2263#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2264#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2265#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2266#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2267#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2268#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2269#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2270#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2271#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2272#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2273#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2274#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2275
2276/* CAN_TRR1 Masks */
2277#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2278#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2279#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2280#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2281#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2282#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2283#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2284#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2285#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2286#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2287#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2288#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2289#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2290#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2291#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2292#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2293
2294/* CAN_TRR2 Masks */
2295#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2296#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2297#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2298#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2299#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2300#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2301#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2302#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2303#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2304#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2305#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2306#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2307#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2308#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2309#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2310#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2311
2312/* CAN_TRS1 Masks */
2313#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2314#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2315#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2316#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2317#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2318#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2319#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2320#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2321#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2322#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2323#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2324#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2325#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2326#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2327#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2328#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2329
2330/* CAN_TRS2 Masks */
2331#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2332#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2333#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2334#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2335#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2336#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2337#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2338#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2339#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2340#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2341#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2342#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2343#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2344#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2345#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2346#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2347
2348/* CAN_AA1 Masks */
2349#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2350#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2351#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2352#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2353#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2354#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2355#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2356#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2357#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2358#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2359#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2360#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2361#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2362#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2363#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2364#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2365
2366/* CAN_AA2 Masks */
2367#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2368#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2369#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2370#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2371#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2372#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2373#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2374#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2375#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2376#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2377#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2378#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2379#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2380#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2381#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2382#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2383
2384/* CAN_TA1 Masks */
2385#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2386#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2387#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2388#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2389#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2390#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2391#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2392#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2393#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2394#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2395#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2396#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2397#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2398#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2399#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2400#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2401
2402/* CAN_TA2 Masks */
2403#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2404#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2405#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2406#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2407#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2408#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2409#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2410#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2411#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2412#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2413#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2414#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2415#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2416#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2417#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2418#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2419
2420/* CAN_MBTD Masks */
2421#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2422#define TDA 0x0040 /* Temporary Disable Acknowledge */
2423#define TDR 0x0080 /* Temporary Disable Request */
2424
2425/* CAN_RFH1 Masks */
2426#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2427#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2428#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2429#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2430#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2431#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2432#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2433#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2434#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2435#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2436#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2437#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2438#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2439#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2440#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2441#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2442
2443/* CAN_RFH2 Masks */
2444#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2445#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2446#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2447#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2448#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2449#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2450#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2451#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2452#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2453#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2454#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2455#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2456#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2457#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2458#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2459#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2460
2461/* CAN_MBTIF1 Masks */
2462#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2463#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2464#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2465#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2466#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2467#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2468#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2469#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2470#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2471#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2472#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2473#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2474#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2475#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2476#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2477#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2478
2479/* CAN_MBTIF2 Masks */
2480#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2481#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2482#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2483#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2484#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2485#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2486#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2487#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2488#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2489#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2490#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2491#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2492#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2493#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2494#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2495#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2496
2497/* CAN_MBRIF1 Masks */
2498#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2499#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2500#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2501#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2502#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2503#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2504#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2505#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2506#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2507#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2508#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2509#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2510#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2511#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2512#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2513#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2514
2515/* CAN_MBRIF2 Masks */
2516#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2517#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2518#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2519#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2520#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2521#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2522#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2523#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2524#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2525#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2526#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2527#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2528#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2529#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2530#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2531#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2532
2533/* CAN_MBIM1 Masks */
2534#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2535#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2536#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2537#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2538#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2539#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2540#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2541#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2542#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2543#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2544#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2545#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2546#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2547#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2548#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2549#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2550
2551/* CAN_MBIM2 Masks */
2552#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2553#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2554#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2555#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2556#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2557#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2558#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2559#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2560#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2561#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2562#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2563#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2564#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2565#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2566#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2567#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2568
2569/* CAN_GIM Masks */
2570#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2571#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2572#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2573#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2574#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2575#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2576#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2577#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2578#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2579#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2580#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2581
2582/* CAN_GIS Masks */
2583#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2584#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2585#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2586#define BOIS 0x0008 /* Bus Off IRQ Status */
2587#define WUIS 0x0010 /* Wake-Up IRQ Status */
2588#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2589#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2590#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2591#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2592#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2593#define ADIS 0x0400 /* Access Denied IRQ Status */
2594
2595/* CAN_GIF Masks */
2596#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2597#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2598#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2599#define BOIF 0x0008 /* Bus Off IRQ Flag */
2600#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2601#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2602#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2603#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2604#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2605#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2606#define ADIF 0x0400 /* Access Denied IRQ Flag */
2607
2608/* CAN_UCCNF Masks */
2609#define UCCNF 0x000F /* Universal Counter Mode */
2610#define UC_STAMP 0x0001 /* Timestamp Mode */
2611#define UC_WDOG 0x0002 /* Watchdog Mode */
2612#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2613#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2614#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2615#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2616#define UC_AA 0x0009 /* TX Abort Count */
2617#define UC_TA 0x000A /* TX Successful Count */
2618#define UC_REJECT 0x000B /* RX Message Rejected Count */
2619#define UC_RML 0x000C /* RX Message Lost Count */
2620#define UC_RX 0x000D /* Total Successful RX Messages Count */
2621#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2622#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2623#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2624#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2625#define UCE 0x0080 /* Universal Counter Enable */
2626
2627/* CAN_ESR Masks */
2628#define ACKE 0x0004 /* Acknowledge Error */
2629#define SER 0x0008 /* Stuff Error */
2630#define CRCE 0x0010 /* CRC Error */
2631#define SA0 0x0020 /* Stuck At Dominant Error */
2632#define BEF 0x0040 /* Bit Error Flag */
2633#define FER 0x0080 /* Form Error Flag */
2634
2635/* CAN_EWR Masks */
2636#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2637#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2638
2639
2640/* ******************* PIN CONTROL REGISTER MASKS ************************/
2641/* PORT_MUX Masks */
2642#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
2643#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
2644#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
2645
4834826e
JJ		 2646#ifdef _MISRA_RULES
2647#define PJCE(x) (((x)&0x3u)<<1) /* Port J CAN/SPI/SPORT Enable */
2648#else
84132c9d 2649#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
4834826e
JJ		 2650#endif /* _MISRA_RULES */
2651
84132c9d
JJ		 2652#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
2653#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
2654#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2655
2656#define PFDE 0x0008 /* Port F DMA Request Enable */
2657#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
2658#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
2659
2660#define PFTE 0x0010 /* Port F Timer Enable */
2661#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
2662#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
2663
2664#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
2665#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
2666#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
2667
2668#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
2669#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
2670#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
2671
2672#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
2673#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
2674#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
2675
2676#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
2677#define PFFE_TIMER 0x0000 /* Enable TMR2 */
2678#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
2679
2680#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
2681#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
2682#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
2683
2684#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
2685#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
2686#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
2687
2688#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
2689#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
2690#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
2691
2692
2693/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
2694/* HDMAx_CTL Masks */
2695#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
2696#define REP 0x0002 /* HDMA Request Polarity */
2697#define UTE 0x0004 /* Urgency Threshold Enable */
2698#define OIE 0x0010 /* Overflow Interrupt Enable */
2699#define BDIE 0x0020 /* Block Done Interrupt Enable */
2700#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
2701#define DRQ 0x0300 /* HDMA Request Type */
2702#define DRQ_NONE 0x0000 /* No Request */
2703#define DRQ_SINGLE 0x0100 /* Channels Request Single */
2704#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
2705#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
2706#define RBC 0x1000 /* Reload BCNT With IBCNT */
2707#define PS 0x2000 /* HDMA Pin Status */
2708#define OI 0x4000 /* Overflow Interrupt Generated */
2709#define BDI 0x8000 /* Block Done Interrupt Generated */
2710
2711/* entry addresses of the user-callable Boot ROM functions */
2712
2713#define _BOOTROM_RESET 0xEF000000
2714#define _BOOTROM_FINAL_INIT 0xEF000002
2715#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
2716#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
2717#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
2718#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
2719#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
2720#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
2721#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
2722
2723/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2724#define PGDE_UART PFDE_UART
2725#define PGDE_DMA PFDE_DMA
2726#define CKELOW SCKELOW
2727
2728#ifdef _MISRA_RULES
2729#pragma diag(pop)
2730#endif /* _MISRA_RULES */
2731
2732#endif /* _DEF_BF534_H */
2733
newlib and cygwin
This page took 0.309565 seconds and 5 git commands to generate.