git://sourceware.org / newlib-cygwin.git / blame
| Commit | Line | Data |
|---|---|---|
| 4834826e JJ |
1 | /* |
| 2 | * The authors hereby grant permission to use, copy, modify, distribute, | |
| 3 | * and license this software and its documentation for any purpose, provided | |
| 4 | * that existing copyright notices are retained in all copies and that this | |
| 5 | * notice is included verbatim in any distributions. No written agreement, | |
| 6 | * license, or royalty fee is required for any of the authorized uses. | |
| 7 | * Modifications to this software may be copyrighted by their authors | |
| 8 | * and need not follow the licensing terms described here, provided that | |
| 9 | * the new terms are clearly indicated on the first page of each file where | |
| 10 | * they apply. | |
| 11 | */ | |
| 12 | ||
| 13 | /* | |
| 1cfc2fea | 14 | ** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved. |
| 4834826e JJ |
15 | ** |
| 16 | ************************************************************************************ | |
| 17 | ** | |
| 18 | ** This include file contains a list of macro "defines" to enable the programmer | |
| 19 | ** to use symbolic names for register-access and bit-manipulation. | |
| 20 | ** | |
| 21 | **/ | |
| 22 | #ifndef _DEF_BF516_H | |
| 23 | #define _DEF_BF516_H | |
| 24 | ||
| 25 | /* Include all Core registers and bit definitions */ | |
| 26 | #include <def_LPBlackfin.h> | |
| 27 | ||
| 28 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ | |
| 29 | ||
| 30 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | |
| 31 | #include <defBF51x_base.h> | |
| 32 | ||
| 33 | #ifdef _MISRA_RULES | |
| 34 | #pragma diag(push) | |
| 35 | #pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4") | |
| 36 | #pragma diag(suppress:misra_rule_19_7:"Allow function-like macros") | |
| 37 | #endif /* _MISRA_RULES */ | |
| 38 | ||
| 39 | /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ | |
| 40 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | |
| 41 | ||
| 42 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | |
| 43 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | |
| 44 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | |
| 45 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | |
| 46 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | |
| 47 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | |
| 48 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | |
| 49 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | |
| 50 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | |
| 51 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | |
| 52 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | |
| 53 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | |
| 54 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | |
| 55 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | |
| 56 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | |
| 57 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | |
| 58 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | |
| 59 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | |
| 60 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | |
| 61 | ||
| 62 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | |
| 63 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | |
| 64 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | |
| 65 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | |
| 66 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | |
| 67 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | |
| 68 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | |
| 69 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | |
| 70 | ||
| 71 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | |
| 72 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | |
| 73 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | |
| 74 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | |
| 75 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | |
| 76 | ||
| 77 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | |
| 78 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | |
| 79 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | |
| 80 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | |
| 81 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | |
| 82 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | |
| 83 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | |
| 84 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | |
| 85 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | |
| 86 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | |
| 87 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | |
| 88 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | |
| 89 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | |
| 90 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | |
| 91 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | |
| 92 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | |
| 93 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | |
| 94 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | |
| 95 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | |
| 96 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | |
| 97 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | |
| 98 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | |
| 99 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | |
| 100 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | |
| 101 | ||
| 102 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | |
| 103 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | |
| 104 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | |
| 105 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | |
| 106 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | |
| 107 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | |
| 108 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | |
| 109 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | |
| 110 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | |
| 111 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | |
| 112 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | |
| 113 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | |
| 114 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | |
| 115 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | |
| 116 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | |
| 117 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | |
| 118 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | |
| 119 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | |
| 120 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | |
| 121 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | |
| 122 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | |
| 123 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | |
| 124 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | |
| 125 | ||
| 126 | /* Listing for IEEE-Supported Count Registers */ | |
| 127 | ||
| 128 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | |
| 129 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | |
| 130 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | |
| 131 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | |
| 132 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | |
| 133 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | |
| 134 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | |
| 135 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | |
| 136 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | |
| 137 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | |
| 138 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | |
| 139 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | |
| 140 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | |
| 141 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | |
| 142 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | |
| 143 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | |
| 144 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | |
| 145 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | |
| 146 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | |
| 147 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | |
| 148 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | |
| 149 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | |
| 150 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | |
| 151 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | |
| 152 | ||
| 153 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | |
| 154 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | |
| 155 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | |
| 156 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | |
| 157 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | |
| 158 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | |
| 159 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | |
| 160 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | |
| 161 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | |
| 162 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | |
| 163 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | |
| 164 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | |
| 165 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | |
| 166 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | |
| 167 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | |
| 168 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | |
| 169 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | |
| 170 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | |
| 171 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | |
| 172 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | |
| 173 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | |
| 174 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | |
| 175 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | |
| 176 | ||
| 177 | ||
| 178 | /* RSI Registers */ | |
| 179 | ||
| 180 | #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ | |
| 181 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 182 | #define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */ | |
| 183 | #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ | |
| 184 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 185 | #define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */ | |
| 186 | #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ | |
| 187 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 188 | #define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */ | |
| 189 | #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ | |
| 190 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 191 | #define SDH_COMMAND RSI_COMMAND /* SDH Command */ | |
| 192 | #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ | |
| 193 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 194 | #define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */ | |
| 195 | #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ | |
| 196 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 197 | #define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */ | |
| 198 | #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ | |
| 199 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 200 | #define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */ | |
| 201 | #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ | |
| 202 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 203 | #define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */ | |
| 204 | #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ | |
| 205 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 206 | #define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */ | |
| 207 | #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ | |
| 208 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 209 | #define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */ | |
| 210 | #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ | |
| 211 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 212 | #define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */ | |
| 213 | #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ | |
| 214 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 215 | #define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */ | |
| 216 | #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ | |
| 217 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 218 | #define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */ | |
| 219 | #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ | |
| 220 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 221 | #define SDH_STATUS RSI_STATUS /* SDH Status */ | |
| 222 | #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ | |
| 223 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 224 | #define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */ | |
| 225 | #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ | |
| 226 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 227 | #define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */ | |
| 228 | #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ | |
| 229 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 230 | #define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */ | |
| 231 | #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ | |
| 232 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 233 | #define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */ | |
| 234 | #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ | |
| 235 | #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ | |
| 236 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 237 | #define SDH_FIFO RSI_FIFO /* SDH Data FIFO */ | |
| 238 | #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ | |
| 239 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 240 | #define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */ | |
| 241 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ | |
| 242 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 243 | #define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */ | |
| 244 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ | |
| 245 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 246 | #define SDH_CFG RSI_CONFIG /* SDH Configuration */ | |
| 247 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ | |
| 248 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 249 | #define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */ | |
| 250 | #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ | |
| 251 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 252 | #define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */ | |
| 253 | #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ | |
| 254 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 255 | #define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */ | |
| 256 | #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ | |
| 257 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 258 | #define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */ | |
| 259 | #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ | |
| 260 | /* legacy register name (below) provided for backwards code compatibility */ | |
| 261 | #define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */ | |
| 262 | /* RSI Registers */ | |
| 263 | ||
| 264 | ||
| 265 | ||
| 266 | /*********************************************************************************** | |
| 267 | ** System MMR Register Bits And Macros | |
| 268 | ** | |
| 269 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | |
| 270 | ** Use these macros carefully, as any that do left shifts for field | |
| 271 | ** depositing will result in the lower order bits being destroyed. Any | |
| 272 | ** macro that shifts left to properly position the bit-field should be | |
| 273 | ** used as part of an OR to initialize a register and NOT as a dynamic | |
| 274 | ** modifier UNLESS the lower order bits are saved and ORed back in when | |
| 275 | ** the macro is used. | |
| 276 | *************************************************************************************/ | |
| 277 | ||
| 278 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | |
| 279 | ||
| 280 | /* EMAC_OPMODE Masks */ | |
| 281 | ||
| 282 | #define RE 0x00000001 /* Receiver Enable */ | |
| 283 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | |
| 284 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | |
| 285 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | |
| 286 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | |
| 287 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | |
| 288 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | |
| 289 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | |
| 290 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | |
| 291 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | |
| 292 | #define RAF 0x00001000 /* Receive-All Mode */ | |
| 293 | #define TE 0x00010000 /* Transmitter Enable */ | |
| 294 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | |
| 295 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | |
| 296 | #define DC 0x00080000 /* Deferral Check */ | |
| 297 | #define BOLMT 0x00300000 /* Back-Off Limit */ | |
| 298 | #define BOLMT_10 0x00000000 /* 10-bit range */ | |
| 299 | #define BOLMT_8 0x00100000 /* 8-bit range */ | |
| 300 | #define BOLMT_4 0x00200000 /* 4-bit range */ | |
| 301 | #define BOLMT_1 0x00300000 /* 1-bit range */ | |
| 302 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | |
| 303 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | |
| 304 | #define RMII 0x01000000 /* RMII/MII* Mode */ | |
| 305 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | |
| 306 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | |
| 307 | #define LB 0x08000000 /* Internal Loopback Enable */ | |
| 308 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | |
| 309 | ||
| 310 | /* EMAC_STAADD Masks */ | |
| 311 | ||
| 312 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | |
| 313 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | |
| 314 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | |
| 315 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | |
| 316 | #define REGAD 0x000007C0 /* STA Register Address */ | |
| 317 | #define PHYAD 0x0000F800 /* PHY Device Address */ | |
| 318 | ||
| 319 | #ifdef _MISRA_RULES | |
| 320 | #define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */ | |
| 321 | #define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */ | |
| 322 | #else | |
| 323 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | |
| 324 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | |
| 325 | #endif /* _MISRA_RULES */ | |
| 326 | ||
| 327 | /* EMAC_STADAT Mask */ | |
| 328 | ||
| 329 | #define STADATA 0x0000FFFF /* Station Management Data */ | |
| 330 | ||
| 331 | /* EMAC_FLC Masks */ | |
| 332 | ||
| 333 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | |
| 334 | #define FLCE 0x00000002 /* Flow Control Enable */ | |
| 335 | #define PCF 0x00000004 /* Pass Control Frames */ | |
| 336 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | |
| 337 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | |
| 338 | ||
| 339 | #ifdef _MISRA_RULES | |
| 340 | #define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */ | |
| 341 | #else | |
| 342 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | |
| 343 | #endif /* _MISRA_RULES */ | |
| 344 | ||
| 345 | /* EMAC_WKUP_CTL Masks */ | |
| 346 | ||
| 347 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | |
| 348 | #define MPKE 0x00000002 /* Magic Packet Enable */ | |
| 349 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | |
| 350 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | |
| 351 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | |
| 352 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | |
| 353 | ||
| 354 | /* EMAC_WKUP_FFCMD Masks */ | |
| 355 | ||
| 356 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | |
| 357 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | |
| 358 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | |
| 359 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | |
| 360 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | |
| 361 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | |
| 362 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | |
| 363 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | |
| 364 | ||
| 365 | /* EMAC_WKUP_FFOFF Masks */ | |
| 366 | ||
| 367 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | |
| 368 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | |
| 369 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | |
| 370 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | |
| 371 | ||
| 372 | #ifdef _MISRA_RULES | |
| 373 | #define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | |
| 374 | #define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | |
| 375 | #define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | |
| 376 | #define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | |
| 377 | #else | |
| 378 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | |
| 379 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | |
| 380 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | |
| 381 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | |
| 382 | #endif /* _MISRA_RULES */ | |
| 383 | ||
| 384 | /* Set ALL Offsets */ | |
| 385 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | |
| 386 | ||
| 387 | /* EMAC_WKUP_FFCRC0 Masks */ | |
| 388 | ||
| 389 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | |
| 390 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | |
| 391 | ||
| 392 | #ifdef _MISRA_RULES | |
| 393 | #define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | |
| 394 | #define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | |
| 395 | #else | |
| 396 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | |
| 397 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | |
| 398 | #endif /* _MISRA_RULES */ | |
| 399 | ||
| 400 | /* EMAC_WKUP_FFCRC1 Masks */ | |
| 401 | ||
| 402 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | |
| 403 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | |
| 404 | ||
| 405 | #ifdef _MISRA_RULES | |
| 406 | #define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | |
| 407 | #define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | |
| 408 | #else | |
| 409 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | |
| 410 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | |
| 411 | #endif /* _MISRA_RULES */ | |
| 412 | ||
| 413 | /* EMAC_SYSCTL Masks */ | |
| 414 | ||
| 415 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | |
| 416 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | |
| 417 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | |
| 418 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | |
| 419 | ||
| 420 | #ifdef _MISRA_RULES | |
| 421 | #define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */ | |
| 422 | #else | |
| 423 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | |
| 424 | #endif /* _MISRA_RULES */ | |
| 425 | ||
| 426 | /* EMAC_SYSTAT Masks */ | |
| 427 | ||
| 428 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | |
| 429 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | |
| 430 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | |
| 431 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | |
| 432 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | |
| 433 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | |
| 434 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | |
| 435 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | |
| 436 | ||
| 437 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | |
| 438 | ||
| 439 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | |
| 440 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | |
| 441 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | |
| 442 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | |
| 443 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | |
| 444 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | |
| 445 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | |
| 446 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | |
| 447 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | |
| 448 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | |
| 449 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | |
| 450 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | |
| 451 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | |
| 452 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | |
| 453 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | |
| 454 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | |
| 455 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | |
| 456 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | |
| 457 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | |
| 458 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | |
| 459 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | |
| 460 | ||
| 461 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | |
| 462 | ||
| 463 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | |
| 464 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | |
| 465 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | |
| 466 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | |
| 467 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | |
| 468 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | |
| 469 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | |
| 470 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | |
| 471 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | |
| 472 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | |
| 473 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | |
| 474 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | |
| 475 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | |
| 476 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | |
| 477 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | |
| 478 | ||
| 479 | /* EMAC_MMC_CTL Masks */ | |
| 480 | #define RSTC 0x00000001 /* Reset All Counters */ | |
| 481 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | |
| 482 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | |
| 483 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | |
| 484 | ||
| 485 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | |
| 486 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | |
| 487 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | |
| 488 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | |
| 489 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | |
| 490 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | |
| 491 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | |
| 492 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | |
| 493 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | |
| 494 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | |
| 495 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | |
| 496 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | |
| 497 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | |
| 498 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | |
| 499 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | |
| 500 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | |
| 501 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | |
| 502 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | |
| 503 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | |
| 504 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | |
| 505 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | |
| 506 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | |
| 507 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | |
| 508 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | |
| 509 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | |
| 510 | ||
| 511 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | |
| 512 | ||
| 513 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | |
| 514 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | |
| 515 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | |
| 516 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | |
| 517 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | |
| 518 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | |
| 519 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | |
| 520 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | |
| 521 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | |
| 522 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | |
| 523 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | |
| 524 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | |
| 525 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | |
| 526 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | |
| 527 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | |
| 528 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | |
| 529 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | |
| 530 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | |
| 531 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | |
| 532 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | |
| 533 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | |
| 534 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | |
| 535 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | |
| 536 | ||
| 537 | ||
| 538 | /* Bit masks for EMAC_PTP_CTL */ | |
| 539 | ||
| 540 | #define EMAC_PTP_CTL_EN 0x1 /* Block Enable */ | |
| 541 | #define EMAC_PTP_CTL_TL 0x2 /* Time Stamp Lock */ | |
| 542 | #define EMAC_PTP_CTL_CKS 0xC /* Clock source for the PTP_TSYNC block */ | |
| 543 | #define EMAC_PTP_CTL_ASEN 0x10 /* Auxiliary Snapshot Enable */ | |
| 544 | #define EMAC_PTP_CTL_CKDIV 0x60 /* Divider for the selected PTP_CLK output */ | |
| 545 | #define EMAC_PTP_CTL_PPSEN 0x80 /* Pulse Per Second (PPS) Enable */ | |
| 546 | #define EMAC_PTP_CTL_EFTM 0x100 /* Ethernet Frame type field compare mask */ | |
| 547 | #define EMAC_PTP_CTL_IPVM 0x200 /* IP Version field compare mask */ | |
| 548 | #define EMAC_PTP_CTL_IPTM 0x400 /* IP Type Frame field (Layer 4 protocol) compare mask */ | |
| 549 | #define EMAC_PTP_CTL_UDPEM 0x800 /* UDP Event port field compare mask */ | |
| 550 | #define EMAC_PTP_CTL_PTPCM 0x1000 /* PTP Control field compare mask */ | |
| 551 | #define EMAC_PTP_CTL_CKOEN 0x2000 /* Clock output Enable */ | |
| 552 | ||
| 553 | /* Bit masks for EMAC_PTP_IE */ | |
| 554 | ||
| 555 | #define EMAC_PTP_IE_ALIE 0x1 /* Alarm Feature and Interrupt Enable */ | |
| 556 | #define EMAC_PTP_IE_RXEIE 0x2 /* Receive Event Interrupt Enable */ | |
| 557 | #define EMAC_PTP_IE_RXGIE 0x4 /* Receive General Interrupt Enable */ | |
| 558 | #define EMAC_PTP_IE_TXIE 0x8 /* Transmit Interrupt Enable */ | |
| 559 | #define EMAC_PTP_IE_TXOVE 0x10 /* Transmit Overrun Error Interrupt Enable */ | |
| 560 | #define EMAC_PTP_IE_RXOVE 0x20 /* Receive Overrun Error Interrupt Enable */ | |
| 561 | #define EMAC_PTP_IE_ASIE 0x40 /* Auxiliary Snapshot Interrupt Enable */ | |
| 562 | ||
| 563 | /* Bit masks for EMAC_PTP_ISTAT */ | |
| 564 | ||
| 565 | #define EMAC_PTP_ISTAT_ALS 0x1 /* Alarm Status */ | |
| 566 | #define EMAC_PTP_ISTAT_RXEL 0x2 /* Receive Event Interrupt Locked */ | |
| 567 | #define EMAC_PTP_ISTAT_RXGL 0x4 /* Receive General Interrupt Locked */ | |
| 568 | #define EMAC_PTP_ISTAT_TXTL 0x8 /* Transmit Snapshot Locked */ | |
| 569 | #define EMAC_PTP_ISTAT_RXOV 0x10 /* Receive Snapshot Overrun Status */ | |
| 570 | #define EMAC_PTP_ISTAT_TXOV 0x20 /* Transmit snapshot Overrun Status */ | |
| 571 | #define EMAC_PTP_ISTAT_ASL 0x40 /* Auxiliary Snapshot Interrupt Status */ | |
| 572 | ||
| 573 | ||
| 574 | /* Bit masks for RSI_PWR_CONTROL */ | |
| 575 | #define PWR_ON 0x3 /* Power On */ | |
| 576 | #define RSI_CMD_OD 0x40 /* Open Drain Output */ | |
| 577 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 578 | #define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */ | |
| 579 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 580 | #define nSD_CMD_OD 0x0 | |
| 581 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 582 | #if 0 | |
| 583 | #define TBD 0x3c /* TBD */ | |
| 584 | #endif | |
| 585 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 586 | #define ROD_CTL 0x80 | |
| 587 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 588 | #define nROD_CTL 0x80 | |
| 589 | ||
| 590 | ||
| 591 | /* Bit masks for RSI_CLK_CONTROL */ | |
| 592 | #define CLKDIV 0xff /* MC_CLK Divisor */ | |
| 593 | #define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */ | |
| 594 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 595 | #define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */ | |
| 596 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 597 | #define nCLK_E 0x0 | |
| 598 | #define PWR_SV_EN 0x200 /* Power Save Enable */ | |
| 599 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 600 | #define PWR_SV_E PWR_SV_EN /* Power Save Enable */ | |
| 601 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 602 | #define nPWR_SV_E 0x0 | |
| 603 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | |
| 604 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 605 | #define nCLKDIV_BYPASS 0x0 | |
| 606 | #define BUS_MODE 0x1800 /* Bus width selection */ | |
| 607 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 608 | #define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */ | |
| 609 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 610 | #define nWIDE_BUS 0x0 | |
| 611 | ||
| 612 | ||
| 613 | /* Bit masks for RSI_COMMAND */ | |
| 614 | #define CMD_IDX 0x3f /* Command Index */ | |
| 615 | #define CMD_RSP_EN 0x40 /* Response */ | |
| 616 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 617 | #define CMD_RSP CMD_RSP_EN /* Response */ | |
| 618 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 619 | #define nCMD_RSP 0x0 | |
| 620 | #define CMD_LRSP_EN 0x80 /* Long Response */ | |
| 621 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 622 | #define CMD_L_RSP CMD_LRSP_EN /* Long Response */ | |
| 623 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 624 | #define nCMD_L_RSP 0x0 | |
| 625 | #define CMD_INT_EN 0x100 /* Command Interrupt */ | |
| 626 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 627 | #define CMD_INT_E CMD_INT_EN /* Command Interrupt */ | |
| 628 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 629 | #define nCMD_INT_E 0x0 | |
| 630 | #define CMD_PEND_EN 0x200 /* Command Pending */ | |
| 631 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 632 | #define CMD_PEND_E CMD_PEND_EN /* Command Pending */ | |
| 633 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 634 | #define nCMD_PEND_E 0x0 | |
| 635 | #define CMD_EN 0x400 /* Command Enable */ | |
| 636 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 637 | #define CMD_E CMD_EN /* Command Enable */ | |
| 638 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 639 | #define nCMD_E 0x0 | |
| 640 | ||
| 641 | ||
| 642 | /* Bit masks for RSI_RESP_CMD */ | |
| 643 | #define RESP_CMD 0x3f /* Response Command */ | |
| 644 | ||
| 645 | /* Bit masks for RSI_DATA_LGTH */ | |
| 646 | #define DATA_LENGTH 0xffff /* Data Length */ | |
| 647 | ||
| 648 | ||
| 649 | /* Bit masks for RSI_DATA_CONTROL */ | |
| 650 | #define DATA_EN 0x1 /* Data Transfer Enable */ | |
| 651 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 652 | #define DTX_E DATA_EN /* Data Transfer Enable */ | |
| 653 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 654 | #define nDTX_E 0x0 | |
| 655 | #define DATA_DIR 0x2 /* Data Transfer Direction */ | |
| 656 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 657 | #define DTX_DIR DATA_DIR /* Data Transfer Direction */ | |
| 658 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 659 | #define nDTX_DIR 0x0 | |
| 660 | #define DATA_MODE 0x4 /* Data Transfer Mode */ | |
| 661 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 662 | #define DTX_MODE DATA_MODE /* Data Transfer Mode */ | |
| 663 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 664 | #define nDTX_MODE 0x0 | |
| 665 | #define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */ | |
| 666 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 667 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | |
| 668 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 669 | #define nDTX_DMA_E 0x0 | |
| 670 | #define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | |
| 671 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 672 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | |
| 673 | #define CEATA_EN 0x100 /* CE-ATA operation mode enable */ | |
| 674 | #define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */ | |
| 675 | ||
| 676 | /* Bit masks for RSI_DATA_CNT */ | |
| 677 | #define DATA_COUNT 0xffff /* Data Count */ | |
| 678 | ||
| 679 | /* Bit masks for RSI_STATUS */ | |
| 680 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | |
| 681 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 682 | #define nCMD_CRC_FAIL 0x0 | |
| 683 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | |
| 684 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 685 | #define nDAT_CRC_FAIL 0x0 | |
| 686 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ | |
| 687 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 688 | #define nCMD_TIMEOUT 0x0 | |
| 689 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ | |
| 690 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 691 | #define nDAT_TIMEOUT 0x0 | |
| 692 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | |
| 693 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 694 | #define nTX_UNDERRUN 0x0 | |
| 695 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | |
| 696 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 697 | #define nRX_OVERRUN 0x0 | |
| 698 | #define CMD_RESP_END 0x40 /* CMD Response End */ | |
| 699 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 700 | #define nCMD_RESP_END 0x0 | |
| 701 | #define CMD_SENT 0x80 /* CMD Sent */ | |
| 702 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 703 | #define nCMD_SENT 0x0 | |
| 704 | #define DAT_END 0x100 /* Data End */ | |
| 705 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 706 | #define nDAT_END 0x0 | |
| 707 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | |
| 708 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 709 | #define nSTART_BIT_ERR 0x0 | |
| 710 | #define DAT_BLK_END 0x400 /* Data Block End */ | |
| 711 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 712 | #define nDAT_BLK_END 0x0 | |
| 713 | #define CMD_ACT 0x800 /* CMD Active */ | |
| 714 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 715 | #define nCMD_ACT 0x0 | |
| 716 | #define TX_ACT 0x1000 /* Transmit Active */ | |
| 717 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 718 | #define nTX_ACT 0x0 | |
| 719 | #define RX_ACT 0x2000 /* Receive Active */ | |
| 720 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 721 | #define nRX_ACT 0x0 | |
| 722 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | |
| 723 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 724 | #define nTX_FIFO_STAT 0x0 | |
| 725 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | |
| 726 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 727 | #define nRX_FIFO_STAT 0x0 | |
| 728 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | |
| 729 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 730 | #define nTX_FIFO_FULL 0x0 | |
| 731 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | |
| 732 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 733 | #define nRX_FIFO_FULL 0x0 | |
| 734 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | |
| 735 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 736 | #define nTX_FIFO_ZERO 0x0 | |
| 737 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | |
| 738 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 739 | #define nRX_DAT_ZERO 0x0 | |
| 740 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | |
| 741 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 742 | #define nTX_DAT_RDY 0x0 | |
| 743 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | |
| 744 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 745 | #define nRX_FIFO_RDY 0x0 | |
| 746 | ||
| 747 | /* Bit masks for RSI_STATCL */ | |
| 748 | ||
| 749 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | |
| 750 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 751 | #define nCMD_CRC_FAIL_STAT 0x0 | |
| 752 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | |
| 753 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 754 | #define nDAT_CRC_FAIL_STAT 0x0 | |
| 755 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | |
| 756 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 757 | #define nCMD_TIMEOUT_STAT 0x0 | |
| 758 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | |
| 759 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 760 | #define nDAT_TIMEOUT_STAT 0x0 | |
| 761 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | |
| 762 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 763 | #define nTX_UNDERRUN_STAT 0x0 | |
| 764 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | |
| 765 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 766 | #define nRX_OVERRUN_STAT 0x0 | |
| 767 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | |
| 768 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 769 | #define nCMD_RESP_END_STAT 0x0 | |
| 770 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | |
| 771 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 772 | #define nCMD_SENT_STAT 0x0 | |
| 773 | #define DAT_END_STAT 0x100 /* Data End Status */ | |
| 774 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 775 | #define nDAT_END_STAT 0x0 | |
| 776 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | |
| 777 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 778 | #define nSTART_BIT_ERR_STAT 0x0 | |
| 779 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | |
| 780 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 781 | #define nDAT_BLK_END_STAT 0x0 | |
| 782 | ||
| 783 | /* Bit masks for RSI_MASKx */ | |
| 784 | ||
| 785 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | |
| 786 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 787 | #define nCMD_CRC_FAIL_MASK 0x0 | |
| 788 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | |
| 789 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 790 | #define nDAT_CRC_FAIL_MASK 0x0 | |
| 791 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | |
| 792 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 793 | #define nCMD_TIMEOUT_MASK 0x0 | |
| 794 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | |
| 795 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 796 | #define nDAT_TIMEOUT_MASK 0x0 | |
| 797 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | |
| 798 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 799 | #define nTX_UNDERRUN_MASK 0x0 | |
| 800 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | |
| 801 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 802 | #define nRX_OVERRUN_MASK 0x0 | |
| 803 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | |
| 804 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 805 | #define nCMD_RESP_END_MASK 0x0 | |
| 806 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | |
| 807 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 808 | #define nCMD_SENT_MASK 0x0 | |
| 809 | #define DAT_END_MASK 0x100 /* Data End Mask */ | |
| 810 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 811 | #define nDAT_END_MASK 0x0 | |
| 812 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | |
| 813 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 814 | #define nSTART_BIT_ERR_MASK 0x0 | |
| 815 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | |
| 816 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 817 | #define nDAT_BLK_END_MASK 0x0 | |
| 818 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | |
| 819 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 820 | #define nCMD_ACT_MASK 0x0 | |
| 821 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | |
| 822 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 823 | #define nTX_ACT_MASK 0x0 | |
| 824 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | |
| 825 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 826 | #define nRX_ACT_MASK 0x0 | |
| 827 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | |
| 828 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 829 | #define nTX_FIFO_STAT_MASK 0x0 | |
| 830 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | |
| 831 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 832 | #define nRX_FIFO_STAT_MASK 0x0 | |
| 833 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | |
| 834 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 835 | #define nTX_FIFO_FULL_MASK 0x0 | |
| 836 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | |
| 837 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 838 | #define nRX_FIFO_FULL_MASK 0x0 | |
| 839 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | |
| 840 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 841 | #define nTX_FIFO_ZERO_MASK 0x0 | |
| 842 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | |
| 843 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 844 | #define nRX_DAT_ZERO_MASK 0x0 | |
| 845 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | |
| 846 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 847 | #define nTX_DAT_RDY_MASK 0x0 | |
| 848 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | |
| 849 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 850 | #define nRX_FIFO_RDY_MASK 0x0 | |
| 851 | ||
| 852 | /* Bit masks for RSI_FIFO_CNT */ | |
| 853 | #define FIFO_COUNT 0x7fff /* FIFO Count */ | |
| 854 | ||
| 855 | /* Bit masks for RSI_CEATA_CONTROL */ | |
| 856 | #define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */ | |
| 857 | ||
| 858 | /* Bit masks for RSI_ESTAT */ | |
| 859 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | |
| 860 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 861 | #define nSDIO_INT_DET 0x0 | |
| 862 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | |
| 863 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 864 | #define nSD_CARD_DET 0x0 | |
| 865 | #define CEATA_INT_DET 0x20 | |
| 866 | ||
| 867 | /* Bit masks for RSI_EMASK */ | |
| 868 | #define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */ | |
| 869 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 870 | #define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */ | |
| 871 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 872 | #define nSDIO_MSK 0x0 | |
| 873 | #define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */ | |
| 874 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 875 | #define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */ | |
| 876 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 877 | #define nSCD_MSK 0x0 | |
| 878 | #define CEATA_INT_DET_MASK 0x20 | |
| 879 | ||
| 880 | ||
| 881 | /* Bit masks for SDH_CFG */ | |
| 882 | ||
| 883 | /* Left in for backwards compatibility */ | |
| 884 | #define RSI_CLK_EN 0x1 | |
| 885 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 886 | #define CLKS_EN RSI_CLK_EN /* Clocks Enable */ | |
| 887 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 888 | #define nCLKS_EN 0x0 | |
| 889 | #define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */ | |
| 890 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 891 | #define SD4E SDIO4_EN /* SDIO 4-Bit Enable */ | |
| 892 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 893 | #define nSD4E 0x0 | |
| 894 | #define MW_EN 0x8 /* Moving Window Enable */ | |
| 895 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 896 | #define MWE MW_EN /* Moving Window Enable */ | |
| 897 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 898 | #define nMWE 0x0 | |
| 899 | #define RSI_RST 0x10 /* SDMMC Reset */ | |
| 900 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 901 | #define SD_RST RSI_RST /* SDMMC Reset */ | |
| 902 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 903 | #define nSD_RST 0x0 | |
| 904 | #define PU_DAT 0x20 /* Pull-up SD_DAT */ | |
| 905 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 906 | #define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */ | |
| 907 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 908 | #define nPUP_SDDAT 0x0 | |
| 909 | #define PU_DAT3 0x40 /* Pull-up SD_DAT3 */ | |
| 910 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 911 | #define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */ | |
| 912 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 913 | #define nPUP_SDDAT3 0x0 | |
| 914 | #define PD_DAT3 0x80 /* Pull-down SD_DAT3 */ | |
| 915 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 916 | #define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */ | |
| 917 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 918 | #define nPD_SDDAT3 0x0 | |
| 919 | ||
| 920 | ||
| 921 | /* Bit masks for RSI_RD_WAIT_EN */ | |
| 922 | #define SDIO_RWR 0x1 /* Read Wait Request */ | |
| 923 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 924 | #define RWR SDIO_RWR /* Read Wait Request */ | |
| 925 | /* legacy bit mask (below) provided for backwards code compatibility */ | |
| 926 | #define nRWR 0x0 | |
| 927 | ||
| 928 | /* Bit masks for RSI_PIDx */ | |
| 929 | #define RSI_PID 0xff /* RSI Peripheral ID */ | |
| 930 | ||
| 931 | ||
| 932 | #ifdef _MISRA_RULES | |
| 933 | #pragma diag(pop) | |
| 934 | #endif /* _MISRA_RULES */ | |
| 935 | ||
| 936 | #endif /* _DEF_BF516_H */ |