MEP Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
MEP Architecture
This section describes various things about the cgen description of
the MEP architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): msb = 0
ISA description
-
ext_cop1_16 - MeP coprocessor instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
-
ext_cop1_32 - MeP coprocessor instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
-
ext_cop1_48 - MeP coprocessor instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
-
ext_cop1_64 - MeP coprocessor instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
-
ext_core1 - MeP core extension instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
-
mep - MeP core instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
CPU Families
-
mepf - MeP family
Machines:
-
c5 - C5 media engine
Models:
-
mep - MeP media engine processor
-
h1 - H1 media engine
Models:
-
mep - MeP media engine
Models:
Machine variants
c5 - C5 media engine
-
bfd-name: c5
-
isas: mep ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
h1 - H1 media engine
-
bfd-name: h1
-
isas: mep ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
mep - MeP media engine
-
bfd-name: mep
-
isas: mep ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
Model variants
mep - MeP media engine processor
Registers
h-ccr - Coprocessor control registers
-
machines: base
-
bitsize: 32
-
array: [64]
names:
| $ccr0 |
0 |
| $ccr1 |
1 |
| $ccr2 |
2 |
| $ccr3 |
3 |
| $ccr4 |
4 |
| $ccr5 |
5 |
| $ccr6 |
6 |
| $ccr7 |
7 |
| $ccr8 |
8 |
| $ccr9 |
9 |
| $ccr10 |
10 |
| $ccr11 |
11 |
| $ccr12 |
12 |
| $ccr13 |
13 |
| $ccr14 |
14 |
| $ccr15 |
15 |
| $ccr16 |
16 |
| $ccr17 |
17 |
| $ccr18 |
18 |
| $ccr19 |
19 |
| $ccr20 |
20 |
| $ccr21 |
21 |
| $ccr22 |
22 |
| $ccr23 |
23 |
| $ccr24 |
24 |
| $ccr25 |
25 |
| $ccr26 |
26 |
| $ccr27 |
27 |
| $ccr28 |
28 |
| $ccr29 |
29 |
| $ccr30 |
30 |
| $ccr31 |
31 |
| $ccr32 |
32 |
| $ccr33 |
33 |
| $ccr34 |
34 |
| $ccr35 |
35 |
| $ccr36 |
36 |
| $ccr37 |
37 |
| $ccr38 |
38 |
| $ccr39 |
39 |
| $ccr40 |
40 |
| $ccr41 |
41 |
| $ccr42 |
42 |
| $ccr43 |
43 |
| $ccr44 |
44 |
| $ccr45 |
45 |
| $ccr46 |
46 |
| $ccr47 |
47 |
| $ccr48 |
48 |
| $ccr49 |
49 |
| $ccr50 |
50 |
| $ccr51 |
51 |
| $ccr52 |
52 |
| $ccr53 |
53 |
| $ccr54 |
54 |
| $ccr55 |
55 |
| $ccr56 |
56 |
| $ccr57 |
57 |
| $ccr58 |
58 |
| $ccr59 |
59 |
| $ccr60 |
60 |
| $ccr61 |
61 |
| $ccr62 |
62 |
| $ccr63 |
63 |
h-ccr-ivc2 - Coprocessor control registers for ivc2 coprocessor
-
machines: base
-
bitsize: 64
-
array: [64]
names:
| $csar0 |
0 |
| $cc |
1 |
| $cofr0 |
4 |
| $cofr1 |
5 |
| $cofa0 |
6 |
| $cofa1 |
7 |
| $csar1 |
15 |
| $acc0_0 |
16 |
| $acc0_1 |
17 |
| $acc0_2 |
18 |
| $acc0_3 |
19 |
| $acc0_4 |
20 |
| $acc0_5 |
21 |
| $acc0_6 |
22 |
| $acc0_7 |
23 |
| $acc1_0 |
24 |
| $acc1_1 |
25 |
| $acc1_2 |
26 |
| $acc1_3 |
27 |
| $acc1_4 |
28 |
| $acc1_5 |
29 |
| $acc1_6 |
30 |
| $acc1_7 |
31 |
| $ccr0 |
0 |
| $ccr1 |
1 |
| $ccr2 |
2 |
| $ccr3 |
3 |
| $ccr4 |
4 |
| $ccr5 |
5 |
| $ccr6 |
6 |
| $ccr7 |
7 |
| $ccr8 |
8 |
| $ccr9 |
9 |
| $ccr10 |
10 |
| $ccr11 |
11 |
| $ccr12 |
12 |
| $ccr13 |
13 |
| $ccr14 |
14 |
| $ccr15 |
15 |
| $ccr16 |
16 |
| $ccr17 |
17 |
| $ccr18 |
18 |
| $ccr19 |
19 |
| $ccr20 |
20 |
| $ccr21 |
21 |
| $ccr22 |
22 |
| $ccr23 |
23 |
| $ccr24 |
24 |
| $ccr25 |
25 |
| $ccr26 |
26 |
| $ccr27 |
27 |
| $ccr28 |
28 |
| $ccr29 |
29 |
| $ccr30 |
30 |
| $ccr31 |
31 |
h-ccr-w - Coprocessor control registers, pending writes
-
machines: base
-
bitsize: 32
-
array: [64]
h-cr - 32-bit coprocessor registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
| 0 |
0 |
| 1 |
1 |
| 2 |
2 |
| 3 |
3 |
| 4 |
4 |
| 5 |
5 |
| 6 |
6 |
| 7 |
7 |
| 8 |
8 |
| 9 |
9 |
| 10 |
10 |
| 11 |
11 |
| 12 |
12 |
| 13 |
13 |
| 14 |
14 |
| 15 |
15 |
| 16 |
16 |
| 17 |
17 |
| 18 |
18 |
| 19 |
19 |
| 20 |
20 |
| 21 |
21 |
| 22 |
22 |
| 23 |
23 |
| 24 |
24 |
| 25 |
25 |
| 26 |
26 |
| 27 |
27 |
| 28 |
28 |
| 29 |
29 |
| 30 |
30 |
| 31 |
31 |
h-cr-ivc2 - 64-bit coprocessor registers for ivc2 coprocessor
-
machines: base
-
bitsize: 64
-
array: [64]
names:
| 0 |
0 |
| 1 |
1 |
| 2 |
2 |
| 3 |
3 |
| 4 |
4 |
| 5 |
5 |
| 6 |
6 |
| 7 |
7 |
h-cr64 - 64-bit coprocessor registers
-
machines: base
-
bitsize: 64
-
array: [32]
names:
| 0 |
0 |
| 1 |
1 |
| 2 |
2 |
| 3 |
3 |
| 4 |
4 |
| 5 |
5 |
| 6 |
6 |
| 7 |
7 |
| 8 |
8 |
| 9 |
9 |
| 10 |
10 |
| 11 |
11 |
| 12 |
12 |
| 13 |
13 |
| 14 |
14 |
| 15 |
15 |
| 16 |
16 |
| 17 |
17 |
| 18 |
18 |
| 19 |
19 |
| 20 |
20 |
| 21 |
21 |
| 22 |
22 |
| 23 |
23 |
| 24 |
24 |
| 25 |
25 |
| 26 |
26 |
| 27 |
27 |
| 28 |
28 |
| 29 |
29 |
| 30 |
30 |
| 31 |
31 |
h-cr64-w - 64-bit coprocessor registers, pending writes
-
machines: base
-
bitsize: 64
-
array: [32]
h-csr - Control/special registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
| pc |
0 |
| lp |
1 |
| sar |
2 |
| rpb |
4 |
| rpe |
5 |
| rpc |
6 |
| hi |
7 |
| lo |
8 |
| mb0 |
12 |
| me0 |
13 |
| mb1 |
14 |
| me1 |
15 |
| psw |
16 |
| id |
17 |
| tmp |
18 |
| epc |
19 |
| exc |
20 |
| cfg |
21 |
| npc |
23 |
| dbg |
24 |
| depc |
25 |
| opt |
26 |
| rcfg |
27 |
| ccfg |
28 |
| vid |
22 |
h-gpr - General purpose registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
| 0 |
0 |
| 1 |
1 |
| 2 |
2 |
| 3 |
3 |
| 4 |
4 |
| 5 |
5 |
| 6 |
6 |
| 7 |
7 |
| 8 |
8 |
| 9 |
9 |
| 10 |
10 |
| 11 |
11 |
| fp |
8 |
| tp |
13 |
| gp |
14 |
| sp |
15 |
| 12 |
12 |
| 13 |
13 |
| 14 |
14 |
| 15 |
15 |
h-pc - program counter
-
machines: base
-
bitsize: 32
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/