0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0x6 | Rj | Ri |
(sequence () (set vbit (add-oflag Ri Rj 0)) (set cbit (add-cflag Ri Rj 0)) (set Ri (add Ri Rj)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-m4 | f-Ri |
0xa | 0x5 | m4 | Ri |
(sequence () (set vbit (add-oflag Ri m4 0)) (set cbit (add-cflag Ri m4 0)) (set Ri (add Ri m4)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0x7 | Rj | Ri |
(sequence ((WI tmp)) (set tmp (addc Ri Rj cbit)) (set vbit (add-oflag Ri Rj cbit)) (set cbit (add-cflag Ri Rj cbit)) (set Ri tmp) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xa | 0x4 | u4 | Ri |
(sequence () (set vbit (add-oflag Ri u4 0)) (set cbit (add-cflag Ri u4 0)) (set Ri (add Ri u4)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0x2 | Rj | Ri |
(set Ri (add Ri Rj))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-m4 | f-Ri |
0xa | 0x1 | m4 | Ri |
(set Ri (add Ri m4))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xa | 0x0 | u4 | Ri |
(set Ri (add Ri u4))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-s10 |
0xa | 0x3 | s10 |
(set (reg h-gr 15) (add (reg h-gr 15) s10))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0x2 | Rj | Ri |
(sequence () (set Ri (and Ri Rj)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0x6 | Rj | Ri |
(sequence ((QI tmp)) (set QI tmp (and QI (mem QI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set QI (mem QI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-u8 |
0x8 | 0x3 | u8 |
(set ccr (and ccr u8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0x5 | Rj | Ri |
(sequence ((HI tmp)) (set HI tmp (and HI (mem HI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set HI (mem HI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0x4 | Rj | Ri |
(sequence ((WI tmp)) (set WI tmp (and WI (mem WI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set WI (mem WI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xb | 0xa | Rj | Ri |
(sequence ((WI shift)) (set shift (and Rj 31)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (sra Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x9 | u4 | Ri |
(sequence ((WI shift)) (set shift (add u4 16)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (sra Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x8 | u4 | Ri |
(sequence ((WI shift)) (set shift u4) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (sra Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x8 | 0x1 | u4 | Ri |
(set QI (mem QI Ri) (and QI (or QI (sll QI u4 4) 15) (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x8 | 0x0 | u4 | Ri |
(set QI (mem QI Ri) (and QI (or QI u4 240) (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x4 | label9 |
(if cbit (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x4 | label9 |
(delay 1 (if cbit (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x9 | 0x9 | u4 | Ri |
(set QI (mem QI Ri) (xor QI (sll QI u4 4) (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x9 | 0x8 | u4 | Ri |
(set QI (mem QI Ri) (xor QI u4 (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x2 | label9 |
(if zbit (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x2 | label9 |
(delay 1 (if zbit (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xb | label9 |
(if (not (xor vbit nbit)) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xb | label9 |
(delay 1 (if (not (xor vbit nbit)) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xd | label9 |
(if (not (or (xor vbit nbit) zbit)) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xd | label9 |
(delay 1 (if (not (or (xor vbit nbit) zbit)) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xf | label9 |
(if (not (or cbit zbit)) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xf | label9 |
(delay 1 (if (not (or cbit zbit)) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xc | label9 |
(if (or (xor vbit nbit) zbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xc | label9 |
(delay 1 (if (or (xor vbit nbit) zbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xe | label9 |
(if (or cbit zbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xe | label9 |
(delay 1 (if (or cbit zbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0xa | label9 |
(if (xor vbit nbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0xa | label9 |
(delay 1 (if (xor vbit nbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x6 | label9 |
(if nbit (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x5 | label9 |
(if (not cbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x5 | label9 |
(delay 1 (if (not cbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x6 | label9 |
(delay 1 (if nbit (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x3 | label9 |
(if (not zbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x3 | label9 |
(delay 1 (if (not zbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x1 | label9 |
(nop)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x1 | label9 |
(delay 1 (nop))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x9 | label9 |
(if (not vbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x9 | label9 |
(delay 1 (if (not vbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x9 | 0x1 | u4 | Ri |
(set QI (mem QI Ri) (or QI (sll QI u4 4) (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x9 | 0x0 | u4 | Ri |
(set QI (mem QI Ri) (or QI u4 (mem QI Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x7 | label9 |
(if (not nbit) (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x7 | label9 |
(delay 1 (if (not nbit) (set pc label9)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x0 | label9 |
(set pc label9)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x0 | label9 |
(delay 1 (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x8 | 0x9 | u4 | Ri |
(sequence ((QI tmp)) (set tmp (and QI (sll QI u4 4) (mem QI Ri))) (set zbit (eq tmp 0)) (set nbit (lt tmp 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0x8 | 0x8 | u4 | Ri |
(sequence ((QI tmp)) (set tmp (and QI u4 (mem QI Ri))) (set zbit (eq tmp 0)) (set nbit 0))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xe | 0x8 | label9 |
(if vbit (set pc label9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-cc | f-rel9 |
0xf | 0x8 | label9 |
(delay 1 (if vbit (set pc label9)))
0 1 2 3 | 4 | 5 6 7 8 9 10 11 12 13 14 15 |
f-op1 | f-op5 | f-rel12 |
0xd | 0x0 | label12 |
(sequence () (set (reg h-dr 1) (add pc 2)) (set pc label12))
0 1 2 3 | 4 | 5 6 7 8 9 10 11 12 13 14 15 |
f-op1 | f-op5 | f-rel12 |
0xd | 0x1 | label12 |
(delay 1 (sequence () (set (reg h-dr 1) (add pc 4)) (set pc label12)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x1 | Ri |
(sequence () (set (reg h-dr 1) (add pc 2)) (set pc Ri))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0xf | 0x1 | Ri |
(delay 1 (sequence () (set (reg h-dr 1) (add pc 4)) (set pc Ri)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xa | Rj | Ri |
(sequence ((WI tmp1)) (set vbit (sub-oflag Ri Rj 0)) (set cbit (sub-cflag Ri Rj 0)) (set tmp1 (sub Ri Rj)) (sequence () (set zbit (eq tmp1 0)) (set nbit (lt tmp1 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-m4 | f-Ri |
0xa | 0x9 | m4 | Ri |
(sequence ((WI tmp1)) (set vbit (sub-oflag Ri m4 0)) (set cbit (sub-cflag Ri m4 0)) (set tmp1 (sub Ri m4)) (sequence () (set zbit (eq tmp1 0)) (set nbit (lt tmp1 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xa | 0x8 | u4 | Ri |
(sequence ((WI tmp1)) (set vbit (sub-oflag Ri u4 0)) (set cbit (sub-cflag Ri u4 0)) (set tmp1 (sub Ri u4)) (sequence () (set zbit (eq tmp1 0)) (set nbit (lt tmp1 0))))
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 | 24 25 26 27 | 28 29 30 31 |
f-op1 | f-ccc | f-op2 | f-op3 | f-Rjc | f-u4c | f-CRi |
0x9 | ccc | 0xf | 0xd | Rjc | u4c | CRi |
(nop)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 | 24 25 26 27 | 28 29 30 31 |
f-op1 | f-ccc | f-op2 | f-op3 | f-CRj | f-u4c | f-CRi |
0x9 | ccc | 0xf | 0xc | CRj | u4c | CRi |
(nop)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 | 24 25 26 27 | 28 29 30 31 |
f-op1 | f-ccc | f-op2 | f-op3 | f-CRj | f-u4c | f-Ric |
0x9 | ccc | 0xf | 0xe | CRj | u4c | Ric |
(nop)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 | 24 25 26 27 | 28 29 30 31 |
f-op1 | f-ccc | f-op2 | f-op3 | f-CRj | f-u4c | f-Ric |
0x9 | ccc | 0xf | 0xf | CRj | u4c | Ric |
(nop)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x4 | Ri |
(sequence () (set d0bit (lt (reg h-dr 5) 0)) (set d1bit (xor d0bit (lt Ri 0))) (if (ne d0bit 0) (set (reg h-dr 4) 4294967295) (set (reg h-dr 4) 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x5 | Ri |
(sequence () (set d0bit 0) (set d1bit 0) (set (reg h-dr 4) 0))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x6 | Ri |
(sequence ((WI tmp)) (set (reg h-dr 4) (sll (reg h-dr 4) 1)) (if (lt (reg h-dr 5) 0) (set (reg h-dr 4) (add (reg h-dr 4) 1))) (set (reg h-dr 5) (sll (reg h-dr 5) 1)) (if (eq d1bit 1) (sequence () (set tmp (add (reg h-dr 4) Ri)) (set cbit (add-cflag (reg h-dr 4) Ri 0))) (sequence () (set tmp (sub (reg h-dr 4) Ri)) (set cbit (sub-cflag (reg h-dr 4) Ri 0)))) (if (not (xor (xor d0bit d1bit) cbit)) (sequence () (set (reg h-dr 4) tmp) (set (reg h-dr 5) (or (reg h-dr 5) 1)))) (set zbit (eq (reg h-dr 4) 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x7 | Ri |
(sequence ((WI tmp)) (if (eq d1bit 1) (sequence () (set tmp (add (reg h-dr 4) Ri)) (set cbit (add-cflag (reg h-dr 4) Ri 0))) (sequence () (set tmp (sub (reg h-dr 4) Ri)) (set cbit (sub-cflag (reg h-dr 4) Ri 0)))) (if (eq tmp 0) (sequence () (set zbit 1) (set (reg h-dr 4) 0)) (set zbit 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0x6 | 0x0 |
(if (eq zbit 1) (set (reg h-dr 5) (add (reg h-dr 5) 1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0x7 | 0x0 |
(if (eq d1bit 1) (set (reg h-dr 5) (neg (reg h-dr 5))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x0 | 0x8 | dir10 |
(set (reg h-gr 13) (mem WI dir10))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir8 |
0x0 | 0xa | dir8 |
(set (reg h-gr 13) (mem QI dir8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir9 |
0x0 | 0x9 | dir9 |
(set (reg h-gr 13) (mem HI dir9))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x0 | 0xc | dir10 |
(sequence () (set (mem WI (reg h-gr 13)) (mem WI dir10)) (set (reg h-gr 13) (add (reg h-gr 13) 4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir8 |
0x0 | 0xe | dir8 |
(sequence () (set (mem QI (reg h-gr 13)) (mem QI dir8)) (set (reg h-gr 13) (add (reg h-gr 13) 1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir9 |
0x0 | 0xd | dir9 |
(sequence () (set (mem HI (reg h-gr 13)) (mem HI dir9)) (set (reg h-gr 13) (add (reg h-gr 13) 2)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x0 | 0xb | dir10 |
(sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (mem WI dir10)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x1 | 0x8 | dir10 |
(set (mem WI dir10) (reg h-gr 13))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir8 |
0x1 | 0xa | dir8 |
(set (mem QI dir8) (reg h-gr 13))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir9 |
0x1 | 0x9 | dir9 |
(set (mem HI dir9) (reg h-gr 13))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x1 | 0xc | dir10 |
(sequence () (set (mem WI dir10) (mem WI (reg h-gr 13))) (set (reg h-gr 13) (add (reg h-gr 13) 4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir8 |
0x1 | 0xe | dir8 |
(sequence () (set (mem QI dir8) (mem QI (reg h-gr 13))) (set (reg h-gr 13) (add (reg h-gr 13) 1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir9 |
0x1 | 0xd | dir9 |
(sequence () (set (mem HI dir9) (mem HI (reg h-gr 13))) (set (reg h-gr 13) (add (reg h-gr 13) 2)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-dir10 |
0x1 | 0xb | dir10 |
(sequence () (set (mem WI dir10) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-u10 |
0x0 | 0xf | u10 |
(sequence ((WI tmp)) (set tmp (sub (reg h-gr 15) 4)) (set (mem WI tmp) (reg h-gr 14)) (set (reg h-gr 14) tmp) (set (reg h-gr 15) (sub (reg h-gr 15) u10)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0xa | Rj | Ri |
(sequence () (set Ri (xor Ri Rj)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0xe | Rj | Ri |
(sequence ((QI tmp)) (set QI tmp (xor QI (mem QI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set QI (mem QI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0xd | Rj | Ri |
(sequence ((HI tmp)) (set HI tmp (xor HI (mem HI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set HI (mem HI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0xc | Rj | Ri |
(sequence ((WI tmp)) (set WI tmp (xor WI (mem WI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set WI (mem WI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x8 | Ri |
(set Ri (ext WI (and QI Ri 255)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0xa | Ri |
(set Ri (ext WI (and HI Ri 65535)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x9 | Ri |
(set Ri (zext WI (and UQI Ri 255)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0xb | Ri |
(set Ri (zext WI (and UHI Ri 65535)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-u8 |
0x1 | 0xf | u8 |
(sequence () (clobber (reg h-dr 2)) (clobber ibit) (clobber sbit) (set WI pc (c-call WI "fr30_int" pc u8)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0x3 | 0x0 |
(sequence () (clobber (reg h-dr 2)) (clobber ibit) (clobber ilm) (set WI pc (c-call WI "fr30_inte" pc)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0x7 | 0x0 | Ri |
(set pc Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x9 | 0xf | 0x0 | Ri |
(delay 1 (set pc Ri))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x4 | Rj | Ri |
(set Ri (mem WI Rj))
0 1 2 3 | 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | 24 25 26 27 | 28 29 30 31 |
f-op1 | f-i20 | f-op2 | f-Ri |
0x9 | i20 | 0xb | Ri |
(set Ri i20)
0 1 2 3 | 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 | 36 37 38 39 | 40 41 42 43 | 44 45 46 47 |
f-op1 | f-i32 | f-op2 | f-op3 | f-Ri |
0x9 | i32 | 0xf | 0x8 | Ri |
(set Ri i32)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-i8 | f-Ri |
0xc | i8 | Ri |
(set Ri i8)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-reglist_low_ld |
0x8 | 0xc | reglist_low_ld |
(sequence () (if (and reglist_low_ld 1) (sequence () (set (reg h-gr 0) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 2) (sequence () (set (reg h-gr 1) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 4) (sequence () (set (reg h-gr 2) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 8) (sequence () (set (reg h-gr 3) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 16) (sequence () (set (reg h-gr 4) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 32) (sequence () (set (reg h-gr 5) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 64) (sequence () (set (reg h-gr 6) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_low_ld 128) (sequence () (set (reg h-gr 7) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-reglist_hi_ld |
0x8 | 0xd | reglist_hi_ld |
(sequence () (if (and reglist_hi_ld 1) (sequence () (set (reg h-gr 8) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 2) (sequence () (set (reg h-gr 9) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 4) (sequence () (set (reg h-gr 10) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 8) (sequence () (set (reg h-gr 11) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 16) (sequence () (set (reg h-gr 12) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 32) (sequence () (set (reg h-gr 13) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 64) (sequence () (set (reg h-gr 14) (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))) (if (and reglist_hi_ld 128) (set (reg h-gr 15) (mem WI (reg h-gr 15)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x0 | Rj | Ri |
(set Ri (mem WI (add Rj (reg h-gr 13))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x2 | Rj | Ri |
(set Ri (mem UQI (add Rj (reg h-gr 13))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x1 | Rj | Ri |
(set Ri (mem UHI (add Rj (reg h-gr 13))))
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp10 | f-Ri |
0x2 | disp10 | Ri |
(set Ri (mem WI (add disp10 (reg h-gr 14))))
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp8 | f-Ri |
0x6 | disp8 | Ri |
(set Ri (mem UQI (add disp8 (reg h-gr 14))))
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp9 | f-Ri |
0x4 | disp9 | Ri |
(set Ri (mem UHI (add disp9 (reg h-gr 14))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-udisp6 | f-Ri |
0x0 | 0x3 | udisp6 | Ri |
(set Ri (mem WI (add udisp6 (reg h-gr 15))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Rs2 |
0x0 | 0x7 | 0x8 | Rs2 |
(sequence ((WI tmp)) (set tmp (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)) (set Rs2 tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x0 | 0x7 | 0x0 | Ri |
(sequence () (set Ri (mem WI (reg h-gr 15))) (if (ne f-Ri 15) (set (reg h-gr 15) (add (reg h-gr 15) 4))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x0 | 0x7 | 0x9 | 0x0 |
(sequence () (set ps (mem WI (reg h-gr 15))) (set (reg h-gr 15) (add (reg h-gr 15) 4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0xc | u4 | Ri |
(set Ri (add Ri 4))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x6 | Rj | Ri |
(set Ri (mem UQI Rj))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x0 | 0x5 | Rj | Ri |
(set Ri (mem UHI Rj))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0x9 | 0x0 |
(sequence () (set (reg h-gr 15) (add (reg h-gr 14) 4)) (set (reg h-gr 14) (mem WI (sub (reg h-gr 15) 4))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xb | 0x6 | Rj | Ri |
(sequence ((WI shift)) (set shift (and Rj 31)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0)) (set Ri (sll Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x5 | u4 | Ri |
(sequence ((WI shift)) (set shift (add u4 16)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0)) (set Ri (sll Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x4 | u4 | Ri |
(sequence ((WI shift)) (set shift u4) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub 32 shift))) 0)) (set Ri (sll Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xb | 0x2 | Rj | Ri |
(sequence ((WI shift)) (set shift (and Rj 31)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (srl Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x1 | u4 | Ri |
(sequence ((WI shift)) (set shift (add u4 16)) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (srl Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0x0 | u4 | Ri |
(sequence ((WI shift)) (set shift u4) (if (ne shift 0) (sequence () (set cbit (ne (and Ri (sll 1 (sub shift 1))) 0)) (set Ri (srl Ri shift))) (set cbit 0)) (set nbit (lt Ri 0)) (set zbit (eq Ri 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0xb | Rj | Ri |
(set Ri Rj)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rs1 | f-Ri |
0xb | 0x3 | Rs1 | Ri |
(set Rs1 Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x0 | 0x7 | 0x1 | Ri |
(set ps Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rs1 | f-Ri |
0xb | 0x7 | Rs1 | Ri |
(set Ri Rs1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x1 | 0x7 | 0x1 | Ri |
(set Ri ps)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xf | Rj | Ri |
(sequence ((DI tmp)) (set tmp (mul DI (ext DI Rj) (ext DI Ri))) (set (reg h-dr 5) (trunc WI tmp)) (set (reg h-dr 4) (trunc WI (srl tmp 32))) (set nbit (lt (reg h-dr 5) 0)) (set zbit (eq tmp 0)) (set vbit (orif (gt tmp 2147483647) (lt tmp (neg 2147483648)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xb | 0xf | Rj | Ri |
(sequence () (set (reg h-dr 5) (mul (trunc HI Rj) (trunc HI Ri))) (set nbit (lt (reg h-dr 5) 0)) (set zbit (ge (reg h-dr 5) 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xb | Rj | Ri |
(sequence ((DI tmp)) (set tmp (mul DI (zext DI Rj) (zext DI Ri))) (set (reg h-dr 5) (trunc WI tmp)) (set (reg h-dr 4) (trunc WI (srl tmp 32))) (set nbit (lt (reg h-dr 4) 0)) (set zbit (eq (reg h-dr 5) 0)) (set vbit (ne (reg h-dr 4) 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xb | 0xb | Rj | Ri |
(sequence () (set (reg h-dr 5) (mul (and Rj 65535) (and Ri 65535))) (set nbit (lt (reg h-dr 5) 0)) (set zbit (ge (reg h-dr 5) 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0xa | 0x0 |
(nop)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0x2 | Rj | Ri |
(sequence () (set Ri (or Ri Rj)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0x6 | Rj | Ri |
(sequence ((QI tmp)) (set QI tmp (or QI (mem QI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set QI (mem QI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-u8 |
0x9 | 0x3 | u8 |
(set ccr (or ccr u8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0x5 | Rj | Ri |
(sequence ((HI tmp)) (set HI tmp (or HI (mem HI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set HI (mem HI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x9 | 0x4 | Rj | Ri |
(sequence ((WI tmp)) (set WI tmp (or WI (mem WI Ri) Rj)) (sequence () (set zbit (eq tmp 0)) (set nbit (lt tmp 0))) (set WI (mem WI Ri) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0x7 | 0x2 | 0x0 |
(set pc (reg h-dr 1))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0xf | 0x2 | 0x0 |
(delay 1 (set pc (reg h-dr 1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x9 | 0x7 | 0x3 | 0x0 |
(if (eq sbit 0) (sequence () (set UWI pc (mem UWI (reg h-dr 2))) (set (reg h-dr 2) (add (reg h-dr 2) 4)) (set UWI ps (mem UWI (reg h-dr 2))) (set (reg h-dr 2) (add (reg h-dr 2) 4))) (sequence () (set UWI pc (mem UWI (reg h-dr 3))) (set (reg h-dr 3) (add (reg h-dr 3) 4)) (set UWI ps (mem UWI (reg h-dr 3))) (set (reg h-dr 3) (add (reg h-dr 3) 4))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x4 | Rj | Ri |
(set (mem WI Rj) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x6 | Rj | Ri |
(set (mem QI Rj) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x5 | Rj | Ri |
(set (mem HI Rj) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-u8 |
0x8 | 0x7 | u8 |
(set ilm (and u8 31))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-reglist_low_st |
0x8 | 0xe | reglist_low_st |
(sequence () (if (and reglist_low_st 1) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 7)))) (if (and reglist_low_st 2) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 6)))) (if (and reglist_low_st 4) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 5)))) (if (and reglist_low_st 8) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 4)))) (if (and reglist_low_st 16) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 3)))) (if (and reglist_low_st 32) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 2)))) (if (and reglist_low_st 64) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 1)))) (if (and reglist_low_st 128) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 0)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-op2 | f-reglist_hi_st |
0x8 | 0xf | reglist_hi_st |
(sequence () (if (and reglist_hi_st 1) (sequence ((WI save-r15)) (set save-r15 (reg h-gr 15)) (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) save-r15))) (if (and reglist_hi_st 2) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 14)))) (if (and reglist_hi_st 4) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 13)))) (if (and reglist_hi_st 8) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 12)))) (if (and reglist_hi_st 16) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 11)))) (if (and reglist_hi_st 32) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 10)))) (if (and reglist_hi_st 64) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 9)))) (if (and reglist_hi_st 128) (sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) (reg h-gr 8)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x0 | Rj | Ri |
(set (mem WI (add Rj (reg h-gr 13))) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x2 | Rj | Ri |
(set (mem QI (add Rj (reg h-gr 13))) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x1 | 0x1 | Rj | Ri |
(set (mem HI (add Rj (reg h-gr 13))) Ri)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp10 | f-Ri |
0x3 | disp10 | Ri |
(set (mem WI (add disp10 (reg h-gr 14))) Ri)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp8 | f-Ri |
0x7 | disp8 | Ri |
(set (mem QI (add disp8 (reg h-gr 14))) Ri)
0 1 2 3 | 4 5 6 7 8 9 10 11 | 12 13 14 15 |
f-op1 | f-disp9 | f-Ri |
0x5 | disp9 | Ri |
(set (mem HI (add disp9 (reg h-gr 14))) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-udisp6 | f-Ri |
0x1 | 0x3 | udisp6 | Ri |
(set (mem WI (add (reg h-gr 15) udisp6)) Ri)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Rs2 |
0x1 | 0x7 | 0x8 | Rs2 |
(sequence ((WI tmp)) (set tmp Rs2) (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-Ri |
0x1 | 0x7 | 0x0 | Ri |
(sequence ((WI tmp)) (set tmp Ri) (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) tmp))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-op3 | f-op4 |
0x1 | 0x7 | 0x9 | 0x0 |
(sequence () (set (reg h-gr 15) (sub (reg h-gr 15) 4)) (set (mem WI (reg h-gr 15)) ps))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-u4 | f-Ri |
0xb | 0xd | u4 | Ri |
(set Ri (add Ri 4))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xc | Rj | Ri |
(sequence () (set vbit (sub-oflag Ri Rj 0)) (set cbit (sub-cflag Ri Rj 0)) (set Ri (sub Ri Rj)) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xd | Rj | Ri |
(sequence ((WI tmp)) (set tmp (subc Ri Rj cbit)) (set vbit (sub-oflag Ri Rj cbit)) (set cbit (sub-cflag Ri Rj cbit)) (set Ri tmp) (sequence () (set zbit (eq Ri 0)) (set nbit (lt Ri 0))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0xa | 0xe | Rj | Ri |
(set Ri (sub Ri Rj))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-op2 | f-Rj | f-Ri |
0x8 | 0xa | Rj | Ri |
(sequence ((WI tmp)) (set tmp Ri) (set Ri (mem UQI Rj)) (set (mem UQI Rj) tmp))
((emit ldi20 i20 Ri))
((emit ldi32 i32 Ri))
((emit ldi8 i8 Ri))
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/