Bug 29526 - x86: inconsistent suffix recognition in Intel syntax mode
Summary: x86: inconsistent suffix recognition in Intel syntax mode
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: gas (show other bugs)
Version: unspecified
: P2 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
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Depends on:
Blocks:
 
Reported: 2022-08-26 09:25 UTC by Jan Beulich
Modified: 2022-12-12 12:58 UTC (History)
1 user (show)

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Description Jan Beulich 2022-08-26 09:25:02 UTC
While generally insn suffixes are used for sizing in only very few cases for Intel syntax, we've been accepting such forever. But this then needs to be consistent - observe the anomaly for MOVD when assembling

	notw	[rbx]
	notd	[rbx]

	nopw	[rbx]
	nopd	[rbx]

	addw	[rbx], 5
	addd	[rbx], 5

	movw	[rbx], 5
	movd	[rbx], 5

See the v1 posting of a patch addressing this:
https://sourceware.org/pipermail/binutils/2022-August/122458.html
Comment 1 H.J. Lu 2022-08-26 18:21:44 UTC
Intel syntax should specify memory operand size when there is an ambiguity,
instead of relying on suffixes.  I don't think we should make assembler
more complex to allow more suffixes in Intel syntax.
Comment 2 Sourceware Commits 2022-12-12 12:54:11 UTC
The master branch has been updated by Jan Beulich <jbeulich@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=04784e33fabb45c4de7a901587f468d4bc169649

commit 04784e33fabb45c4de7a901587f468d4bc169649
Author: Jan Beulich <jbeulich@suse.com>
Date:   Mon Dec 12 13:51:46 2022 +0100

    x86: re-work insn/suffix recognition
    
    Having templates with a suffix explicitly present has always been
    quirky. Introduce a 2nd matching pass in case the 1st one couldn't find
    a suitable template _and_ didn't itself already need to trim off a
    suffix to find a match at all. This requires error reporting adjustments
    (albeit luckily fewer than I was afraid might be necessary), as errors
    previously reported during matching now need deferring until after the
    2nd pass (because, obviously, we must not emit any error if the 2nd pass
    succeeds). While also related to PR gas/29524, it was requested that
    move-with-sign-extend be left as broken as it always was.
    
    PR gas/29525
    Note that with the dropped CMPSD and MOVSD Intel Syntax string insn
    templates taking operands, mixed IsString/non-IsString template groups
    (with memory operands) cannot occur anymore. With that
    maybe_adjust_templates() becomes unnecessary (and is hence being
    removed).
    
    PR gas/29526
    Note further that while the additions to the intel16 testcase aren't
    really proper Intel syntax, we've been permitting all of those except
    for the MOVD variant. The test therefore is to avoid re-introducing such
    an inconsistency.
Comment 3 Jan Beulich 2022-12-12 12:58:38 UTC
Now done (hopefully there aren't further anomalies).